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10787488
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02/26/2004
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09/01/2005
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11/14/2006
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09/01/2005
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09/19/2006
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12/16/2004
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10/17/2006
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02/03/2005
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04/04/2006
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09/08/2005
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12/20/2005
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08/15/2006
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09/08/2005
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07/04/2006
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05/24/2011
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09/02/2004
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07/05/2005
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10/14/2004
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01/24/2006
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09/15/2005
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10/14/2008
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03/13/2004
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09/15/2005
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04/04/2006
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03/12/2004
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05/05/2005
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08/22/2006
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10801766
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03/16/2004
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01/13/2005
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10/03/2006
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10803852
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03/18/2004
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08/01/2006
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03/19/2004
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04/18/2006
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10804553
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03/19/2004
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09/22/2005
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04/25/2006
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03/23/2004
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09/09/2004
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03/09/2010
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03/25/2004
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09/29/2005
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10/04/2005
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10811860
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03/30/2004
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10/13/2005
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10/30/2007
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03/30/2004
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10/06/2005
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06/12/2007
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03/30/2004
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10/27/2005
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05/28/2013
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03/31/2004
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10/13/2005
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04/01/2008
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10816150
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04/01/2004
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10/06/2005
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11/02/2010
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10816661
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04/02/2004
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09/11/2007
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04/02/2004
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10/13/2005
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04/08/2008
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04/06/2004
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02/24/2009
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04/05/2004
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07/15/2008
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04/06/2004
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10/20/2005
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02/28/2006
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10/13/2005
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05/13/2008
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04/07/2004
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04/08/2008
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04/08/2004
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10/13/2005
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07/11/2006
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04/14/2004
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09/30/2004
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10/20/2005
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09/05/2006
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04/19/2004
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10/20/2005
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07/26/2005
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04/23/2004
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10/07/2004
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08/01/2006
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04/26/2004
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11/18/2004
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07/06/2010
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10/27/2005
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04/11/2006
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04/28/2004
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11/03/2005
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10/05/2010
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04/29/2004
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03/03/2005
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05/02/2006
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04/30/2004
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11/03/2005
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06/12/2007
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04/30/2004
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11/11/2008
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11/10/2005
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07/17/2007
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12/19/2006
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05/04/2004
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11/10/2005
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03/10/2009
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05/06/2004
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11/17/2005
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12/27/2005
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05/06/2004
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11/10/2005
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09/16/2008
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05/10/2004
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11/10/2005
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05/25/2010
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05/10/2004
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05/02/2006
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05/13/2004
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10/21/2004
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10/31/2006
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05/13/2004
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11/17/2005
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07/25/2006
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05/19/2004
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11/25/2004
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07/07/2009
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05/21/2004
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11/14/2006
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05/21/2004
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11/24/2005
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10/03/2006
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05/25/2004
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10/28/2004
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05/06/2008
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Filing Dt:
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05/25/2004
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Publication #:
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Pub Dt:
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12/15/2005
| | | | |
Title:
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MODELING LANGUAGE AND METHOD FOR ADDRESS TRANSLATION DESIGN MECHANISMS IN TEST GENERATION
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Patent #:
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Issue Dt:
|
03/11/2008
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Application #:
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10855047
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Filing Dt:
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05/27/2004
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Publication #:
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Pub Dt:
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12/01/2005
| | | | |
Title:
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METHOD FOR DEFERRED DATA COLLECTION IN A CLOCK RUNNING SYSTEM
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Patent #:
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Issue Dt:
|
03/25/2008
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Application #:
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10855915
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Filing Dt:
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05/27/2004
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Publication #:
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Pub Dt:
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12/23/2004
| | | | |
Title:
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HIGH-QUALITY SGOI BY ANNEALING NEAR THE ALLOY MELTING POINT
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Patent #:
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Issue Dt:
|
06/14/2005
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Application #:
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10856503
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Filing Dt:
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05/28/2004
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Publication #:
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Pub Dt:
|
11/11/2004
| | | | |
Title:
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METHOD TO FABRICATE HIGH-PERFORMANCE NPN TRANSISTORS IN A BICMOS PROCESS
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Patent #:
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Issue Dt:
|
03/07/2006
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Application #:
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10856547
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Filing Dt:
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05/28/2004
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Publication #:
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Pub Dt:
|
12/01/2005
| | | | |
Title:
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INDIRECT SWITCHING AND SENSING OF PHASE CHANGE MEMORY CELLS
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Patent #:
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Issue Dt:
|
11/11/2008
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Application #:
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10858605
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Filing Dt:
|
06/02/2004
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Title:
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FEEDBACK CONTROL OF IMPRINT MASK FEATURE PROFILE USING SCATTEROMETRY AND SPACER ETCHBACK
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Patent #:
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Issue Dt:
|
11/14/2006
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Application #:
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10858739
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Filing Dt:
|
06/01/2004
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Title:
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WAFER LEVEL GLOBAL BITMAP CHARACTERIZATION IN INTEGRATED CIRCUIT TECHNOLOGY DEVELOPMENT
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Patent #:
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Issue Dt:
|
05/29/2007
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Application #:
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10858759
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Filing Dt:
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06/02/2004
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Title:
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IN-SITU DEFECT MONITOR AND CONTROL SYSTEM FOR IMMERSION MEDIUM IN IMMERSION LITHOGRAPHY
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Patent #:
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Issue Dt:
|
04/29/2008
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Application #:
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10858791
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Filing Dt:
|
06/02/2004
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Title:
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METHOD FOR OPTIMIZING LOOP CONTROL OF MICROCODED INSTRUCTIONS
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Patent #:
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Issue Dt:
|
09/09/2008
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Application #:
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10859276
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Filing Dt:
|
06/02/2004
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Title:
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OPTICAL PROXIMITY CORRECTION (OPC) TECHNIQUE TO COMPENSATE FOR FLARE
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Patent #:
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Issue Dt:
|
08/14/2007
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Application #:
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10859673
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Filing Dt:
|
06/03/2004
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Title:
|
METHODS AND FIXTURE FOR COUPLING A LID TO A SUPPORT SUBSTRATE
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Patent #:
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|
Issue Dt:
|
02/08/2011
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Application #:
|
10860966
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Filing Dt:
|
06/04/2004
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Title:
|
MUTI-GIGABIT PER SECOND CONCURRENT ENCRYPTION IN BLOCK CIPHER MODES
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|
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Patent #:
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Issue Dt:
|
02/13/2007
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Application #:
|
10862518
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Filing Dt:
|
06/07/2004
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Publication #:
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Pub Dt:
|
05/05/2005
| | | | |
Title:
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TECHNIQUE FOR FORMING TRANSISTORS HAVING RAISED DRAIN AND SOURCE REGIONS WITH DIFFERENT HEIGHTS
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Patent #:
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Issue Dt:
|
07/26/2005
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Application #:
|
10864238
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Filing Dt:
|
06/09/2004
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Publication #:
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Pub Dt:
|
01/13/2005
| | | | |
Title:
|
COMPLEMENTARY TWO TRANSISTOR ROM CELL
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Patent #:
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Issue Dt:
|
05/31/2005
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Application #:
|
10865138
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Filing Dt:
|
06/10/2004
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Publication #:
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Pub Dt:
|
11/11/2004
| | | | |
Title:
|
DIFFUSED EXTRINSIC BASE AND METHOD FOR FABRICATION
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Patent #:
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|
Issue Dt:
|
10/24/2006
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Application #:
|
10865920
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Filing Dt:
|
06/14/2004
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Publication #:
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Pub Dt:
|
12/15/2005
| | | | |
Title:
|
MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER
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Patent #:
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Issue Dt:
|
08/05/2008
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Application #:
|
10867094
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Filing Dt:
|
06/14/2004
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Publication #:
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Pub Dt:
|
12/15/2005
| | | | |
Title:
|
MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT
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Patent #:
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Issue Dt:
|
08/05/2008
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Application #:
|
10867302
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Filing Dt:
|
06/14/2004
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Publication #:
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Pub Dt:
|
12/02/2004
| | | | |
Title:
|
SYSTEM FOR FACILITATING COVERAGE FEEDBACK TESTCASE GENERATION REPRODUCIBILITY
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|
Patent #:
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Issue Dt:
|
09/04/2007
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Application #:
|
10867772
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Filing Dt:
|
06/16/2004
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Publication #:
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Pub Dt:
|
01/06/2005
| | | | |
Title:
|
METHOD OF FABRICATING SEMICONDUCTOR SIDE WALL FIN
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Patent #:
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|
Issue Dt:
|
12/05/2006
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Application #:
|
10868791
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Filing Dt:
|
06/17/2004
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Publication #:
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Pub Dt:
|
11/25/2004
| | | | |
Title:
|
METHOD FOR MANUFACTURING DEVICE SUBSTRATE WITH METAL BACK-GATE AND STRUCTURE FORMED THEREBY
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Patent #:
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Issue Dt:
|
06/20/2006
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Application #:
|
10869624
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Filing Dt:
|
06/16/2004
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Publication #:
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Pub Dt:
|
11/11/2004
| | | | |
Title:
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IMPLANTED ASYMMETRIC DOPED POLYSILICON GATE FINFET
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Patent #:
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|
Issue Dt:
|
10/09/2007
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Application #:
|
10869658
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Filing Dt:
|
06/16/2004
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Publication #:
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Pub Dt:
|
12/22/2005
| | | | |
Title:
|
HIGH-TEMPERATURE STABLE GATE STRUCTURE WITH METALLIC ELECTRODE
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|
|
Patent #:
|
|
Issue Dt:
|
01/08/2013
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Application #:
|
10870318
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Filing Dt:
|
06/17/2004
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Title:
|
NETWORK INTERFACE SYSTEMS AND METHODS FOR OFFLOADING SEGMENTATION AND/OR CHECKSUMMING WITH SECURITY PROCESSING
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Patent #:
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Issue Dt:
|
06/20/2006
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Application #:
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10872173
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Filing Dt:
|
06/18/2004
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Publication #:
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Pub Dt:
|
11/18/2004
| | | | |
Title:
|
MOS ANTIFUSE WITH LOW POST-PROGRAM RESISTANCE
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Patent #:
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Issue Dt:
|
01/30/2007
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Application #:
|
10872707
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Filing Dt:
|
06/21/2004
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Title:
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STRAINED SILICON MOSFET HAVING IMPROVED SOURCE/DRAIN EXTENSION DOPANT DIFFUSION RESISTANCE AND METHOD FOR ITS FABRICATION
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Patent #:
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Issue Dt:
|
05/29/2007
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Application #:
|
10873240
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Filing Dt:
|
06/23/2004
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Title:
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MULTI-CHANNEL TRANSISTOR WITH TUNABLE HOT CARRIER EFFECT
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Patent #:
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Issue Dt:
|
07/29/2008
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Application #:
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10873672
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Filing Dt:
|
06/22/2004
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Publication #:
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Pub Dt:
|
12/22/2005
| | | | |
Title:
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REDUCING POWER CONSUMPTION IN SIGNAL DETECTION
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Patent #:
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Issue Dt:
|
10/03/2006
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Application #:
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10873733
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Filing Dt:
|
06/22/2004
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Publication #:
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Pub Dt:
|
12/22/2005
| | | | |
Title:
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METHOD OF FORMING METAL/HIGH-K GATE STACKS WITH HIGH MOBILITY
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Patent #:
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Issue Dt:
|
10/09/2007
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Application #:
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10875699
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Filing Dt:
|
06/24/2004
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Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
Title:
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COMMON CARRIER
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Patent #:
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Issue Dt:
|
03/06/2007
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Application #:
|
10875727
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Filing Dt:
|
06/24/2004
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Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
COMPRESSIVE SIGE <110> GROWTH AND STRUCTURE OF MOSFET DEVICES
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Patent #:
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Issue Dt:
|
11/29/2005
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Application #:
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10879833
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Filing Dt:
|
06/29/2004
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Title:
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DUAL GATED FINFET GAIN CELL
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Patent #:
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Issue Dt:
|
09/16/2008
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Application #:
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10880853
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Filing Dt:
|
06/30/2004
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Publication #:
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Pub Dt:
|
01/05/2006
| | | | |
Title:
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METHOD, SYSTEM AND PROGRAM PRODUCT FOR PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING INCOMPLETELY SPECIFIED CONFIGURATION ENTITIES
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Patent #:
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Issue Dt:
|
12/27/2011
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Application #:
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10881932
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Filing Dt:
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06/30/2004
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Publication #:
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Pub Dt:
|
02/03/2005
| | | | |
Title:
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METHOD OF IMPROVING THE WAFER-TO-WAFER THICKNESS UNIFORMITY OF SILICON NITRIDE LAYERS
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Patent #:
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Issue Dt:
|
11/21/2006
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Application #:
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10883392
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Filing Dt:
|
07/01/2004
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Publication #:
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Pub Dt:
|
01/05/2006
| | | | |
Title:
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APPARATUS AND METHODS FOR MICROCHANNEL COOLING OF SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGES
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Patent #:
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Issue Dt:
|
02/06/2007
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Application #:
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10883887
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Filing Dt:
|
07/02/2004
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Publication #:
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Pub Dt:
|
01/05/2006
| | | | |
Title:
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STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED P+ SILICON GERMANIUM LAYER
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Patent #:
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Issue Dt:
|
04/27/2010
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Application #:
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10885462
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Filing Dt:
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07/06/2004
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Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
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METHODS FOR THE FORMATION OF FULLY SILICIDED METAL GATES
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Patent #:
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Issue Dt:
|
11/02/2010
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Application #:
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10887069
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Filing Dt:
|
07/08/2004
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Title:
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DATA PROCESSOR HAVING A CACHE WITH EFFICIENT STORAGE OF PREDECODE INFORMATION, CACHE, AND METHOD
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Patent #:
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Issue Dt:
|
10/10/2006
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Application #:
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10887087
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Filing Dt:
|
07/09/2004
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Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
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COPPER CONDUCTOR
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Patent #:
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Issue Dt:
|
12/13/2005
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Application #:
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10887983
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Filing Dt:
|
07/08/2004
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Title:
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QUASI-STATIC RANDOM ACCESS MEMORY
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Patent #:
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|
Issue Dt:
|
08/06/2013
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Application #:
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10890649
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Filing Dt:
|
07/14/2004
|
Title:
|
Network interface with secondary data and packet information storage and memory control systems to accommodate out-of-order data processing and split transactions on a host system bus
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Patent #:
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Issue Dt:
|
03/25/2008
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Application #:
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10892211
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Filing Dt:
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07/16/2004
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Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
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|