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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
1
Patent #:
Issue Dt:
08/01/2006
Application #:
10787488
Filing Dt:
02/26/2004
Publication #:
Pub Dt:
09/01/2005
Title:
INTEGRATED CIRCUIT LOGIC WITH SELF COMPENSATING BLOCK DELAYS
2
Patent #:
Issue Dt:
11/14/2006
Application #:
10787640
Filing Dt:
02/26/2004
Publication #:
Pub Dt:
09/01/2005
Title:
INTEGRATED CIRCUIT CHIP UTILIZING CARBON NANOTUBE COMPOSITE INTERCONNECTION VIAS
3
Patent #:
Issue Dt:
09/19/2006
Application #:
10787738
Filing Dt:
02/25/2004
Publication #:
Pub Dt:
12/16/2004
Title:
METHOD OF FABRICATING A SHIFTABLE MAGNETIC SHIFT REGISTER
4
Patent #:
Issue Dt:
10/17/2006
Application #:
10790567
Filing Dt:
03/01/2004
Title:
PATTERNING WITH RIGID ORGANIC UNDER-LAYER
5
Patent #:
Issue Dt:
02/24/2009
Application #:
10790852
Filing Dt:
03/02/2004
Publication #:
Pub Dt:
02/03/2005
Title:
FIELD EFFECT TRANSISTOR HAVING A DOPED GATE ELECTRODE WITH REDUCED GATE DEPLETION AND METHOD OF FORMING THE TRANSISTOR
6
Patent #:
Issue Dt:
04/04/2006
Application #:
10791094
Filing Dt:
03/01/2004
Title:
TRENCHES TO REDUCE LATERAL SILICIDE GROWTH IN INTEGRATED CIRCUIT TECHNOLOGY
7
Patent #:
Issue Dt:
01/13/2009
Application #:
10791175
Filing Dt:
03/02/2004
Publication #:
Pub Dt:
09/08/2005
Title:
METHOD FOR PROVIDING AUTOMATIC ADAPTATION TO FREQUENCY OFFSETS IN HIGH SPEED SERIAL LINKS
8
Patent #:
Issue Dt:
12/20/2005
Application #:
10791263
Filing Dt:
03/02/2004
Title:
LITHOGRAPHY METHOD AND SYSTEM WITH ADJUSTABLE REFLECTOR
9
Patent #:
Issue Dt:
08/15/2006
Application #:
10791759
Filing Dt:
03/04/2004
Publication #:
Pub Dt:
09/08/2005
Title:
METHOD OF REDUCING STI DIVOT FORMATION DURING SEMICONDUCTOR DEVICE FABRICATION
10
Patent #:
Issue Dt:
07/04/2006
Application #:
10791904
Filing Dt:
03/04/2004
Title:
COMPOSITE TANTALUM CAPPED INLAID COPPER WITH REDUCED ELECTROMIGRATION AND REDUCED STRESS MIGRATION
11
Patent #:
Issue Dt:
05/24/2011
Application #:
10791914
Filing Dt:
03/03/2004
Title:
METHOD OF GENERATING PACKETS WITHOUT REPETITION IN VERIFICATION OF A DEVICE
12
Patent #:
Issue Dt:
04/05/2005
Application #:
10796731
Filing Dt:
03/09/2004
Publication #:
Pub Dt:
09/02/2004
Title:
DOPING METHODS FOR FULLY-DEPLETED SOI STRUCTURES, AND DEVICE COMPRISING THE RESULTING DOPED REGIONS
13
Patent #:
Issue Dt:
07/05/2005
Application #:
10797878
Filing Dt:
03/10/2004
Publication #:
Pub Dt:
10/14/2004
Title:
METHOD, SYSTEM AND PROGRAM PRODUCTS FOR OPERATIONALLY MIGRATING A CLUSTER THROUGH EMULATION
14
Patent #:
Issue Dt:
01/24/2006
Application #:
10798907
Filing Dt:
03/11/2004
Publication #:
Pub Dt:
09/15/2005
Title:
METHOD OF FORMING FINFET GATES WITHOUT LONG ETCHES
15
Patent #:
Issue Dt:
10/14/2008
Application #:
10799282
Filing Dt:
03/13/2004
Publication #:
Pub Dt:
09/15/2005
Title:
METHOD FOR FABRICATING DUAL DAMASCENE STRUCTURES USING PHOTO-IMPRINT LITHOGRAPHY, METHODS FOR FABRICATING IMPRINT LITHOGRAPHY MOLDS FOR DUAL DAMASCENE STRUCTURES, MATERIALS FOR IMPRINTABLE DIELECTRICS AND EQUIPMENT FOR PHOTO-IMPRINT LITHOGRAPHY USED IN DUAL DAMASCE
16
Patent #:
Issue Dt:
04/04/2006
Application #:
10799380
Filing Dt:
03/12/2004
Publication #:
Pub Dt:
05/05/2005
Title:
CMOS ON HYBRID SUBSTRATE WITH DIFFERENT CRYSTAL ORIENTATIONS USING SILICON-TO-SILICON DIRECT WAFER BONDING
17
Patent #:
Issue Dt:
08/22/2006
Application #:
10801766
Filing Dt:
03/16/2004
Publication #:
Pub Dt:
01/13/2005
Title:
HYDRAZINE-FREE SOLUTION DEPOSITION OF CHALCOGENIDE FILMS
18
Patent #:
Issue Dt:
10/03/2006
Application #:
10803852
Filing Dt:
03/18/2004
Title:
METHOD OF ULTRA-LOW ENERGY ION IMPLANTATION TO FORM ALLOY LAYERS IN COPPER
19
Patent #:
Issue Dt:
08/01/2006
Application #:
10804308
Filing Dt:
03/19/2004
Title:
LOCATION-BASED REMINDERS
20
Patent #:
Issue Dt:
04/18/2006
Application #:
10804553
Filing Dt:
03/19/2004
Publication #:
Pub Dt:
09/22/2005
Title:
METHOD FOR FABRICATING A SELF-ALIGNED NANOCOLUMNAR AIRBRIDGE AND STRUCTURE PRODUCED THEREBY
21
Patent #:
Issue Dt:
04/25/2006
Application #:
10806117
Filing Dt:
03/23/2004
Publication #:
Pub Dt:
09/09/2004
Title:
ENGINEERED METAL GATE ELECTRODE
22
Patent #:
Issue Dt:
03/09/2010
Application #:
10809229
Filing Dt:
03/25/2004
Publication #:
Pub Dt:
09/29/2005
Title:
FOUR LAYER ARCHITECTURE FOR NETWORK DEVICE DRIVERS
23
Patent #:
Issue Dt:
10/04/2005
Application #:
10811860
Filing Dt:
03/30/2004
Publication #:
Pub Dt:
10/13/2005
Title:
CU INTERCONNECTS WITH COMPOSITE BARRIER LAYERS FOR WAFER-TO-WAFER UNIFORMITY
24
Patent #:
Issue Dt:
10/30/2007
Application #:
10813351
Filing Dt:
03/30/2004
Publication #:
Pub Dt:
10/06/2005
Title:
SELECTIVE SHIELD/MATERIAL FLOW MECHANISM
25
Patent #:
Issue Dt:
06/12/2007
Application #:
10813519
Filing Dt:
03/30/2004
Publication #:
Pub Dt:
10/27/2005
Title:
METHOD FOR A VOIDING ALIASED TOKENS DURING ABNORMAL COMMUNICATIONS
26
Patent #:
Issue Dt:
05/28/2013
Application #:
10814482
Filing Dt:
03/31/2004
Publication #:
Pub Dt:
10/13/2005
Title:
METHOD FOR FABRICATING STRAINED SILICON-ON-INSULATOR STRUCTURES AND STRAINED SILICON-ON INSULATOR STRUCTURES FORMED THEREBY
27
Patent #:
Issue Dt:
04/01/2008
Application #:
10816150
Filing Dt:
04/01/2004
Publication #:
Pub Dt:
10/06/2005
Title:
SYSTEM AND METHOD FOR AUTOMATIC SELECTION OF TRANSMISSION LINE MACROMODELS
28
Patent #:
Issue Dt:
11/02/2010
Application #:
10816661
Filing Dt:
04/02/2004
Title:
METHODS AND APPARATUS FOR PASSING INITIALIZATION VECTOR INFORMATION FROM SOFTWARE TO HARDWARE TO PERFORM IPSEC ENCRYPTION OPERATION
29
Patent #:
Issue Dt:
09/11/2007
Application #:
10816764
Filing Dt:
04/02/2004
Publication #:
Pub Dt:
10/13/2005
Title:
SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE DESIGN AND MANUFACTURE USING OPTICAL RULE CHECKING TO SCREEN RESOLUTION ENHANCEMENT TECHNIQUES
30
Patent #:
Issue Dt:
04/08/2008
Application #:
10817811
Filing Dt:
04/06/2004
Title:
OFDM RECEIVER HAVING ADAPTIVE CHANNEL ESTIMATOR FOR CORRECTING CHANNEL FADING BASED ON ACCUMULATED PSEUDO POWER VALUES
31
Patent #:
Issue Dt:
02/24/2009
Application #:
10818155
Filing Dt:
04/05/2004
Title:
DISPOSABLE SPACER PROCESS FOR FIELD EFFECT TRANSISTOR FABRICATION
32
Patent #:
Issue Dt:
07/15/2008
Application #:
10818567
Filing Dt:
04/06/2004
Publication #:
Pub Dt:
10/20/2005
Title:
METHOD AND SYSTEM FOR THE COMPRESSION OF PROBABILITY TABLES
33
Patent #:
Issue Dt:
02/28/2006
Application #:
10819441
Filing Dt:
04/07/2004
Publication #:
Pub Dt:
10/13/2005
Title:
SEMICONDUCTOR ON INSULATOR SUBSTRATE AND DEVICES FORMED THEREFROM
34
Patent #:
Issue Dt:
05/13/2008
Application #:
10819451
Filing Dt:
04/07/2004
Title:
METHOD AND APPARATUS FOR FILTERING MEMORY WRITE SNOOP ACTIVITY IN A DISTRIBUTED SHARED MEMORY COMPUTER
35
Patent #:
Issue Dt:
04/08/2008
Application #:
10821044
Filing Dt:
04/08/2004
Publication #:
Pub Dt:
10/13/2005
Title:
APPARATUS, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MONITORING AND CONTROLLING A MICROCOMPUTER USING A SINGLE EXISTING PIN
36
Patent #:
Issue Dt:
07/11/2006
Application #:
10824289
Filing Dt:
04/14/2004
Publication #:
Pub Dt:
09/30/2004
Title:
METHOD OF CREATING HIGH-QUALITY RELAXED SIGE-ON-INSULATOR FOR STRAINED SI CMOS APPLICATIONS
37
Patent #:
Issue Dt:
01/09/2007
Application #:
10827230
Filing Dt:
04/20/2004
Publication #:
Pub Dt:
10/20/2005
Title:
METHOD AND STRUCTURE FOR VARIABLE PITCH MICROWAVE PROBE ASSEMBLY
38
Patent #:
Issue Dt:
09/05/2006
Application #:
10827693
Filing Dt:
04/19/2004
Publication #:
Pub Dt:
10/20/2005
Title:
STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTIRIC AND DIELECTRIC CAPPING LAYER
39
Patent #:
Issue Dt:
07/26/2005
Application #:
10830006
Filing Dt:
04/23/2004
Publication #:
Pub Dt:
10/07/2004
Title:
NARROW FIN FINFET
40
Patent #:
Issue Dt:
08/01/2006
Application #:
10832217
Filing Dt:
04/26/2004
Publication #:
Pub Dt:
11/18/2004
Title:
HIGH SPEED COMPOSITE P-CHANNEL SI/SIGE HETEROSTRUCTURE FOR FIELD EFFECT DEVICES
41
Patent #:
Issue Dt:
07/06/2010
Application #:
10832658
Filing Dt:
04/27/2004
Publication #:
Pub Dt:
10/27/2005
Title:
ASYNCHRONOUS PACKET BASED DUAL PORT LINK LIST HEADER AND DATA CREDIT MANAGEMENT STRUCTURE
42
Patent #:
Issue Dt:
04/11/2006
Application #:
10833651
Filing Dt:
04/28/2004
Publication #:
Pub Dt:
11/03/2005
Title:
DEVICE AND METHOD FOR DETERMINING AN ILLUMINATION INTENSITY PROFILE OF AN ILLUMINATOR FOR A LITHOGRAPHY SYSTEM
43
Patent #:
Issue Dt:
10/05/2010
Application #:
10835411
Filing Dt:
04/29/2004
Publication #:
Pub Dt:
03/03/2005
Title:
METHOD OF FORMING A TEOS CAP LAYER AT LOW TEMPERATURE AND REDUCED DEPOSITION RATE
44
Patent #:
Issue Dt:
05/02/2006
Application #:
10835814
Filing Dt:
04/30/2004
Publication #:
Pub Dt:
11/03/2005
Title:
NON-PLANARIZED, SELF-ALIGNED, NON-VOLATILE PHASE-CHANGE MEMORY ARRAY AND METHOD OF FORMATION
45
Patent #:
Issue Dt:
06/12/2007
Application #:
10837395
Filing Dt:
04/30/2004
Title:
SPEED VERIFICATION OF AN EMBEDDED PROCESSOR IN A PROGRAMMABLE LOGIC DEVICE
46
Patent #:
Issue Dt:
11/11/2008
Application #:
10838378
Filing Dt:
05/04/2004
Publication #:
Pub Dt:
11/10/2005
Title:
SELF-ALIGNED METAL TO FORM CONTACTS TO GE CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY
47
Patent #:
Issue Dt:
07/17/2007
Application #:
10839072
Filing Dt:
05/05/2004
Title:
EFFICIENT MEMORY CHECK ARCHITECTURE AND METHOD
48
Patent #:
Issue Dt:
12/19/2006
Application #:
10839437
Filing Dt:
05/04/2004
Title:
CONVERSION OF TRANSITION METAL TO SILICIDE THROUGH BACK END PROCESSING IN INTEGRATED CIRCUIT TECHNOLOGY
49
Patent #:
Issue Dt:
08/28/2007
Application #:
10839474
Filing Dt:
05/05/2004
Publication #:
Pub Dt:
11/10/2005
Title:
SYSTEM AND METHOD FOR VALIDATING A MEMORY FILE THAT LINKS SPECULATIVE RESULTS OF LOAD OPERATIONS TO REGISTER VALUES
50
Patent #:
Issue Dt:
03/10/2009
Application #:
10839872
Filing Dt:
05/06/2004
Publication #:
Pub Dt:
11/17/2005
Title:
NETWORK INTERFACE WITH SECURITY ASSOCIATION DATA PREFETCH FOR HIGH SPEED OFFLOADED SECURITY PROCESSING
51
Patent #:
Issue Dt:
12/27/2005
Application #:
10840561
Filing Dt:
05/06/2004
Publication #:
Pub Dt:
11/10/2005
Title:
CIRCUIT FOR COMPENSATING CHARGE LEAKAGE IN A LOW PASS FILTER CAPACITOR OF PLL SYSTEMS
52
Patent #:
Issue Dt:
09/16/2008
Application #:
10842085
Filing Dt:
05/10/2004
Publication #:
Pub Dt:
11/10/2005
Title:
DESIGN VERIFICATION OF HIGHLY OPTIMIZED SYNCHRONOUS PIPELINES VIA RANDOM SIMULATION DRIVEN BY CRITICAL RESOURCE SCHEDULING
53
Patent #:
Issue Dt:
05/25/2010
Application #:
10843255
Filing Dt:
05/10/2004
Title:
MEDIA ACCELERATOR INTERFACE API
54
Patent #:
Issue Dt:
05/02/2006
Application #:
10844533
Filing Dt:
05/13/2004
Publication #:
Pub Dt:
10/21/2004
Title:
COPPER TO ALUMINUM INTERLAYER INTERCONNECT USING STUD AND VIA LINER
55
Patent #:
Issue Dt:
10/31/2006
Application #:
10844794
Filing Dt:
05/13/2004
Publication #:
Pub Dt:
11/17/2005
Title:
FAST AND ACCURATE OPTICAL PROXIMITY CORRECTION ENGINE FOR INCORPORATING LONG RANGE FLARE EFFECTS
56
Patent #:
Issue Dt:
07/25/2006
Application #:
10849459
Filing Dt:
05/19/2004
Publication #:
Pub Dt:
11/25/2004
Title:
SELF-ALIGNED CORROSION STOP FOR COPPER C4 AND WIREBOND
57
Patent #:
Issue Dt:
07/07/2009
Application #:
10849847
Filing Dt:
05/21/2004
Title:
METHOD OF FORMING SEMICONDUCTOR DEVICES BY MICROWAVE CURING OF LOW-K DIELECTRIC FILMS
58
Patent #:
Issue Dt:
11/14/2006
Application #:
10851821
Filing Dt:
05/21/2004
Publication #:
Pub Dt:
11/24/2005
Title:
POLYCRYSTALLINE SIGE JUNCTIONS FOR ADVANCED DEVICES
59
Patent #:
Issue Dt:
10/03/2006
Application #:
10852142
Filing Dt:
05/25/2004
Publication #:
Pub Dt:
10/28/2004
Title:
METHOD TO SELECTIVELY CAP INTERCONNECTS WITH INDIUM OR TIN BRONZES AND/OR OXIDES THEREOF AND THE INTERCONNECT SO CAPPED
60
Patent #:
Issue Dt:
05/06/2008
Application #:
10853041
Filing Dt:
05/25/2004
Publication #:
Pub Dt:
12/15/2005
Title:
MODELING LANGUAGE AND METHOD FOR ADDRESS TRANSLATION DESIGN MECHANISMS IN TEST GENERATION
61
Patent #:
Issue Dt:
03/11/2008
Application #:
10855047
Filing Dt:
05/27/2004
Publication #:
Pub Dt:
12/01/2005
Title:
METHOD FOR DEFERRED DATA COLLECTION IN A CLOCK RUNNING SYSTEM
62
Patent #:
Issue Dt:
03/25/2008
Application #:
10855915
Filing Dt:
05/27/2004
Publication #:
Pub Dt:
12/23/2004
Title:
HIGH-QUALITY SGOI BY ANNEALING NEAR THE ALLOY MELTING POINT
63
Patent #:
Issue Dt:
06/14/2005
Application #:
10856503
Filing Dt:
05/28/2004
Publication #:
Pub Dt:
11/11/2004
Title:
METHOD TO FABRICATE HIGH-PERFORMANCE NPN TRANSISTORS IN A BICMOS PROCESS
64
Patent #:
Issue Dt:
03/07/2006
Application #:
10856547
Filing Dt:
05/28/2004
Publication #:
Pub Dt:
12/01/2005
Title:
INDIRECT SWITCHING AND SENSING OF PHASE CHANGE MEMORY CELLS
65
Patent #:
Issue Dt:
11/11/2008
Application #:
10858605
Filing Dt:
06/02/2004
Title:
FEEDBACK CONTROL OF IMPRINT MASK FEATURE PROFILE USING SCATTEROMETRY AND SPACER ETCHBACK
66
Patent #:
Issue Dt:
11/14/2006
Application #:
10858739
Filing Dt:
06/01/2004
Title:
WAFER LEVEL GLOBAL BITMAP CHARACTERIZATION IN INTEGRATED CIRCUIT TECHNOLOGY DEVELOPMENT
67
Patent #:
Issue Dt:
05/29/2007
Application #:
10858759
Filing Dt:
06/02/2004
Title:
IN-SITU DEFECT MONITOR AND CONTROL SYSTEM FOR IMMERSION MEDIUM IN IMMERSION LITHOGRAPHY
68
Patent #:
Issue Dt:
04/29/2008
Application #:
10858791
Filing Dt:
06/02/2004
Title:
METHOD FOR OPTIMIZING LOOP CONTROL OF MICROCODED INSTRUCTIONS
69
Patent #:
Issue Dt:
09/09/2008
Application #:
10859276
Filing Dt:
06/02/2004
Title:
OPTICAL PROXIMITY CORRECTION (OPC) TECHNIQUE TO COMPENSATE FOR FLARE
70
Patent #:
Issue Dt:
08/14/2007
Application #:
10859673
Filing Dt:
06/03/2004
Title:
METHODS AND FIXTURE FOR COUPLING A LID TO A SUPPORT SUBSTRATE
71
Patent #:
Issue Dt:
02/08/2011
Application #:
10860966
Filing Dt:
06/04/2004
Title:
MUTI-GIGABIT PER SECOND CONCURRENT ENCRYPTION IN BLOCK CIPHER MODES
72
Patent #:
Issue Dt:
02/13/2007
Application #:
10862518
Filing Dt:
06/07/2004
Publication #:
Pub Dt:
05/05/2005
Title:
TECHNIQUE FOR FORMING TRANSISTORS HAVING RAISED DRAIN AND SOURCE REGIONS WITH DIFFERENT HEIGHTS
73
Patent #:
Issue Dt:
07/26/2005
Application #:
10864238
Filing Dt:
06/09/2004
Publication #:
Pub Dt:
01/13/2005
Title:
COMPLEMENTARY TWO TRANSISTOR ROM CELL
74
Patent #:
Issue Dt:
05/31/2005
Application #:
10865138
Filing Dt:
06/10/2004
Publication #:
Pub Dt:
11/11/2004
Title:
DIFFUSED EXTRINSIC BASE AND METHOD FOR FABRICATION
75
Patent #:
Issue Dt:
10/24/2006
Application #:
10865920
Filing Dt:
06/14/2004
Publication #:
Pub Dt:
12/15/2005
Title:
MIXED ORIENTATION AND MIXED MATERIAL SEMICONDUCTOR-ON-INSULATOR WAFER
76
Patent #:
Issue Dt:
08/05/2008
Application #:
10867094
Filing Dt:
06/14/2004
Publication #:
Pub Dt:
12/15/2005
Title:
MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT
77
Patent #:
Issue Dt:
08/05/2008
Application #:
10867302
Filing Dt:
06/14/2004
Publication #:
Pub Dt:
12/02/2004
Title:
SYSTEM FOR FACILITATING COVERAGE FEEDBACK TESTCASE GENERATION REPRODUCIBILITY
78
Patent #:
Issue Dt:
09/04/2007
Application #:
10867772
Filing Dt:
06/16/2004
Publication #:
Pub Dt:
01/06/2005
Title:
METHOD OF FABRICATING SEMICONDUCTOR SIDE WALL FIN
79
Patent #:
Issue Dt:
12/05/2006
Application #:
10868791
Filing Dt:
06/17/2004
Publication #:
Pub Dt:
11/25/2004
Title:
METHOD FOR MANUFACTURING DEVICE SUBSTRATE WITH METAL BACK-GATE AND STRUCTURE FORMED THEREBY
80
Patent #:
Issue Dt:
06/20/2006
Application #:
10869624
Filing Dt:
06/16/2004
Publication #:
Pub Dt:
11/11/2004
Title:
IMPLANTED ASYMMETRIC DOPED POLYSILICON GATE FINFET
81
Patent #:
Issue Dt:
10/09/2007
Application #:
10869658
Filing Dt:
06/16/2004
Publication #:
Pub Dt:
12/22/2005
Title:
HIGH-TEMPERATURE STABLE GATE STRUCTURE WITH METALLIC ELECTRODE
82
Patent #:
Issue Dt:
01/08/2013
Application #:
10870318
Filing Dt:
06/17/2004
Title:
NETWORK INTERFACE SYSTEMS AND METHODS FOR OFFLOADING SEGMENTATION AND/OR CHECKSUMMING WITH SECURITY PROCESSING
83
Patent #:
Issue Dt:
06/20/2006
Application #:
10872173
Filing Dt:
06/18/2004
Publication #:
Pub Dt:
11/18/2004
Title:
MOS ANTIFUSE WITH LOW POST-PROGRAM RESISTANCE
84
Patent #:
Issue Dt:
01/30/2007
Application #:
10872707
Filing Dt:
06/21/2004
Title:
STRAINED SILICON MOSFET HAVING IMPROVED SOURCE/DRAIN EXTENSION DOPANT DIFFUSION RESISTANCE AND METHOD FOR ITS FABRICATION
85
Patent #:
Issue Dt:
05/29/2007
Application #:
10873240
Filing Dt:
06/23/2004
Title:
MULTI-CHANNEL TRANSISTOR WITH TUNABLE HOT CARRIER EFFECT
86
Patent #:
Issue Dt:
07/29/2008
Application #:
10873672
Filing Dt:
06/22/2004
Publication #:
Pub Dt:
12/22/2005
Title:
REDUCING POWER CONSUMPTION IN SIGNAL DETECTION
87
Patent #:
Issue Dt:
10/03/2006
Application #:
10873733
Filing Dt:
06/22/2004
Publication #:
Pub Dt:
12/22/2005
Title:
METHOD OF FORMING METAL/HIGH-K GATE STACKS WITH HIGH MOBILITY
88
Patent #:
Issue Dt:
10/09/2007
Application #:
10875699
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
12/29/2005
Title:
COMMON CARRIER
89
Patent #:
Issue Dt:
03/06/2007
Application #:
10875727
Filing Dt:
06/24/2004
Publication #:
Pub Dt:
12/29/2005
Title:
COMPRESSIVE SIGE <110> GROWTH AND STRUCTURE OF MOSFET DEVICES
90
Patent #:
Issue Dt:
11/29/2005
Application #:
10879833
Filing Dt:
06/29/2004
Title:
DUAL GATED FINFET GAIN CELL
91
Patent #:
Issue Dt:
09/16/2008
Application #:
10880853
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD, SYSTEM AND PROGRAM PRODUCT FOR PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE SUPPORTING INCOMPLETELY SPECIFIED CONFIGURATION ENTITIES
92
Patent #:
Issue Dt:
12/27/2011
Application #:
10881932
Filing Dt:
06/30/2004
Publication #:
Pub Dt:
02/03/2005
Title:
METHOD OF IMPROVING THE WAFER-TO-WAFER THICKNESS UNIFORMITY OF SILICON NITRIDE LAYERS
93
Patent #:
Issue Dt:
11/21/2006
Application #:
10883392
Filing Dt:
07/01/2004
Publication #:
Pub Dt:
01/05/2006
Title:
APPARATUS AND METHODS FOR MICROCHANNEL COOLING OF SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGES
94
Patent #:
Issue Dt:
02/06/2007
Application #:
10883887
Filing Dt:
07/02/2004
Publication #:
Pub Dt:
01/05/2006
Title:
STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED P+ SILICON GERMANIUM LAYER
95
Patent #:
Issue Dt:
04/27/2010
Application #:
10885462
Filing Dt:
07/06/2004
Publication #:
Pub Dt:
01/12/2006
Title:
METHODS FOR THE FORMATION OF FULLY SILICIDED METAL GATES
96
Patent #:
Issue Dt:
11/02/2010
Application #:
10887069
Filing Dt:
07/08/2004
Title:
DATA PROCESSOR HAVING A CACHE WITH EFFICIENT STORAGE OF PREDECODE INFORMATION, CACHE, AND METHOD
97
Patent #:
Issue Dt:
10/10/2006
Application #:
10887087
Filing Dt:
07/09/2004
Publication #:
Pub Dt:
01/12/2006
Title:
COPPER CONDUCTOR
98
Patent #:
Issue Dt:
12/13/2005
Application #:
10887983
Filing Dt:
07/08/2004
Title:
QUASI-STATIC RANDOM ACCESS MEMORY
99
Patent #:
Issue Dt:
08/06/2013
Application #:
10890649
Filing Dt:
07/14/2004
Title:
Network interface with secondary data and packet information storage and memory control systems to accommodate out-of-order data processing and split transactions on a host system bus
100
Patent #:
Issue Dt:
03/25/2008
Application #:
10892211
Filing Dt:
07/16/2004
Publication #:
Pub Dt:
01/19/2006
Title:
METHOD AND SYSTEM FOR REAL-TIME ESTIMATION AND PREDICTION OF THE THERMAL STATE OF A MICROPROCESSOR UNIT
Assignor
1
Exec Dt:
11/27/2018
Assignee
1
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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