|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10896504
|
Filing Dt:
|
07/22/2004
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR MINIMIZING THRESHOLD VARIATION FROM BODY CHARGE IN SILICON-ON-INSULATOR CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2009
|
Application #:
|
10896812
|
Filing Dt:
|
07/22/2004
|
Publication #:
|
|
Pub Dt:
|
01/06/2005
| | | | |
Title:
|
CONTROL OF BURIED OXIDE IN SIMOX
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
10899199
|
Filing Dt:
|
07/26/2004
|
Publication #:
|
|
Pub Dt:
|
09/01/2005
| | | | |
Title:
|
ON-THE-FLY ENCRYPTION/DECRYPTION FOR WLAN COMMUNICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2014
|
Application #:
|
10899200
|
Filing Dt:
|
07/26/2004
|
Publication #:
|
|
Pub Dt:
|
08/04/2005
| | | | |
Title:
|
FAST CIPHERING KEY SEARCH FOR WLAN RECEIVERS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10899768
|
Filing Dt:
|
07/27/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
TEMPERATURE SENSOR FOR HIGH POWER VERY LARGE SCALE INTEGRATION CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
10899937
|
Filing Dt:
|
07/27/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
DRAM ACCESS COMMAND QUEUING STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10900487
|
Filing Dt:
|
07/28/2004
|
Publication #:
|
|
Pub Dt:
|
01/13/2005
| | | | |
Title:
|
TUNNELING MAGNETORESISTIVE (TMR) SENSOR HAVING A MAGNESIUM OXIDE BARRIER LAYER FORMED BY A MULTI-LAYER PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
10901868
|
Filing Dt:
|
07/29/2004
|
Publication #:
|
|
Pub Dt:
|
02/03/2005
| | | | |
Title:
|
RELIABLE LOW-K INTERCONNECT STRUCTURE WITH HYBRID DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
04/27/2010
|
Application #:
|
10902601
|
Filing Dt:
|
07/30/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
AUTONOMIC CLIENT MIGRATION SYSTEM FOR SERVICE ENGAGEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10902653
|
Filing Dt:
|
07/28/2004
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
Title:
|
ESD DISSIPATIVE COATING ON CABLES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10904056
|
Filing Dt:
|
10/21/2004
|
Publication #:
|
|
Pub Dt:
|
04/27/2006
| | | | |
Title:
|
SIMULATION TESTING OF DIGITAL LOGIC CIRCUIT DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10904059
|
Filing Dt:
|
10/21/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
STRUCTURE FOR STRAINED CHANNEL FIELD EFFECT TRANSISTOR PAIR HAVING A MEMBER AND A CONTACT VIA
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
10904225
|
Filing Dt:
|
10/29/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
10904309
|
Filing Dt:
|
11/03/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
10904355
|
Filing Dt:
|
11/05/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
METHOD FOR IMPROVING OPTICAL PROXIMITY CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
10904357
|
Filing Dt:
|
11/05/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
FIN DEVICE WITH CAPACITOR INTEGRATED UNDER GATE ELECTRODE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
10904391
|
Filing Dt:
|
11/08/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
SELF-ALIGNED LOW-K GATE CAP
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
10904397
|
Filing Dt:
|
11/08/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR CONVERTING GLOBALLY CLOCK-GATED CIRCUITS TO LOCALLY CLOCK-GATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2006
|
Application #:
|
10904435
|
Filing Dt:
|
11/10/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
APPARATUS AND METHOD FOR SINGLE DIE BACKSIDE PROBING OF SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2006
|
Application #:
|
10904438
|
Filing Dt:
|
11/10/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
IMPROVED ION DETECTOR FOR IONBEAM APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
10904460
|
Filing Dt:
|
11/11/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
CIRCUIT AND METHOD OF CONTROLLING INTEGRATED CIRCUIT POWER CONSUMPTION USING PHASE CHANGE SWITCHES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2008
|
Application #:
|
10904528
|
Filing Dt:
|
11/15/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10904555
|
Filing Dt:
|
11/16/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
FLUIDIC COOLING SYSTEMS AND METHODS FOR ELECTRONIC COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
10904582
|
Filing Dt:
|
11/17/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
METHOD OF FABRICATING A BOTTLE TRENCH AND A BOTTLE TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
|
Application #:
|
10904601
|
Filing Dt:
|
11/18/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR CLEANING A SEMICONDUCTOR SUBSTRATE IN AN IMMERSION LITHOGRAPHY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10904680
|
Filing Dt:
|
11/23/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
DENDRITE GROWTH CONTROL CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
10904681
|
Filing Dt:
|
11/23/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
AN ELECTRICALLY PROGRAMMABLE FUSE FOR SILICON-ON-INSULATOR (SOI) TECHNOLOGY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10904808
|
Filing Dt:
|
11/30/2004
|
Publication #:
|
|
Pub Dt:
|
06/01/2006
| | | | |
Title:
|
STRUCTURE AND METHOD OF APPLYING STRESSES TO PFET AND NFET TRANSISTOR CHANNELS FOR IMPROVED PERFORMANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2006
|
Application #:
|
10904827
|
Filing Dt:
|
12/01/2004
|
Publication #:
|
|
Pub Dt:
|
06/01/2006
| | | | |
Title:
|
IMPROVED HDP-BASED ILD CAPPING LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2007
|
Application #:
|
10904950
|
Filing Dt:
|
12/07/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
METHOD, SYSTEM AND PROGRAM PRODUCT FOR EVALUATING A CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
10905008
|
Filing Dt:
|
12/09/2004
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
Title:
|
TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10905024
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
METHOD FOR FORMING DUAL ETCH STOP LINER AND PROTECTIVE LAYER IN A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2008
|
Application #:
|
10905025
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
10905027
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/08/2008
|
Application #:
|
10905041
|
Filing Dt:
|
12/13/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
SIDEWALL SEMICONDUCTOR TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10905062
|
Filing Dt:
|
12/14/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
DUAL STRESSED SOI SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
10905068
|
Filing Dt:
|
12/14/2004
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
METHOD FOR FORMING DAMASCENE STRUCTURE UTILIZING PLANARIZING MATERIAL COUPLED WITH COMPRESSIVE DIFFUSION BARRIER MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2007
|
Application #:
|
10905094
|
Filing Dt:
|
12/15/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
LOW-COST DEEP TRENCH DECOUPLING CAPACITOR DEVICE AND PROCESS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
10905230
|
Filing Dt:
|
12/22/2004
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
MANUFACTURABLE COWP METAL CAP PROCESS FOR COPPER INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
10905474
|
Filing Dt:
|
01/06/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
CIRCUIT ELEMENT FUNCTION MATCHING DESPITE AUTO-GENERATED DUMMY SHAPES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
10905480
|
Filing Dt:
|
01/06/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
ON-CHIP SIGNAL TRANSFORMER FOR GROUND NOISE ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
10905486
|
Filing Dt:
|
01/06/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
10905586
|
Filing Dt:
|
01/12/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
TRANSISTOR STRUCTURE HAVING STRESSED REGIONS OF OPPOSITE TYPES UNDERLYING CHANNEL AND SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
10905589
|
Filing Dt:
|
01/12/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
ENHANCED PFET USING SHEAR STRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10905590
|
Filing Dt:
|
01/12/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
WIRING PATTERNS FORMED BY SELECTIVE METAL PLATING
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
10905684
|
Filing Dt:
|
01/17/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
SELF-ALIGNED, SILICIDED, TRENCH-BASED, DRAM/EDRAM PROCESSES WITH IMPROVED RETENTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
10905816
|
Filing Dt:
|
01/21/2005
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
DETECTION OF DIAMOND CONTAMINATION IN POLISHING PAD
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10905874
|
Filing Dt:
|
01/25/2005
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
DUAL GATE FINFET RADIO FREQUENCY SWITCH AND MIXER
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/2011
|
Application #:
|
10905905
|
Filing Dt:
|
01/26/2005
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
THERMO-MECHANICAL CLEAVABLE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10905934
|
Filing Dt:
|
01/27/2005
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
MULTIPLE LAYER STRUCTURE FOR SUBSTRATE NOISE ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2007
|
Application #:
|
10905970
|
Filing Dt:
|
01/28/2005
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
CLOCK TREE DISTRIBUTION GENERATION BY DETERMINING ALLOWED PLACEMENT REGIONS FOR CLOCKED ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10905973
|
Filing Dt:
|
01/28/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
METHOD OF FORMING A MIM CAPACITOR FOR CU BEOL APPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
10906016
|
Filing Dt:
|
01/31/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
VERTICAL CARBON NANOTUBE TRANSISTOR INTEGRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
10906111
|
Filing Dt:
|
02/03/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
COMPLIANT ELECTRICAL CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
10906147
|
Filing Dt:
|
02/04/2005
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/21/2008
|
Application #:
|
10906238
|
Filing Dt:
|
02/10/2005
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
VERTICAL BODY-CONTACTED SOI TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2009
|
Application #:
|
10906267
|
Filing Dt:
|
02/11/2005
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
METHOD TO CREATE AIR GAPS USING NON-PLASMA PROCESSES TO DAMAGE ILD MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
10906268
|
Filing Dt:
|
02/11/2005
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
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METHOD TO CREATE REGION SPECIFIC EXPOSURE IN A LAYER
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Patent #:
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Issue Dt:
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05/29/2007
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Application #:
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10906335
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Filing Dt:
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02/15/2005
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Publication #:
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Pub Dt:
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08/17/2006
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Title:
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STRUCTURE AND METHOD FOR MANUFACTURING STRAINED FINFET
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Patent #:
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Issue Dt:
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07/22/2008
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Application #:
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10906343
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Filing Dt:
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02/15/2005
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Publication #:
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Pub Dt:
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08/17/2006
| | | | |
Title:
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SYSTEM AND METHOD FOR BALANCING DELAY OF SIGNAL COMMUNICATION PATHS THROUGH WELL VOLTAGE ADJUSTMENT
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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10906365
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Filing Dt:
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02/16/2005
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Publication #:
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Pub Dt:
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08/17/2006
| | | | |
Title:
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THIN FILM RESISTOR WITH CURRENT DENSITY ENHANCING LAYER (CDEL)
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Patent #:
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Issue Dt:
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07/03/2007
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Application #:
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10906407
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Filing Dt:
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02/18/2005
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Publication #:
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Pub Dt:
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08/24/2006
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Title:
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CLOCK CONTROL CIRCUIT FOR TEST THAT FACILITATES AN AT SPEED STRUCTURAL TEST
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Patent #:
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Issue Dt:
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11/26/2013
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Application #:
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10906508
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Filing Dt:
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02/23/2005
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Publication #:
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Pub Dt:
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08/24/2006
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Title:
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METHOD AND APPARATUS FOR VERIFYING MEMORY TESTING SOFTWARE
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10906510
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Filing Dt:
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02/23/2005
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Publication #:
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Pub Dt:
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08/24/2006
| | | | |
Title:
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IMAGE SENSOR CELLS
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Patent #:
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Issue Dt:
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10/30/2007
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Application #:
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10906547
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Filing Dt:
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02/24/2005
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Publication #:
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Pub Dt:
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09/07/2006
| | | | |
Title:
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IMPROVED DOUBLE GATE ISOLATION
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Patent #:
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Issue Dt:
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07/03/2007
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Application #:
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10906553
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Filing Dt:
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02/24/2005
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Publication #:
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Pub Dt:
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08/24/2006
| | | | |
Title:
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INTEGRATED CIRCUIT LAYOUT CRITICAL AREA DETERMINATION USING VORONOI DIAGRAMS AND SHAPE BIASING
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Patent #:
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Issue Dt:
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03/29/2011
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Application #:
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10906564
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Filing Dt:
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02/24/2005
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Publication #:
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Pub Dt:
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08/24/2006
| | | | |
Title:
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METHOD FOR TESTING A PHOTOMASK
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Patent #:
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Issue Dt:
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10/02/2007
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Application #:
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10906625
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Filing Dt:
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02/28/2005
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Publication #:
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Pub Dt:
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08/31/2006
| | | | |
Title:
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BODY POTENTIAL IMAGER CELL
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Patent #:
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Issue Dt:
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06/05/2007
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Application #:
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10906718
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Filing Dt:
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03/03/2005
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Publication #:
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Pub Dt:
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09/07/2006
| | | | |
Title:
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DENSE SEMICONDUCTOR FUSE ARRAY
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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10906808
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Filing Dt:
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03/08/2005
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Publication #:
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Pub Dt:
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09/14/2006
| | | | |
Title:
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SIMPLIFIED BURIED PLATE STRUCTURE AND PROCESS FOR SEMICONDUCTOR-ON-INSULATOR CHIP
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Patent #:
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Issue Dt:
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11/02/2010
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Application #:
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10906826
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Filing Dt:
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03/08/2005
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Publication #:
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Pub Dt:
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09/14/2006
| | | | |
Title:
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METHOD OF DETERMINING N-WELL SCATTERING EFFECTS ON FETS
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Patent #:
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Issue Dt:
|
05/23/2006
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Application #:
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10907463
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Filing Dt:
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04/01/2005
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Title:
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DE-FLUORINATION OF WAFER SURFACE AND RELATED STRUCTURE
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Patent #:
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Issue Dt:
|
07/03/2007
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Application #:
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10907494
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Filing Dt:
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04/04/2005
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Publication #:
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Pub Dt:
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10/05/2006
| | | | |
Title:
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METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS
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|
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Patent #:
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Issue Dt:
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10/30/2007
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Application #:
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10907496
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Filing Dt:
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04/04/2005
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Publication #:
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Pub Dt:
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10/05/2006
| | | | |
Title:
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VIA REDUNDANCY BASED ON SUBNET TIMING INFORMATION, TARGET VIA DISTANT ALONG PATH FROM SOURCE AND/OR TARGET VIA NET/SUBNET CHARACTERISTIC
|
|
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Patent #:
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|
Issue Dt:
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08/21/2007
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Application #:
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10907537
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Filing Dt:
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04/05/2005
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Publication #:
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Pub Dt:
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10/05/2006
| | | | |
Title:
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HIGH Q MONOLITHIC INDUCTORS FOR USE IN DIFFERENTIAL CIRCUITS
|
|
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10907570
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Filing Dt:
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04/06/2005
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Publication #:
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Pub Dt:
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10/12/2006
| | | | |
Title:
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PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF
|
|
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Patent #:
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Issue Dt:
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11/11/2008
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Application #:
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10907628
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Filing Dt:
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04/08/2005
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Publication #:
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Pub Dt:
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10/12/2006
| | | | |
Title:
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OPTIMAL BUS OPERATION PERFORMANCE IN A LOGIC SIMULATION ENVIRONMENT
|
|
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Patent #:
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Issue Dt:
|
02/03/2009
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Application #:
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10907630
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Filing Dt:
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04/08/2005
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Publication #:
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Pub Dt:
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10/12/2006
| | | | |
Title:
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SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/EDRAM INTEGRATION: METHOD AND STRUCTURE
|
|
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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10907686
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Filing Dt:
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04/12/2005
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Publication #:
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Pub Dt:
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10/12/2006
| | | | |
Title:
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STRUCTURE AND METHOD OF FABRICATING HIGH-DENSITY TRENCH-BASED NON-VOLATILE RANDOM ACCESS SONOS MEMORY CELLS FOR SOC APPLICATIONS
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|
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Patent #:
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Issue Dt:
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08/15/2006
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Application #:
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10907712
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Filing Dt:
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04/13/2005
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Title:
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FOUR-BIT FINFET NVRAM MEMORY DEVICE
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|
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Patent #:
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Issue Dt:
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01/23/2007
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Application #:
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10907873
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Filing Dt:
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04/19/2005
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Publication #:
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Pub Dt:
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10/19/2006
| | | | |
Title:
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HEAT DISSIPATION FOR HEAT GENERATING ELEMENT OF SEMICONDUCTOR DEVICE AND RELATED METHOD
|
|
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Patent #:
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|
Issue Dt:
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03/17/2009
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Application #:
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10907935
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Filing Dt:
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04/21/2005
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Publication #:
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Pub Dt:
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10/26/2006
| | | | |
Title:
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METHOD OF FORMING AN ULTRA-THIN [[HFSIO]] METAL SILCATE FILM FOR HIGH PERFORMANCE CMOS APPLICATIONS AND SEMICONDUCTOR STRUCTURE FORMED IN SAID METHOD
|
|
|
Patent #:
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Issue Dt:
|
09/05/2006
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Application #:
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10907971
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Filing Dt:
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04/22/2005
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Title:
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STRUCTURE AND METHOD FOR DUAL-GATE FET WITH SOI SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
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Application #:
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10908033
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Filing Dt:
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04/26/2005
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Publication #:
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Pub Dt:
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10/26/2006
| | | | |
Title:
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METHOD AND APPARATUS FOR INCREASING FUSE PROGRAMMING YIELD THROUGH PREFERRED USE OF DUPLICATE DATA
|
|
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Patent #:
|
|
Issue Dt:
|
02/12/2008
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Application #:
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10908083
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Filing Dt:
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04/27/2005
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Publication #:
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Pub Dt:
|
11/02/2006
| | | | |
Title:
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SOLDER BUMPS IN FLIP-CHIP TECHNOLOGIES
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|
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Patent #:
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Issue Dt:
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03/25/2008
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Application #:
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10908084
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Filing Dt:
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04/27/2005
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Publication #:
|
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Pub Dt:
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11/02/2006
| | | | |
Title:
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POST BUMP PASSIVATION FOR SOFT ERROR PROTECTION
|
|
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Patent #:
|
|
Issue Dt:
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08/26/2008
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Application #:
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10908102
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Filing Dt:
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04/27/2005
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Publication #:
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Pub Dt:
|
11/02/2006
| | | | |
Title:
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METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION
|
|
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Patent #:
|
|
Issue Dt:
|
04/08/2008
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Application #:
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10908117
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Filing Dt:
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04/28/2005
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Publication #:
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Pub Dt:
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11/02/2006
| | | | |
Title:
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SILICON-ON-INSULATOR BASED RADIATION DETECTION DEVICE AND METHOD
|
|
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Patent #:
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Issue Dt:
|
10/30/2007
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Application #:
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10908252
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Filing Dt:
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05/04/2005
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Publication #:
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Pub Dt:
|
11/09/2006
| | | | |
Title:
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SILICON NITRIDE ETCHING METHODS
|
|
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Patent #:
|
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Issue Dt:
|
04/03/2007
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Application #:
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10908284
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Filing Dt:
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05/05/2005
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Publication #:
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Pub Dt:
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11/09/2006
| | | | |
Title:
|
STRUCTURE AND METHODOLOGY FOR FABRICATION AND INSPECTION OF PHOTOMASKS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
10908342
|
Filing Dt:
|
05/09/2005
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Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
CONTENT BASED YIELD PREDICTION OF VLSI DESIGNS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2008
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Application #:
|
10908346
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Filing Dt:
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05/09/2005
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Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
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TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10908357
|
Filing Dt:
|
05/09/2005
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Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
ALIGNED DUMMY METAL FILL AND HOLE SHAPES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
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Application #:
|
10908360
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Filing Dt:
|
05/09/2005
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Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
|
ELECTRICAL PROGRAMMABLE METAL RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
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Application #:
|
10908361
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Filing Dt:
|
05/09/2005
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Publication #:
|
|
Pub Dt:
|
11/09/2006
| | | | |
Title:
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STRUCTURE AND METHOD FOR PERFORMANCE IMPROVEMENT IN VERTICAL BIPOLAR TRANSISTORS
|
|
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Patent #:
|
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Issue Dt:
|
11/04/2008
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Application #:
|
10908394
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Filing Dt:
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05/10/2005
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Publication #:
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Pub Dt:
|
11/16/2006
| | | | |
Title:
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EMBEDDED SILICON GERMANIUM USING A DOUBLE BURIED OXIDE SILICON-ON-INSULATOR WAFER
|
|
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Patent #:
|
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Issue Dt:
|
11/07/2006
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Application #:
|
10908411
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Filing Dt:
|
05/11/2005
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Publication #:
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Pub Dt:
|
11/16/2006
| | | | |
Title:
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METHOD FOR FORMING A SIGE OR SIGEC GATE SELECTIVELY IN A COMPLEMENTARY MIS/MOS FET DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
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Application #:
|
10908442
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Filing Dt:
|
05/12/2005
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Publication #:
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Pub Dt:
|
11/16/2006
| | | | |
Title:
|
ANTI-HALO COMPENSATION
|
|
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Patent #:
|
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Issue Dt:
|
09/05/2006
|
Application #:
|
10908556
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Filing Dt:
|
05/17/2005
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Title:
|
LOW CAPACITANCE JUNCTION-ISOLATION FOR BULK FINFET TECHNOLOGY
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|
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Patent #:
|
|
Issue Dt:
|
08/08/2006
|
Application #:
|
10908583
|
Filing Dt:
|
05/18/2005
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Title:
|
DOUBLE-GATE FETS (FIELD EFFECT TRANSISTORS)
|
|