|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
10988132
|
Filing Dt:
|
11/12/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
ANTIFUSE STRUCTURE HAVING AN INTEGRATED HEATING ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
10988137
|
Filing Dt:
|
11/12/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
FLUORINATED PHOTORESIST MATERIALS WITH IMPROVED ETCH RESISTANT PROPERTIES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2006
|
Application #:
|
10988215
|
Filing Dt:
|
11/12/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
COOLING DEVICE USING MULTIPLE FANS AND HEAT SINKS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/02/2008
|
Application #:
|
10988219
|
Filing Dt:
|
11/12/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
SEMICONDUCTOR CHIP HEAT TRANSFER DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
10988220
|
Filing Dt:
|
11/12/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
MIXED ELECTRICAL AND OPTICAL LGA INTERPOSER FOR FACILITATING CHIP TO BOARD COMMUNICATIONS BY DUAL SIGNAL TYPES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10990252
|
Filing Dt:
|
11/16/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
DEVICE AND METHOD FOR FABRICATING DOUBLE-SIDED SOI WAFER SCALE PACKAGE WITH THROUGH VIA CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2007
|
Application #:
|
10990401
|
Filing Dt:
|
11/18/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
SPIN-CURRENT SWITCHABLE MAGNETIC MEMORY ELEMENT AND METHOD OF FABRICATING THE MEMORY ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/2008
|
Application #:
|
10991808
|
Filing Dt:
|
11/18/2004
|
Title:
|
SCHEDULING TOOLS WITH QUEUE TIME CONSTRAINTS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/18/2008
|
Application #:
|
10992072
|
Filing Dt:
|
11/19/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
CUT-AND-PASTE IMPRINT LITHOGRAPHIC MOLD AND METHOD THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
10992399
|
Filing Dt:
|
11/18/2004
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
Title:
|
METHOD AND STRUCTURE FOR CREATING PRINTED CIRCUIT BOARDS WITH STEPPED THICKNESS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2005
|
Application #:
|
10993244
|
Filing Dt:
|
11/19/2004
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
FULLY-DEPLETED-COLLECTOR SILICON-ON-INSULATOR (SOI) BIPOLAR TRANSISTOR USEFUL ALONE OR IN SOI BICMOS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2008
|
Application #:
|
10993270
|
Filing Dt:
|
11/19/2004
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
PATTERNED SOI BY OXYGEN IMPLANTATION AND ANNEALING
|
|
|
Patent #:
|
|
Issue Dt:
|
01/03/2012
|
Application #:
|
10993305
|
Filing Dt:
|
11/19/2004
|
Publication #:
|
|
Pub Dt:
|
04/14/2005
| | | | |
Title:
|
OPTICAL ASSEMBLIES FOR TRANSMITTING AND MANIPULATING OPTICAL BEAMS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2006
|
Application #:
|
10993941
|
Filing Dt:
|
11/19/2004
|
Title:
|
GLOBAL PLANARIZATION OF WAFER SCALE PACKAGE WITH PRECISION DIE THICKNESS CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
10994494
|
Filing Dt:
|
11/20/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
METHODS FOR FORMING CO-PLANAR WAFER-SCALE CHIP PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/25/2008
|
Application #:
|
10996034
|
Filing Dt:
|
11/23/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR CONTROLLING ETCH SELECTIVITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
10996284
|
Filing Dt:
|
11/22/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
SRAM WITH DYNAMICALLY ASYMMETRIC CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/24/2008
|
Application #:
|
10996292
|
Filing Dt:
|
11/22/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
TECHNIQES FOR SUPER FAST BUFFER INSERTION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
|
Application #:
|
10996293
|
Filing Dt:
|
11/22/2004
|
Publication #:
|
|
Pub Dt:
|
02/09/2006
| | | | |
Title:
|
CLUSTERING TECHNIQUES FOR FASTER AND BETTER PLACEMENT OF VLSI CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2007
|
Application #:
|
10996311
|
Filing Dt:
|
11/22/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
HIGH PERFORMANCE REGISTER FILE WITH BOOTSTRAPPED STORAGE SUPPLY AND METHOD OF READING DATA THEREFORM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
10996312
|
Filing Dt:
|
11/23/2004
|
Publication #:
|
|
Pub Dt:
|
05/25/2006
| | | | |
Title:
|
ON-CHIP ELECTRICALLY ALTERABLE RESISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
10997597
|
Filing Dt:
|
11/24/2004
|
Publication #:
|
|
Pub Dt:
|
04/28/2005
| | | | |
Title:
|
SOI DEVICE WITH REDUCED JUNCTION CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/2008
|
Application #:
|
10998840
|
Filing Dt:
|
11/30/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCLUDING MIXED RARE EARTH OXIDE FORMED ON SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
10999404
|
Filing Dt:
|
11/30/2004
|
Title:
|
METHOD OF LITHOGRAPHIC MASK CORRECTION USING LOCALIZED TRANSMISSION ADJUSTMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
|
Application #:
|
11000869
|
Filing Dt:
|
12/01/2004
|
Title:
|
SYSTEMS AND METHODS OF IMPRINT LITHOGRAPHY WITH ADJUSTABLE MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2007
|
Application #:
|
11001483
|
Filing Dt:
|
12/01/2004
|
Title:
|
METHOD AND APPARATUS TO RECONCILE RECIPE MANAGER AND MANUFACTURING EXECUTION SYSTEM CONTEXT CONFIGURATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
11001491
|
Filing Dt:
|
12/01/2004
|
Title:
|
WIRELESS MODEM ARCHITECTURE FOR REDUCING MEMORY COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
11001511
|
Filing Dt:
|
12/02/2004
|
Title:
|
MOTORIZED HAMMOCK SWINGING ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11002525
|
Filing Dt:
|
12/02/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFICATION OF DIGITAL DESIGNS USING CASE-SPLITTING VIA CONSTRAINED INTERNAL SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2010
|
Application #:
|
11002559
|
Filing Dt:
|
12/02/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
METHOD TO GATE OFF PLLS IN A DEEP POWER SAVING STATE WITHOUT SEPARATE CLOCK DISTRIBUTION FOR POWER MANAGEMENT LOGIC
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11002686
|
Filing Dt:
|
12/02/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
METHOD, APPARATUS, AND COMPUTER PROGRAM PRODUCT FOR ENHANCING A POWER DISTRIBUTION SYSTEM IN A CERAMIC INTEGRATED CIRCUIT PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2006
|
Application #:
|
11003574
|
Filing Dt:
|
12/03/2004
|
Title:
|
METHOD FOR FORMING WORDLINES HAVING IRREGULAR SPACING IN A MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2006
|
Application #:
|
11003988
|
Filing Dt:
|
12/04/2004
|
Publication #:
|
|
Pub Dt:
|
05/12/2005
| | | | |
Title:
|
METHOD OF ASSESSING POTENTIAL FOR CHARGING DAMAGE IN SOI DESIGNS AND STRUCTURES FOR ELIMINATING POTENTIAL FOR DAMAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11004264
|
Filing Dt:
|
12/01/2004
|
Title:
|
METHOD AND SYSTEM FOR SELF-ASSEMBLING INSTRUCTION OPCODES FOR A CUSTOM RANDOM FUNCTIONAL TEST OF A MICROPROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
11004265
|
Filing Dt:
|
12/01/2004
|
Title:
|
METHOD AND SYSTEM FOR TESTING A MEMORY OF A MICROPROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
11004413
|
Filing Dt:
|
12/04/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR TRANSFERRING DATA TO AND FROM A MAGNETIC SHIFT REGISTER WITH A SHIFTABLE DATA COLUMN
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11004791
|
Filing Dt:
|
12/03/2004
|
Title:
|
SILICON-ON-INSULATOR CHIP HAVING AN ISOLATION BARRIER FOR RELIABILITY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
11004845
|
Filing Dt:
|
12/07/2004
|
Publication #:
|
|
Pub Dt:
|
05/05/2005
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE HAVING REDUCED AMINE-BASED CONTAMINANTS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2008
|
Application #:
|
11004846
|
Filing Dt:
|
12/07/2004
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
METHOD OF MAKING AN ELECTRONIC FUSE WITH IMPROVED ESD TOLERANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2006
|
Application #:
|
11004951
|
Filing Dt:
|
12/07/2004
|
Title:
|
SELECTIVE EPITAXIAL GROWTH FOR TUNABLE CHANNEL THICKNESS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11005659
|
Filing Dt:
|
12/07/2004
|
Publication #:
|
|
Pub Dt:
|
05/19/2005
| | | | |
Title:
|
METHOD OF FORMING FET WITH T-SHAPED GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
11006747
|
Filing Dt:
|
12/08/2004
|
Publication #:
|
|
Pub Dt:
|
06/08/2006
| | | | |
Title:
|
SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE COMPRISING MULTIPLE STACKED HYBRID ORIENTATION LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2008
|
Application #:
|
11008877
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
09/15/2005
| | | | |
Title:
|
TECHNIQUE FOR COMBINING SCAN TEST AND MEMORY BUILT-IN SELF TEST
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2011
|
Application #:
|
11009575
|
Filing Dt:
|
12/10/2004
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
TECHNIQUE FOR FORMING EMBEDDED METAL LINES HAVING INCREASED RESISTANCE AGAINST STRESS-INDUCED MATERIAL TRANSPORT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
11011245
|
Filing Dt:
|
12/14/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
METHOD FOR VERIFICATION USING REACHABILITY OVERAPPROXIMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11011246
|
Filing Dt:
|
12/14/2004
|
Publication #:
|
|
Pub Dt:
|
06/15/2006
| | | | |
Title:
|
METHOD FOR INCREMENTAL DESIGN REDUCTION VIA ITERATIVE OVERAPPROXIMATION AND RE-ENCODING STRATEGIES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
|
11013971
|
Filing Dt:
|
12/16/2004
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
LOW REFRACTIVE INDEX POLYMERS AS UNDERLAYERS FOR SILICON-CONTAINING PHOTORESISTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
11016219
|
Filing Dt:
|
12/17/2004
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
USING ELECTRICALLY PROGRAMMABLE FUSES TO HIDE ARCHITECTURE, PREVENT REVERSE ENGINEERING, AND MAKE A DEVICE INOPERABLE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
11016220
|
Filing Dt:
|
12/17/2004
|
Publication #:
|
|
Pub Dt:
|
06/22/2006
| | | | |
Title:
|
CHANGING CHIP FUNCTION BASED ON FUSE STATES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2006
|
Application #:
|
11021681
|
Filing Dt:
|
12/23/2004
|
Title:
|
MEMORY ELEMENTS USING ORGANIC ACTIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11023677
|
Filing Dt:
|
12/28/2004
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
METHODS AND APPARATUS FOR TESTING A MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2009
|
Application #:
|
11027980
|
Filing Dt:
|
01/03/2005
|
Title:
|
ESD PROTECTION CIRCUIT AND METHOD FOR LOWERING CAPACITANCE OF THE ESD PROTECTION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2011
|
Application #:
|
11028798
|
Filing Dt:
|
01/04/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR DIRECT REFERENCING OF TOP SURFACE OF WORKPIECE DURING IMPRINT LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11029797
|
Filing Dt:
|
01/05/2005
|
Publication #:
|
|
Pub Dt:
|
07/06/2006
| | | | |
Title:
|
STRESSED FIELD EFFECT TRANSISTORS ON HYBRID ORIENTATION SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11029921
|
Filing Dt:
|
01/05/2005
|
Publication #:
|
|
Pub Dt:
|
09/22/2005
| | | | |
Title:
|
HIGH-QUALITY SGOI BY OXIDATION NEAR THE ALLOY MELTING TEMPERATURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2007
|
Application #:
|
11029969
|
Filing Dt:
|
01/05/2005
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
MANUFACTURING METHODS FOR PRINTED CIRCUIT BOARDS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
11030191
|
Filing Dt:
|
01/07/2005
|
Publication #:
|
|
Pub Dt:
|
06/02/2005
| | | | |
Title:
|
MULTI-STEP CHEMICAL MECHANICAL POLISHING OF A GATE AREA IN A FINFET
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
11031138
|
Filing Dt:
|
01/07/2005
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
FLEXIBLE ROW REDUNDANCY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
11031165
|
Filing Dt:
|
01/07/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
QUASI-HYDROPHOBIC SI-SI WAFER BONDING USING HYDROPHILIC SI SURFACES AND DISSOLUTION OF INTERFACIAL BONDING OXIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/2009
|
Application #:
|
11031168
|
Filing Dt:
|
01/07/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2007
|
Application #:
|
11031418
|
Filing Dt:
|
01/07/2005
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
POROUS ORGANOSILICATES WITH IMPROVED MECHANICAL PROPERTIES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11032878
|
Filing Dt:
|
01/11/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
PROBABILISTIC CONGESTION PREDICTION WITH PARTIAL BLOCKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11033641
|
Filing Dt:
|
01/13/2005
|
Title:
|
BINARY CONTROLLED PHASE SELECTOR WITH OUTPUT DUTY CYCLE CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
11033754
|
Filing Dt:
|
01/13/2005
|
Title:
|
DUAL-MODE OUTPUT DRIVER CONFIGURED FOR OUTPUTTING A SIGNAL ACCORDING TO EITHER A SELECTED HIGH VOLTAGE/LOW SPEED MODE OR A LOW VOLTAGE/HIGH SPEED MODE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2007
|
Application #:
|
11033755
|
Filing Dt:
|
01/13/2005
|
Title:
|
ALIGNMENT OF LOCAL TRANSMIT CLOCK TO SYNCHRONOUS DATA TRANSFER CLOCK HAVING PROGRAMMABLE TRANSFER RATE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
11033757
|
Filing Dt:
|
01/13/2005
|
Title:
|
VOLTAGE MODE TRANSCEIVER HAVING PROGRAMMABLE VOLTAGE SWING AND EXTERNAL REFERENCE-BASED CALIBRATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
11033926
|
Filing Dt:
|
01/12/2005
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
Title:
|
CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
11034420
|
Filing Dt:
|
01/11/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
IMPACT CHECKING TECHNIQUE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11034479
|
Filing Dt:
|
01/13/2005
|
Publication #:
|
|
Pub Dt:
|
02/21/2008
| | | | |
Title:
|
ULTRALOW DIELECTRIC CONSTANT LAYER WITH CONTROLLED BIAXIAL STRESS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
11034480
|
Filing Dt:
|
01/13/2005
|
Publication #:
|
|
Pub Dt:
|
07/13/2006
| | | | |
Title:
|
MULTILAYER HARDMASK SCHEME FOR DAMAGE-FREE DUAL DAMASCENE PROCESSING OF SICOH DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2008
|
Application #:
|
11037694
|
Filing Dt:
|
01/18/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
SYSTEMS AND METHODS FOR MANAGING ERROR DEPENDENCIES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
11037913
|
Filing Dt:
|
01/18/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
HETEROGENEOUS THERMAL INTERFACE FOR COOLING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
11037970
|
Filing Dt:
|
01/18/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
ON-CHIP CU INTERCONNECTION USING 1 TO 5 NM THICK METAL CAP
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2006
|
Application #:
|
11037995
|
Filing Dt:
|
01/18/2005
|
Publication #:
|
|
Pub Dt:
|
09/15/2005
| | | | |
Title:
|
LOW-K DIELECTRIC MATERIAL SYSTEM FOR IC APPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2007
|
Application #:
|
11038593
|
Filing Dt:
|
01/19/2005
|
Publication #:
|
|
Pub Dt:
|
07/20/2006
| | | | |
Title:
|
SRAM MEMORIES AND MICROPROCESSORS HAVING LOGIC PORTIONS IMPLEMENTED IN HIGH-PERFORMANCE SILICON SUBSTRATES AND SRAM ARRAY PORTIONS HAVING FIELD EFFECT TRANSISTORS WITH LINKED BODIES AND METHODS FOR MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
11040139
|
Filing Dt:
|
01/21/2005
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR AUTOMATICALLY ESTIMATING PIN LOCATIONS AND INTERCONNECT PARASITICS OF A CIRCUIT LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/2010
|
Application #:
|
11042218
|
Filing Dt:
|
01/25/2005
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
SCRATCH PAD FOR STORING INTERMEDIATE LOOP FILTER DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2006
|
Application #:
|
11042426
|
Filing Dt:
|
01/25/2005
|
Title:
|
FABRICATION OF DUAL WORK-FUNCTION METAL GATE STRUCTURE FOR COMPLEMENTARY FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2007
|
Application #:
|
11042866
|
Filing Dt:
|
01/25/2005
|
Publication #:
|
|
Pub Dt:
|
06/16/2005
| | | | |
Title:
|
EEPROM DEVICE WITH SUBSTRATE HOT-ELECTRON INJECTOR FOR LOW-POWER PROGRAMMING
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2014
|
Application #:
|
11046986
|
Filing Dt:
|
01/31/2005
|
Publication #:
|
|
Pub Dt:
|
11/03/2005
| | | | |
Title:
|
Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2008
|
Application #:
|
11047129
|
Filing Dt:
|
01/31/2005
|
Publication #:
|
|
Pub Dt:
|
12/01/2005
| | | | |
Title:
|
TECHIQUE FOR CONTROLLING MECHANICAL STRESS IN A CHANNEL REGION BY SPACER REMOVAL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11048001
|
Filing Dt:
|
01/31/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
TECHNIQUES SUPPORTING COLLABORATIVE PRODUCT DEVELOPMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11048578
|
Filing Dt:
|
02/01/2005
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
Title:
|
FLUXLESS SOLDER TRANSFER AND REFLOW PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/21/2011
|
Application #:
|
11048739
|
Filing Dt:
|
02/03/2005
|
Publication #:
|
|
Pub Dt:
|
07/28/2005
| | | | |
Title:
|
STRAINED SILICON ON RELAXED SIGE FILM WITH UNIFORM MISFIT DISLOCATION DENSITY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11050232
|
Filing Dt:
|
02/03/2005
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
METHOD FOR RECONFIGURATION OF RANDOM BIASES IN A SYNTHESIZED DESIGN WITHOUT RECOMPILATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
11050325
|
Filing Dt:
|
02/03/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR FREQUENCY INDEPENDENT PROCESSOR UTILIZATION RECORDING REGISTER IN A SIMULTANEOUSLY MULTI-THREADED PROCESSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2007
|
Application #:
|
11050592
|
Filing Dt:
|
02/03/2005
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR OPTIMIZED HANDLING OF CONSTRAINTS DURING SYMBOLIC SIMULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2008
|
Application #:
|
11050602
|
Filing Dt:
|
02/03/2005
|
Publication #:
|
|
Pub Dt:
|
08/03/2006
| | | | |
Title:
|
METHOD FOR BALANCING POWER PLANE PIN CURRENTS IN A PRINTED WIRING BOARD USING COLLINEAR SLOTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
11050790
|
Filing Dt:
|
01/27/2005
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
Title:
|
GATE STACK ENGINEERING BY ELECTROCHEMICAL PROCESSING UTILIZING THROUGH-GATE-DIELECTRIC CURRENT FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11051703
|
Filing Dt:
|
02/04/2005
|
Publication #:
|
|
Pub Dt:
|
06/23/2005
| | | | |
Title:
|
ELECTRONICALLY PROGRAMMABLE ANTIFUSE AND CIRCUITS MADE THEREWITH
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
11052675
|
Filing Dt:
|
02/07/2005
|
Publication #:
|
|
Pub Dt:
|
07/07/2005
| | | | |
Title:
|
METHOD OF MAKING STRAINED CHANNEL CMOS TRANSISTORS HAVING LATTICE-MISMATCHED EPITAXIAL EXTENSION AND SOURCE AND DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2007
|
Application #:
|
11053220
|
Filing Dt:
|
02/08/2005
|
Publication #:
|
|
Pub Dt:
|
08/24/2006
| | | | |
Title:
|
METHODS, SYSTEMS AND MEDIA FOR MANAGING FUNCTIONAL VERIFICATION OF A PARAMETERIZABLE DESIGN
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2006
|
Application #:
|
11053707
|
Filing Dt:
|
02/08/2005
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
Title:
|
DUAL STRAIN-STATE SIGE LAYERS FOR MICROELECTRONICS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/18/2005
|
Application #:
|
11053863
|
Filing Dt:
|
02/10/2005
|
Title:
|
METHOD FOR DETECTING SILICIDE ENCROACHMENT OF A GATE ELECTRODE IN A SEMICONDUCTOR ARRANGEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/10/2009
|
Application #:
|
11054575
|
Filing Dt:
|
02/09/2005
|
Publication #:
|
|
Pub Dt:
|
08/10/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR COLLECTING FAILURE INFORMATION ON ERROR CORRECTION CODE (ECC) PROTECTED DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2007
|
Application #:
|
11055802
|
Filing Dt:
|
02/11/2005
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR CONTROLLING THE TIMING OF PRECHARGE IN A CONTENT ADDRESSABLE MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2008
|
Application #:
|
11055976
|
Filing Dt:
|
02/14/2005
|
Publication #:
|
|
Pub Dt:
|
07/21/2005
| | | | |
Title:
|
SOLUTION DEPOSITION OF CHALCOGENIDE FILMS CONTAINING TRANSITION METALS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
11056456
|
Filing Dt:
|
02/11/2005
|
Publication #:
|
|
Pub Dt:
|
02/23/2006
| | | | |
Title:
|
METHOD AND APPARATUS FOR SOLUTION PROCESSED DOPING OF CARBON NANOTUBE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2008
|
Application #:
|
11056726
|
Filing Dt:
|
02/11/2005
|
Publication #:
|
|
Pub Dt:
|
08/17/2006
| | | | |
Title:
|
EFFICIENT METHOD OF TEST AND SOFT REPAIR OF SRAM WITH REDUNDANCY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11056850
|
Filing Dt:
|
02/11/2005
|
Publication #:
|
|
Pub Dt:
|
04/20/2006
| | | | |
Title:
|
SYSTEM AND METHOD FOR ACCOMMODATING NON-GAUSSIAN AND NON-LINEAR SOURCES OF VARIATION IN STATISTICAL STATIC TIMING ANALYSIS
|
|