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METHOD AND APPARATUS TO DISABLE COMPACTION OF TEST RESPONSES IN DETERMINISTIC TEST-SET EMBEDDING-BASED BIST
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Patent #:
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Issue Dt:
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12/16/2008
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Application #:
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11116053
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Filing Dt:
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04/27/2005
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Publication #:
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Pub Dt:
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11/02/2006
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Title:
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FIELD EFFECT TRANSISTOR WITH MIXED-CRYSTAL-ORIENTATION CHANNEL AND SOURCE/DRAIN REGIONS
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Patent #:
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Issue Dt:
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10/30/2007
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Application #:
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11116625
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Filing Dt:
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04/28/2005
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Publication #:
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Pub Dt:
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11/02/2006
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Title:
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METHODS AND APPARATUS FOR REDUCING MEMORY ERRORS
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Patent #:
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Issue Dt:
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06/10/2008
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Application #:
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11116700
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Filing Dt:
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04/27/2005
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Publication #:
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Pub Dt:
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11/02/2006
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Title:
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MEMORY AND LOGIC DEVICES USING ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICES
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Patent #:
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Issue Dt:
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04/01/2008
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Application #:
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11117276
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Filing Dt:
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04/27/2005
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Publication #:
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Pub Dt:
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11/02/2006
| | | | |
Title:
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ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE
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Patent #:
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Issue Dt:
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04/10/2007
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Application #:
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11121454
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Filing Dt:
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05/04/2005
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Publication #:
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Pub Dt:
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10/20/2005
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Title:
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SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR WITH CARBON INCORPORATION
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Patent #:
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Issue Dt:
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12/10/2013
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Application #:
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11122152
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Filing Dt:
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05/04/2005
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Publication #:
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Pub Dt:
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09/08/2005
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Title:
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Method and apparatus for dynamic manipulation and dispersion in photonic crystal devices
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Patent #:
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Issue Dt:
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09/23/2008
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Application #:
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11124247
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Filing Dt:
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05/06/2005
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Publication #:
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Pub Dt:
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10/06/2005
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Title:
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HIGH TOLERANCE TCR BALANCED HIGH CURRENT RESISTOR FOR RF CMOS AND RF SIGE BICMOS APPLICATIONS AND CADENCED BASED HIERARCHICAL PARAMETERIZED CELL DESIGN KIT WITH TUNABLE TCR AND ESD RESISTOR BALLASTING FEATURE
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Patent #:
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Issue Dt:
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10/21/2008
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Application #:
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11124324
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Filing Dt:
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05/06/2005
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Publication #:
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Pub Dt:
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09/08/2005
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Title:
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METHOD OF CREATING DEEP TRENCH CAPACITOR USING A P+ METAL ELECTRODE
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Patent #:
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Issue Dt:
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05/27/2008
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Application #:
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11124978
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Filing Dt:
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05/09/2005
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Publication #:
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Pub Dt:
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09/15/2005
| | | | |
Title:
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SPLIT POLY-SIGE/POLY-SI ALLOY GATE STACK
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Patent #:
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Issue Dt:
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10/30/2007
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Application #:
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11125063
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Filing Dt:
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05/09/2005
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Publication #:
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Pub Dt:
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10/06/2005
| | | | |
Title:
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DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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03/18/2008
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Application #:
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11125456
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Filing Dt:
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05/10/2005
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Title:
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SYSTEM AND METHOD FOR TRACE MESSAGING
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Patent #:
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Issue Dt:
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11/06/2007
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Application #:
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11125696
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Filing Dt:
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05/10/2005
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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METHOD AND SYSTEM FOR LINE-DIMENSION CONTROL OF AN ETCH PROCESS
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Patent #:
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Issue Dt:
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04/08/2008
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Application #:
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11125971
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Filing Dt:
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05/09/2005
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Publication #:
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Pub Dt:
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11/09/2006
| | | | |
Title:
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PHOTORESISTS FOR VISIBLE LIGHT IMAGING
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Patent #:
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Issue Dt:
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01/22/2008
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Application #:
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11126675
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Filing Dt:
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05/11/2005
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Publication #:
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Pub Dt:
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09/29/2005
| | | | |
Title:
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METHOD AND STRUCTURE FOR BURIED CIRCUITS AND DEVICES
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Patent #:
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Issue Dt:
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10/23/2007
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Application #:
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11127175
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Filing Dt:
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05/12/2005
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Title:
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POLYMER SPACERS FOR CREATING SUB-LITHOGRAPHIC SPACES
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Patent #:
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Issue Dt:
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06/17/2008
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Application #:
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11128069
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Filing Dt:
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05/12/2005
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Publication #:
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Pub Dt:
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11/16/2006
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Title:
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INTEGRATED CIRCUIT DESIGN UTILIZING ARRAY OF FUNCTIONALLY INTERCHANGEABLE DYNAMIC LOGIC CELLS
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Patent #:
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Issue Dt:
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03/16/2010
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Application #:
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11128389
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Filing Dt:
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05/13/2005
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Title:
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SYSTEM AND METHOD FOR IMPROVING OXIDE-NITRIDE-OXIDE (ONO) COUPLING IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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04/08/2008
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Application #:
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11129784
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Filing Dt:
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05/16/2005
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Publication #:
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Pub Dt:
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01/12/2006
| | | | |
Title:
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GENIE: A METHOD FOR CLASSIFICATION AND GRAPHICAL DISPLAY OF NEGATIVE SLACK TIMING TEST FAILURES
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Patent #:
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Issue Dt:
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12/04/2007
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Application #:
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11129785
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Filing Dt:
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05/16/2005
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Publication #:
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Pub Dt:
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01/19/2006
| | | | |
Title:
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NEGATIVE SLACK RECOVERABILITY FACTOR - A NET WEIGHT TO ENHANCE TIMING CLOSURE BEHAVIOR
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Patent #:
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Issue Dt:
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05/13/2008
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Application #:
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11130078
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Filing Dt:
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05/16/2005
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Publication #:
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Pub Dt:
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11/16/2006
| | | | |
Title:
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PROCESS FOR PREPARING ELECTRONICS STRUCTURES USING A SACRIFICIAL MULTILAYER HARDMASK SCHEME
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Patent #:
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Issue Dt:
|
11/20/2007
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Application #:
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11130459
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Filing Dt:
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05/16/2005
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Title:
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METHOD AND APPARATUS FOR FAST DISTURBANCE DETECTION AND CLASSIFICIATION
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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11131534
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Filing Dt:
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05/18/2005
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Publication #:
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Pub Dt:
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11/23/2006
| | | | |
Title:
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CIRCUITS AND METHODS FOR IMPLEMENTING POWER AMPLIFIERS FOR MILLIMETER WAVE APPLICATIONS
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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11135227
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Filing Dt:
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05/23/2005
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Publication #:
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Pub Dt:
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12/07/2006
| | | | |
Title:
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VERTICAL FET WITH NANOWIRE CHANNELS AND A SILICIDED BOTTOM CONTACT
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11135720
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Filing Dt:
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05/24/2005
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Publication #:
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Pub Dt:
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04/13/2006
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Title:
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CHIP BOND LAYOUT FOR CHIP CARRIER FOR FLIP CHIP APPLICATIONS
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Patent #:
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Issue Dt:
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12/25/2007
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Application #:
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11136256
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Filing Dt:
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05/24/2005
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Publication #:
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Pub Dt:
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11/30/2006
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Title:
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SYSTEMS, METHODS, AND MEDIA FOR BLOCK-BASED ASSERTION GENERATION, QUALIFICATION AND ANALYSIS
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Patent #:
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Issue Dt:
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11/25/2008
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Application #:
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11136872
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Filing Dt:
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05/25/2005
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
Title:
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METHOD FOR AN EQUALIZER COMPUTATION IN A MEDIA SYSTEM USING A DATA SET SEPARATOR SEQUENCE
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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11137234
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Filing Dt:
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05/25/2005
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Publication #:
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Pub Dt:
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11/30/2006
| | | | |
Title:
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METHODS AND APPARATUS FOR REDUCING LEAKAGE CURRENT IN A DISABLED SOI CIRCUIT
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Patent #:
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Issue Dt:
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02/26/2008
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11137245
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Filing Dt:
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05/25/2005
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Publication #:
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Pub Dt:
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11/30/2006
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Title:
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CROSSTALK REDUCTION IN ELECTRICAL INTERCONNECTS USING DIFFERENTIAL SIGNALING
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Patent #:
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Issue Dt:
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07/29/2008
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Application #:
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11138797
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Filing Dt:
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05/26/2005
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Publication #:
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Pub Dt:
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05/18/2006
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Title:
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DEVICE COMPRISING DOPED NANO-COMPONENT AND METHOD OF FORMING THE DEVICE
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Patent #:
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Issue Dt:
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08/14/2007
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11140780
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Filing Dt:
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05/31/2005
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Publication #:
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Pub Dt:
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11/30/2006
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Title:
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MEMORY DEVICE AND METHOD OF MANUFACTURING THE DEVICE BY SIMULTANEOUSLY CONDITIONING TRANSITION METAL OXIDE LAYERS IN A PLURALITY OF MEMORY CELLS
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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11140803
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Filing Dt:
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05/31/2005
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Title:
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SERIAL INTERFACE HAVING A READ TEMPERATURE COMMAND
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Patent #:
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Issue Dt:
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03/04/2008
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11142566
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06/01/2005
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Pub Dt:
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12/07/2006
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Title:
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SYSTEM AND METHOD FOR CREATING A STANDARD CELL LIBRARY FOR REDUCED LEAKAGE AND IMPROVED PERFORMANCE
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Patent #:
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Issue Dt:
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10/07/2008
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11146441
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06/06/2005
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Pub Dt:
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12/07/2006
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Title:
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APPARATUS AND METHOD FOR FAR END NOISE REDUCTION USING CAPACITIVE CANCELLATION BY OFFSET WIRING
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Issue Dt:
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10/16/2007
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11146495
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06/06/2005
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Publication #:
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Pub Dt:
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12/07/2006
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Title:
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PLANAR ARRAY CONTACT MEMORY CARDS
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Issue Dt:
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06/17/2008
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11146863
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06/07/2005
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Publication #:
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Pub Dt:
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12/07/2006
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Title:
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MICROPROCESSOR INCLUDING A CONFIGURABLE TRANSLATION LOOKASIDE BUFFER
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Issue Dt:
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04/17/2007
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11147003
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Filing Dt:
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06/07/2005
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Title:
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HYSTERISIS MANAGEMENT FOR DELAY LINE
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Patent #:
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Issue Dt:
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06/29/2010
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11147383
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Filing Dt:
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06/08/2005
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Pub Dt:
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12/14/2006
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Title:
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RAISED SOURCE AND DRAIN PROCESS WITH DISPOSABLE SPACERS
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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11148737
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06/09/2005
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Publication #:
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Pub Dt:
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12/15/2005
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Title:
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SEMICONDUCTOR DEVICE WITH A HIGH THERMAL DISSIPATION EFFICIENCY
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Patent #:
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Issue Dt:
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05/22/2007
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11150188
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06/13/2005
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Pub Dt:
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12/14/2006
| | | | |
Title:
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METHOD AND STRUCTURE FOR HIGH PERFORMANCE PHASE CHANGE MEMORY
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