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02/02/2010
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11259644
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10/26/2005
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04/26/2007
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02/12/2008
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11259654
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10/26/2005
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04/26/2007
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05/06/2008
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11262101
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10/28/2005
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05/03/2007
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04/17/2007
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11262134
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10/28/2005
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03/16/2006
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12/11/2007
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11263138
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10/27/2005
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05/10/2007
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SELF SERIES TERMINATED SERIAL LINK TRANSMITTER HAVING SEGMENTATION FOR AMPLITUDE, PRE-EMPHASIS, AND SLEW RATE CONTROL AND VOLTAGE REGULATION FOR AMPLITUDE ACCURACY AND HIGH VOLTAGE PROTECTION
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09/29/2009
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11263189
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10/31/2005
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05/03/2007
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10/02/2007
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11263430
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10/31/2005
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03/16/2006
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SILICON-CONTAINING COMPOSITIONS FOR SPIN-ON ARC/HARDMASK MATERIALS
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05/27/2008
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11264446
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11/01/2005
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03/16/2006
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MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD
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03/25/2008
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11266741
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11/03/2005
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05/03/2007
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METHOD FOR FABRICATING AND BEOL INTERCONNECT STRUCTURES WITH SIMULTANEOUS FORMATION OF HIGH-K AND LOW-K DIELECTRIC REGIONS
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12/30/2008
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11267882
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11/04/2005
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03/16/2006
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10/16/2007
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11268106
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11/07/2005
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03/16/2006
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LOW K AND ULTRA LOW K SICOH DIELECTRIC FILMS AND METHODS TO FORM THE SAME
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07/14/2009
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11270029
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11/08/2005
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PROTECTION ELEMENT AND METHOD OF MANUFACTURE
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10/21/2008
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11270708
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11/09/2005
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04/13/2006
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METHOD OF FORMING AN INTEGRATED CIRCUIT STRUCTURE ON A HYBRID CRYSTAL ORIENTED SUBSTRATE
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02/05/2008
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11271032
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11/10/2005
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05/18/2006
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PROCESS OPTIONS OF FORMING SILICIDED METAL GATES FOR ADVANCED CMOS DEVICES
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04/01/2008
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11272884
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11/14/2005
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03/30/2006
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DATA PROCESSING IN DIGITAL SYSTEMS
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06/10/2008
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11275010
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12/01/2005
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06/14/2007
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MEMORY DEVICES USING CARBON NANOTUBE (CNT) TECHNOLOGIES
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10/28/2008
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11275035
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12/05/2005
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06/07/2007
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AUTOMATED SIMULATION TESTBENCH GENERATION FOR SERIALIZER/DESERIALIZER DATAPATH SYSTEMS
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06/14/2016
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11275091
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12/09/2005
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06/14/2007
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METHOD AND SYSTEM OF COMMUNICATING BETWEEN PEER PROCESSORS IN SoC ENVIRONMENT
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12/07/2010
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11275092
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12/09/2005
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07/19/2007
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METHOD AND SYSTEM OF COHERENT DESIGN VERIFICATION OF INTER-CLUSTER INTERACTIONS
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10/26/2010
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11275417
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12/30/2005
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07/05/2007
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PIXEL ARRAY, IMAGING SENSOR INCLUDING THE PIXEL ARRAY AND DIGITAL CAMERA INCLUDING THE IMAGING SENSOR
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12/30/2008
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11275482
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01/09/2006
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04/27/2006
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INTEGRATED CIRCUIT STRUCTURES FOR PREVENTING CHARGING DAMAGE
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04/14/2009
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11275492
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01/10/2006
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07/12/2007
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SRAM ARRAY AND ANALOG FET WITH DUAL-STRAIN LAYERS COMPRISING RELAXED REGIONS
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01/06/2009
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11275514
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01/11/2006
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07/12/2007
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SEMICONDUCTOR TRANSISTORS WITH EXPANDED TOP PORTIONS OF GATES
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07/01/2008
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11275540
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01/13/2006
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05/11/2006
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MEMORY ARRAY REPAIR WHERE REPAIR LOGIC CANNOT OPERATE AT SAME OPERATING CONDITION AS ARRAY
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10/13/2009
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11275604
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01/19/2006
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08/16/2007
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DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE
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11/20/2007
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11275638
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01/20/2006
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07/26/2007
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ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
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02/01/2011
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11276236
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02/20/2006
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08/23/2007
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PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS
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03/22/2011
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11276282
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02/22/2006
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08/23/2007
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METHOD OF FABRICATING A PRECISION BURIED RESISTOR
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05/12/2009
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11276366
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02/27/2006
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08/30/2007
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MULTI-ORIENTATION SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE, AND METHOD OF FABRICATING SAME
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07/14/2009
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11276369
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02/27/2006
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08/30/2007
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HIGH PERFORMANCE TAPERED VARACTOR
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08/14/2007
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11276380
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02/27/2006
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08/30/2007
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CHIP UNDERFILL IN FLIP-CHIP TECHNOLOGIES
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02/10/2009
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11276413
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02/28/2006
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08/30/2007
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MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST)
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05/05/2009
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11276433
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02/28/2006
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08/30/2007
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TESTING OF MULTIPLE ASYNCHRONOUS LOGIC DOMAINS
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11/11/2008
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11276451
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02/28/2006
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08/30/2007
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INTRINSIC RC POWER DISTRIBUTION FOR NOISE FILTERING OF ANALOG SUPPLIES
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04/28/2009
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11277306
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03/23/2006
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10/18/2007
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ERROR DETECTION AND CORRECTION IN SEMICONDUCTOR STRUCTURES
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07/22/2008
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11277315
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03/23/2006
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09/27/2007
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METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS
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07/22/2008
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11277385
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03/24/2006
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09/27/2007
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STATIC TIMING SLACKS ANALYSIS AND MODIFICATION
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04/29/2008
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11277677
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03/28/2006
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10/11/2007
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DUAL-PLANE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR
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12/11/2007
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11278169
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03/31/2006
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10/04/2007
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APPARATUS FOR IMPLEMENTING DYNAMIC DATA PATH WITH INTERLOCKED KEEPER AND RESTORE DEVICES
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11/18/2008
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11278262
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03/31/2006
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10/04/2007
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METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE
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10/11/2011
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11278618
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04/04/2006
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TRANSISTOR WITH ASYMMETRIC SILICON GERMANIUM SOURCE REGION
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06/02/2009
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11278840
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04/06/2006
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10/11/2007
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TIME WEIGHTED MOVING AVERAGE FILTER
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03/03/2009
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11278910
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04/06/2006
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07/27/2006
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PROTECTING SILICON GERMANIUM SIDEWALL WITH SILICON FOR STRAINED SILICON/SILICON MOSFETS
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07/15/2008
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11278924
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04/06/2006
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07/27/2006
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METHODOLOGY FOR PLACEMENT BASED ON CIRCUIT FUNCTION AND LATCHUP SENSITIVITY
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10/23/2007
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11279063
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04/07/2006
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10/11/2007
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INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF
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12/02/2008
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11279237
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04/10/2006
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10/18/2007
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METHODS AND READABLE MEDIA FOR USING RELATIVE POSITIONING IN STRUCTURES WITH DYNAMIC RANGES
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10/14/2008
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11279283
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04/11/2006
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10/11/2007
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VLSI ARTWORK LEGALIZATION FOR HIERARCHICAL DESIGNS WITH MULTIPLE GRID CONSTRAINTS
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09/09/2008
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11279312
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04/11/2006
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10/18/2007
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METHOD FOR VERIFYING PERFORMANCE OF AN ARRAY BY SIMULATING OPERATION OF EDGE CELLS IN A FULL ARRAY MODEL
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04/29/2008
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11279434
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04/12/2006
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10/18/2007
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VERTICAL PARALLEL PLATE CAPACITOR USING SPACER SHAPED ELECTRODES AND METHOD FOR FABRICATION THEREOF
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07/08/2008
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11279639
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04/13/2006
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11/08/2007
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DETERMINING RELATIVE AMOUNT OF USAGE OF DATA RETAINING DEVICE BASED ON POTENTIAL OF CHARGE STORING DEVICE
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01/01/2008
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11279981
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04/17/2006
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Title:
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COMPUTER GRAPHICS PROCESSING SYSTEM, COMPUTER MEMORY, AND METHOD OF USE WITH COMPUTER GRAPHICS PROCESSING SYSTEM UTILIZING HIERARCHICAL IMAGE DEPTH BUFFER
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07/28/2009
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11281032
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11/17/2005
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06/29/2006
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DEPOSITION OF HAFNIUM OXIDE AND/OR ZIRCONIUM OXIDE AND FABRICATION OF PASSIVATED ELECTRONIC STRUCTURES
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02/26/2008
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11281169
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11/17/2005
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10/05/2006
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TECHNIQUE FOR CD MEASUREMENT ON THE BASIS OF AREA FRACTION DETERMINATION
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04/08/2008
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11281688
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11/17/2005
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05/17/2007
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PRINTED CIRCUIT BOARD AND CHIP MODULE
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11/16/2010
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11285338
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11/22/2005
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05/24/2007
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SATISFIABILITY (SAT) BASED BOUNDED MODEL CHECKERS
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09/18/2007
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11286454
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11/23/2005
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Title:
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DELAY-LOCKED LOOP HAVING A PLURALITY OF LOCK MODES
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06/10/2008
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11289066
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11/29/2005
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05/31/2007
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GENERATION OF HARDWARE THERMAL PROFILES FOR A SET OF PROCESSORS
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12/23/2008
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11290787
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11/30/2005
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Title:
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THIN FILM GERMANIUM DIODE WITH LOW REVERSE BREAKDOWN
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Patent #:
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Issue Dt:
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10/28/2008
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Application #:
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11293774
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Filing Dt:
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12/02/2005
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Publication #:
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Pub Dt:
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04/20/2006
| | | | |
Title:
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ULTRA-THIN, HIGH QUALITY STRAINED SILICON-ON-INSULATOR FORMED BY ELASTIC STRAIN TRANSFER
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Patent #:
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Issue Dt:
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12/09/2008
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Application #:
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11297308
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Filing Dt:
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12/08/2005
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Publication #:
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Pub Dt:
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06/14/2007
| | | | |
Title:
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METHOD AND APPARATUS FOR PERFORMING TEMPORAL CHECKING
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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11297730
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Filing Dt:
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12/08/2005
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Publication #:
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Pub Dt:
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06/14/2007
| | | | |
Title:
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METHODS AND APPARATUS FOR INLINE VARIABILITY MEASUREMENT OF INTEGRATED CIRCUIT COMPONENTS
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Patent #:
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Issue Dt:
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09/16/2008
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Application #:
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11297856
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Filing Dt:
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12/09/2005
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Publication #:
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Pub Dt:
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06/14/2007
| | | | |
Title:
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MEMORY ACCESS REQUEST ARBITRATION
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Patent #:
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Issue Dt:
|
12/02/2008
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Application #:
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11298340
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Filing Dt:
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12/07/2005
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Title:
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SCANNER OPTIMIZATION FOR REDUCED ACROSS-CHIP PERFORMANCE VARIATION THROUGH NON-CONTACT ELECTRICAL METROLOGY
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Patent #:
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Issue Dt:
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11/06/2012
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Application #:
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11299071
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Filing Dt:
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12/09/2005
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Title:
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THERMAL THROTTLING OF PERIPHERAL COMPONENTS IN A PROCESSING DEVICE
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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11303103
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Filing Dt:
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12/16/2005
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Title:
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METHOD AND APPARATUS FOR HIERARCHICAL PROCESS CONTROL
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Patent #:
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Issue Dt:
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08/04/2009
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Application #:
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11303715
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Filing Dt:
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12/16/2005
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Publication #:
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Pub Dt:
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06/21/2007
| | | | |
Title:
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DUAL METAL GATE SELF-ALIGNED INTEGRATION
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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11303792
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Filing Dt:
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12/16/2005
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Publication #:
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Pub Dt:
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06/21/2007
| | | | |
Title:
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SYSTEM AND METHOD OF CRITICALITY PREDICTION IN STATISTICAL TIMING ANALYSIS
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Patent #:
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Issue Dt:
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05/18/2010
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Application #:
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11305584
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Filing Dt:
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12/16/2005
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Publication #:
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Pub Dt:
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06/21/2007
| | | | |
Title:
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FORMATION OF RAISED SOURCE/DRAIN STRUCTURES IN NFET WITH EMBEDDED SIGE IN PFET
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Patent #:
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Issue Dt:
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10/14/2008
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Application #:
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11306597
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Filing Dt:
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01/04/2006
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Publication #:
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Pub Dt:
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07/12/2007
| | | | |
Title:
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ELECTRICAL FUSES COMPRISING THIN FILM TRANSISTORS (TFTS), AND METHODS FOR PROGRAMMING SAME
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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11306663
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Filing Dt:
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01/05/2006
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Publication #:
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Pub Dt:
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09/21/2006
| | | | |
Title:
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SELECTABLE OPEN CIRCUIT AND ANTI-FUSE ELEMENT
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Patent #:
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Issue Dt:
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02/05/2008
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Application #:
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11306669
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Filing Dt:
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01/06/2006
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Publication #:
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Pub Dt:
|
07/12/2007
| | | | |
Title:
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TRENCH MEMORY
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Patent #:
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Issue Dt:
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09/06/2011
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Application #:
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11306670
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Filing Dt:
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01/06/2006
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Publication #:
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Pub Dt:
|
07/12/2007
| | | | |
Title:
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TRANSISTORS WITH GATE STACKS HAVING METAL ELECTRODES
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Patent #:
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Issue Dt:
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07/14/2009
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Application #:
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11306709
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Filing Dt:
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01/09/2006
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Publication #:
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Pub Dt:
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07/12/2007
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE INCLUDING TRENCH CAPACITOR AND TRENCH RESISTOR
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Patent #:
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Issue Dt:
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08/26/2008
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Application #:
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11306719
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Filing Dt:
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01/09/2006
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Publication #:
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Pub Dt:
|
07/12/2007
| | | | |
Title:
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AIR BREAK FOR IMPROVED SILICIDE FORMATION WITH COMPOSITE CAPS
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Patent #:
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Issue Dt:
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01/04/2011
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Application #:
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11306721
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Filing Dt:
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01/09/2006
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Publication #:
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Pub Dt:
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10/23/2008
| | | | |
Title:
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METHOD OF FORMING A CROSS-SECTION HOURGLASS SHAPED CHANNEL REGION FOR CHARGE CARRIER MOBILITY MODIFICATION
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Patent #:
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Issue Dt:
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09/08/2009
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Application #:
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11306746
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Filing Dt:
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01/10/2006
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Publication #:
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Pub Dt:
|
07/12/2007
| | | | |
Title:
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INTEGRATED CIRCUIT COMB CAPACITOR
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Patent #:
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Issue Dt:
|
11/27/2007
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Application #:
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11306827
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Filing Dt:
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01/12/2006
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Publication #:
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Pub Dt:
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07/26/2007
| | | | |
Title:
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METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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11306930
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Filing Dt:
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01/17/2006
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Publication #:
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Pub Dt:
|
07/19/2007
| | | | |
Title:
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METHOD OF MAKING A SEMICONDUCTOR STRUCTURE WITH A PLATING ENHANCEMENT LAYER
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Patent #:
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Issue Dt:
|
01/04/2011
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Application #:
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11306983
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Filing Dt:
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01/18/2006
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Publication #:
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Pub Dt:
|
07/19/2007
| | | | |
Title:
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METHOD FOR FABRICATING LAST LEVEL COPPER-TO-C4 CONNECTION
WITH INTERFACIAL CAP STRUCTURE
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Patent #:
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Issue Dt:
|
09/16/2008
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Application #:
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11307288
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Filing Dt:
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01/31/2006
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Publication #:
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Pub Dt:
|
12/14/2006
| | | | |
Title:
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SYSTEM FOR DISPATCHING SEMICONDUCTORS LOTS
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Patent #:
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Issue Dt:
|
03/31/2009
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Application #:
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11307294
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Filing Dt:
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01/31/2006
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Publication #:
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Pub Dt:
|
01/03/2008
| | | | |
Title:
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MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION
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Patent #:
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Issue Dt:
|
05/20/2008
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Application #:
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11307324
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Filing Dt:
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02/01/2006
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Publication #:
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Pub Dt:
|
10/11/2007
| | | | |
Title:
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STRUCTURE AND METHOD FOR THERMALLY STRESSING OR TESTING A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
07/01/2008
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Application #:
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11307404
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Filing Dt:
|
02/06/2006
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Publication #:
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Pub Dt:
|
08/09/2007
| | | | |
Title:
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PLANAR VERTICAL RESISTOR AND BOND PAD RESISTOR
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Patent #:
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Issue Dt:
|
11/25/2008
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Application #:
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11307481
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Filing Dt:
|
02/09/2006
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Publication #:
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Pub Dt:
|
08/09/2007
| | | | |
Title:
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CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS AND METHOD FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
|
12/04/2007
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Application #:
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11307640
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Filing Dt:
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02/15/2006
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Publication #:
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Pub Dt:
|
08/16/2007
| | | | |
Title:
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METROLOGY TOOL RECIPE VALIDATOR USING BEST KNOWN METHODS
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Patent #:
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Issue Dt:
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04/14/2009
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Application #:
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11307642
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Filing Dt:
|
02/15/2006
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Publication #:
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Pub Dt:
|
01/17/2008
| | | | |
Title:
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STRUCTURE AND METHOD OF CHEMICALLY FORMED ANCHORED METALLIC VIAS
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Patent #:
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Issue Dt:
|
04/15/2008
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Application #:
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11307762
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Filing Dt:
|
02/21/2006
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Publication #:
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Pub Dt:
|
08/23/2007
| | | | |
Title:
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POLY FILLED SUBSTRATE CONTACT ON SOI STRUCTURE
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Patent #:
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Issue Dt:
|
08/07/2007
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Application #:
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11307785
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Filing Dt:
|
02/22/2006
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Publication #:
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Pub Dt:
|
08/23/2007
| | | | |
Title:
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SYSTEM AND METHOD FOR INCREASING RELIABILITY OF ELECTRICAL FUSE PROGRAMMING
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Patent #:
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Issue Dt:
|
07/19/2011
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Application #:
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11307828
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Filing Dt:
|
02/24/2006
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Publication #:
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Pub Dt:
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08/30/2007
| | | | |
Title:
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STRUCTURE AND METHOD FOR RELIABILITY EVALUATION OF FCPBGA SUBSTRATES FOR HIGH POWER SEMICONDUCTOR PACKAGING APPLICATIONS
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Patent #:
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Issue Dt:
|
10/21/2008
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Application #:
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11307894
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Filing Dt:
|
02/27/2006
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Publication #:
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Pub Dt:
|
08/30/2007
| | | | |
Title:
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METHOD FOR TESTING THE VALIDITY OF INITIAL-CONDITION STATEMENTS IN CIRCUIT SIMULATION, AND CORRECTING INCONSISTENCIES THEREOF
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Patent #:
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Issue Dt:
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02/17/2009
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Application #:
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11308103
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Filing Dt:
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03/07/2006
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Publication #:
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Pub Dt:
|
09/13/2007
| | | | |
Title:
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TRENCH MEMORY WITH MONOLITHIC CONDUCTING MATERIAL AND METHODS FOR FORMING SAME
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Patent #:
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Issue Dt:
|
06/03/2008
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Application #:
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11308167
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Filing Dt:
|
03/09/2006
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Publication #:
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Pub Dt:
|
09/13/2007
| | | | |
Title:
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METHOD AND DEVICE INCLUDING REWORKABLE ALPHA PARTICLE BARRIER AND CORROSION BARRIER
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Patent #:
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Issue Dt:
|
05/20/2008
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Application #:
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11308394
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Filing Dt:
|
03/21/2006
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Publication #:
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Pub Dt:
|
09/27/2007
| | | | |
Title:
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RECESSING TRENCH TO TARGET DEPTH
USING FEED FORWARD DATA
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Patent #:
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Issue Dt:
|
02/05/2013
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Application #:
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11308396
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Filing Dt:
|
03/21/2006
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Publication #:
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Pub Dt:
|
09/27/2007
| | | | |
Title:
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STRUCTURE AND METHOD TO IMPROVE CURRENT-CARRYING CAPABILITIES OF C4 JOINTS
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Patent #:
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Issue Dt:
|
04/14/2009
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Application #:
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11308408
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Filing Dt:
|
03/22/2006
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Publication #:
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Pub Dt:
|
09/27/2007
| | | | |
Title:
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GROUNDING FRONT-END-OF-LINE STRUCTURES ON A SOI SUBSTRATE
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Patent #:
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Issue Dt:
|
10/19/2010
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Application #:
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11308422
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Filing Dt:
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03/23/2006
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Publication #:
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Pub Dt:
|
09/27/2007
| | | | |
Title:
|
SURFACE TREATMENT OF INTER-LAYER DIELECTRIC
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Patent #:
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Issue Dt:
|
12/02/2008
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Application #:
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11308432
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Filing Dt:
|
03/24/2006
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Publication #:
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Pub Dt:
|
09/27/2007
| | | | |
Title:
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METHOD OF MAKING FIELD TRANSISTOR WITH REDUCED THICKNESS GATE
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Patent #:
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Issue Dt:
|
05/27/2008
|
Application #:
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11308503
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Filing Dt:
|
03/30/2006
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Publication #:
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Pub Dt:
|
10/11/2007
| | | | |
Title:
|
SELECTIVE LINKS IN SILICON HETERO-JUNCTION BIPOLAR TRANSISTORS USING CARBON DOPING AND METHOD OF FORMING SAME
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Patent #:
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Issue Dt:
|
10/28/2008
|
Application #:
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11308516
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Filing Dt:
|
03/31/2006
|
Publication #:
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Pub Dt:
|
10/04/2007
| | | | |
Title:
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IMPROVED SOI SUBSTRATE AND SOI DEVICE, AND METHOD FOR FORMING THE SAME
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|
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Patent #:
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Issue Dt:
|
05/20/2008
|
Application #:
|
11308539
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Filing Dt:
|
04/04/2006
|
Publication #:
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Pub Dt:
|
10/04/2007
| | | | |
Title:
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METHOD AND STRUCTURE FOR ELIMINATING ALUMINUM TERMINAL PAD MATERIAL IN SEMICONDUCTOR DEVICES
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|