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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09295978
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Filing Dt:
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04/21/1999
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Title:
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APPARATUS AND METHOD FOR PROVIDING A WAIT FOR STATUS CHANGE CAPABILITY FOR A HOST COMPUTER SYSTEM
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Issue Dt:
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06/25/2002
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09296043
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04/21/1999
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Title:
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SEMICONDUCTOR WAFER ALIGNMENT METHOD USING AN IDENTIFICATION SCRIBE
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07/10/2001
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09296054
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Filing Dt:
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04/21/1999
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Title:
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APPARATUS AND METHOD OF ENCAPSULATED COPPER (CU) INTERCONNECT FORMATION
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01/01/2002
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09296551
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04/22/1999
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Title:
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INCREASED SPEED INITIALIZATION USING DYNAMIC SLOT ALLOCATION
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04/03/2001
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09296552
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Filing Dt:
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04/22/1999
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Title:
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OPTIMIZED TRENCH/VIA PROFILE FOR DAMASCENE FILLING
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09/25/2001
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09298690
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04/23/1999
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Title:
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MERCURY PROCESS GOLD BALLBOND REMOVAL APPARATUS
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09/02/2003
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09300762
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04/26/1999
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Title:
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POROUS POWER AND GROUND PLANES FOR REDUCED PCB DELAMINATION AND BETTER RELIABILITY
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08/29/2000
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09301050
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04/28/1999
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Title:
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METHOD AND APPARATUS FOR SLURRY POLISHING
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07/03/2001
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09301263
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Filing Dt:
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04/28/1999
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Title:
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SEPARATELY OPTIMIZED GATE STRUCTURES FOR N-CHANNEL AND P-CHANNEL TRANSISTORS IN AN INTEGRATED CIRCUIT
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06/26/2001
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09301887
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04/29/1999
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Title:
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DIELECTRIC ADHESION ENHANCEMENT IN DAMASCENE PROCESS FOR SEMICONDUCTORS
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06/24/2003
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09302371
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04/30/1999
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Title:
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APPARATUS AND METHOD OF IMPLEMENTING A HOME NETWORK BY FILTERING ISDN-BASED SIGNALS WITHIN THE CUSTOMER PREMISES
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02/27/2001
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09302634
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04/29/1999
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Title:
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INPUT STRUCTURE FOR I/O DEVICE
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10/22/2002
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09302639
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04/30/1999
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Title:
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METHOD AND APPARATUS FOR MULTIPHASE CHEMICAL MECHANICAL POLISHING
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01/01/2002
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09302737
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04/30/1999
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Title:
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CHEMICAL MECHANICAL POLISHING IN-SITU END POINT SYSTEM
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10/31/2000
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09302902
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04/30/1999
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Title:
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IMPEDANCE CONTROL USING FUSES
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04/17/2001
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09303042
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04/30/1999
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Title:
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CHIP THERMAL PROTECTION DEVICE
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03/06/2001
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09303187
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04/30/1999
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Title:
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AUTOMATED INSPECTION SYSTEM FOR METALLIC SURFACES
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11/05/2002
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09303277
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04/30/1999
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Title:
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METHOD AND STRUCTURES FOR DUAL DEPTH OXYGEN LAYERS IN SILICON-ON-INSULATOR PROCESSES
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10/02/2001
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09303696
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05/03/1999
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Title:
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CMOS PROCESSS WITH LOW THERMAL BUDGET
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02/27/2001
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09303959
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Filing Dt:
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05/03/1999
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Title:
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MOSFET WITH SUPPRESSED GATE-EDGE FRINGING FIELD EFFECT
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12/10/2002
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09304129
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05/03/1999
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12/20/2001
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Title:
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HIGH-K GATE DIELECTRIC PROCESS WITH SELF ALIGNED DAMASCENE CONTACT TO DAMASCENE GATE AND A LOW-K INTER LEVEL DIELECTRIC
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01/01/2002
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09304959
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05/05/1999
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Title:
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MULTIPORT COMMUNICATION SWITCH HAVING GIGAPORT AND EXPANSION PORTS SHARING THE SAME TIME SLOT IN INTERNAL RULES CHECKER
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Issue Dt:
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08/08/2000
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09305906
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05/05/1999
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Title:
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LOW DIELECTRIC CONSTANT COATING OF CONDUCTIVE MATERIAL IN A DAMASCENE PROCESS FOR SEMICONDUCTORS
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04/08/2003
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09306871
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05/07/1999
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Title:
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APPARATUS AND METHOD FOR DETECTING AN INVALID RESOURCE CONFIGURATION USING A PLURALITY OF BIT MASK REGISTERS COUPLED TO A STATUS REGISTER IN A SYSTEM HAVING A PLURALITY OF RESOURCES
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Issue Dt:
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05/06/2003
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09306879
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05/07/1999
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Title:
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REGISTER CHANGE SUMMARY RESOURCE
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Patent #:
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Issue Dt:
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02/19/2002
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09307085
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Filing Dt:
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05/07/1999
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Title:
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TIMER PROCESSING ENGINE FOR SUPPORTING MULTIPLE VIRTUAL MINIMUM TIME TIMERS
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09309105
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Filing Dt:
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05/10/1999
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Title:
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MOSFET-TYPE DEVICE WITH HIGHER DRIVER CURRENT AND LOWER STEADY STATE POWER DISSIPATION
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02/18/2003
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09310170
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05/11/1999
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Title:
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METHOD OF FORMING CMOS TRANSISTOR HAVING ULTRA SHALLOW SOURCE AND DRAIN REGIONS
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Issue Dt:
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11/19/2002
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09311361
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Filing Dt:
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05/13/1999
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Title:
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APPARATUS AND METHOD FOR SHARING AN EXTERNAL MEMORY BETWEEN MULTIPLE NETWORK SWITCHES
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Issue Dt:
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09/03/2002
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Application #:
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09311367
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Filing Dt:
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05/13/1999
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Title:
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METHOD AND APPARATUS FOR FINDING A MATCH ENTRY USING RECEIVE PORT NUMBER EMBEDDED IN THE PORT VECTOR
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Issue Dt:
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02/13/2001
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09311448
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Filing Dt:
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05/14/1999
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Title:
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MICROCONTROLLER HAVING A BLOCK OF LOGIC CONFIGURABLE TO PERFORM A SELECTED LOGIC FUNCTION AND TO PRODUCE OUTPUT SIGNALS COUPLED TO CORRESPONDING I/O PADS ACCORDING TO A PREDEFINED HARDWARE INTERFACE
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04/25/2000
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09311735
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05/14/1999
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Title:
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SEMICONDUCTOR INTERCONNECT BARRIER FOR FLUORINATED DIELECTRICS
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10/01/2002
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09311973
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05/14/1999
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Title:
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PROCESS FOR MANUFACTURING SELF-ALIGNED CORROSION STOP FOR COPPER C4 AND WIREBOND
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09/11/2001
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09312208
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Filing Dt:
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05/14/1999
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Title:
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SEMICONDUCTOR INTERCONNECT BARRIER OF BORON SILICON NITRIDE AND MANUFACTURING METHOD THEREFOR
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Issue Dt:
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07/30/2002
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09313670
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05/18/1999
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Title:
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DEADLOCK AVOIDANCE USING EXPONENTIAL BACKOFF
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Issue Dt:
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07/24/2001
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09313873
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Filing Dt:
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05/18/1999
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Title:
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STORE TO LOAD FORWARDING USING A DEPENDENCY LINK FILE
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Issue Dt:
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10/29/2002
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09314035
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Filing Dt:
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05/18/1999
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Title:
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LOAD/STORE UNIT HAVING PRE-CACHE AND POST-CACHE QUEUES FOR LOW LATENCY LOAD MEMORY OPERATIONS
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05/13/2003
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09314976
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05/20/1999
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Title:
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WEIGHTED ROUND ROBIN CELL ARCHITECTURE
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Issue Dt:
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09/23/2003
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09314977
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Filing Dt:
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05/20/1999
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Pub Dt:
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04/17/2003
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Title:
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APPARATUS AND METHOD IN A NETWORK SWITCH PORT FOR TRANSFERRING DATA BETWEEN BUFFER MEMORY AND TRANSMIT AND RECEIVE STATE MACHINES ACCORDING TO A PRESCRIBED INTERFACE PROTOCOL
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Issue Dt:
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12/05/2000
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09315458
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05/20/1999
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Title:
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REDUNDANCY CIRCUIT AND METHOD FOR SEMICONDUCTOR MEMORY
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Issue Dt:
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02/13/2001
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Application #:
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09315459
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Filing Dt:
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05/20/1999
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Title:
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LAYEROUT FOR SEMICONDUCTOR MEMORY INCLUDING MULTI-LEVEL SENSING
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01/07/2003
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09315724
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05/21/1999
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Title:
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METHOD AND APPARATUS FOR RECLAIMING BUFFERS USING A SINGLE BUFFER BIT
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03/25/2003
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09315804
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05/21/1999
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Title:
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METHOD AND DEVICE FOR IDENTIFICATION OF A SUBSTANCE
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Issue Dt:
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03/18/2003
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09315854
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05/21/1999
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Title:
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METHOD AND APPARATUS IN A NETWORK SWITCH FOR HANDLING LINK FAILURE AND LINK RECOVERY IN A TRUNKED DATA PATH
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Issue Dt:
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10/01/2002
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Application #:
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09316073
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Filing Dt:
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05/21/1999
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Title:
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METHOD AND APPARATUS FOR PORT VECTOR DETERMINATION AT EGRESS
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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09316084
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Filing Dt:
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05/21/1999
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Title:
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METHOD AND APPARATUS FOR MAINTAINING RANDOMLY ACCESSIBLE FREE BUFFER INFORMATION FOR A NETWORK SWITCH
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Issue Dt:
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04/20/2004
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09316184
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05/21/1999
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Title:
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APPARATUS AND METHOD FOR PROGRAMMABLY MODIFYING A LIMIT OF A RETRY COUNTER IN A NETWORK SWITCH PORT IN RESPONSE TO EXERTING BACKPRESSURE
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Issue Dt:
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05/13/2003
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Application #:
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09316185
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Filing Dt:
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05/21/1999
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Title:
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APPARATUS AND METHOD FOR MODIFYING A LIMIT OF A RETRY COUNTER IN A NETWORK SWITCH PORT IN RESPONSE TO EXERTING BACKPRESSURE
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Patent #:
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Issue Dt:
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01/20/2004
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Application #:
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09317145
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Filing Dt:
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05/24/1999
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Title:
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METHOD AND APPARATUS FOR SUPPORT OF TAGGING AND UNTAGGING PER VLAN PER PORT
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Patent #:
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Issue Dt:
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06/04/2002
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09317147
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Filing Dt:
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05/24/1999
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Title:
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A SPLIT-QUEUE ARCHITECTURE WITH A FIRST QUEUE AREA AND A SECOND QUEUE AREA AND QUEUE OVERFLOW AREA HAVING A TRICKLE MODE AND AN OVERFLOW MODE BASED ON PRESCRIBED THRESHOLD VALUES
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Issue Dt:
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04/18/2006
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09317156
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05/24/1999
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Title:
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APPARATUS AND METHOD FOR PROGRAMMABLE MEMORY ACCESS SLOT ASSIGNMENT
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Patent #:
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Issue Dt:
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05/01/2001
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Application #:
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09317157
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Filing Dt:
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05/24/1999
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Title:
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REMOVABLE PHOTORESIST SPACERS IN CMOS TRANSISTOR FABRICATION
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Issue Dt:
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08/15/2000
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Application #:
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09318145
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Filing Dt:
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05/25/1999
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Title:
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VARIABLE GAIN RF AMPLIFIER WITH SWITCHABLE BIAS INJECTION AND FEEDBACK
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Issue Dt:
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04/03/2001
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Application #:
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09318148
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Filing Dt:
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05/25/1999
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Title:
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GENERAL PURPOSE DYNAMICALLY PROGRAMMABLE STATE ENGINE FOR EXECUTING FINITE STATE MACHINES
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Issue Dt:
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02/27/2001
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Application #:
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09318519
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Filing Dt:
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05/25/1999
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Title:
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CHANNEL FORMATION AFTER SOURCE AND DRAIN REGIONS ARE FORMED
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Issue Dt:
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07/30/2002
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09318782
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Filing Dt:
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05/25/1999
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Title:
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SELECTIVELY REDUCING TRANSISTOR CHANNEL LENGTH IN A SEMICONDUCTOR DEVICE
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Issue Dt:
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01/02/2001
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Application #:
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09318824
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Filing Dt:
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05/26/1999
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Title:
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FORMATION OF JUNCTIONS BY DIFFUSION FROM A DOPED AMORPHOUS SILICON FILM DURING SILICIDATION
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Issue Dt:
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12/11/2001
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Application #:
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09320417
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Filing Dt:
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05/26/1999
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Title:
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METHOD TO PRODUCE HIGH DENSITY MEMORY CELLS AND SMALL SPACES BY USING NITRIDE SPACER
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Issue Dt:
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02/22/2000
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09320534
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05/26/1999
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Title:
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ADJUSTMENT OF PARTICLE BEAM LANDING ANGLE
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Issue Dt:
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08/13/2002
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Application #:
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09320612
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Filing Dt:
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05/26/1999
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Title:
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DUAL-RIE STRUCTURE FOR VIA/LINE INTERCONNECTIONS
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02/04/2003
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09321582
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05/28/1999
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Title:
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METHOD AND APPARATUS FOR MANIPULATING VLAN TAGS
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Issue Dt:
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09/23/2003
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Application #:
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09321833
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Filing Dt:
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05/28/1999
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Title:
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METHOD AND APPARATUS FOR OPERATING A NETWORK SWITCH IN A CPU-LESS ENVIRONMENT
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Issue Dt:
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10/08/2002
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09321834
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Filing Dt:
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05/28/1999
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Title:
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POWER MANAGEMENT INDICATION MECHANISM FOR SUPPORTING POWER SAVING MODE IN COMPUTER SYSTEM
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Issue Dt:
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11/18/2003
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09321842
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Filing Dt:
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05/28/1999
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Title:
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MULTI-PHASE EEPROM READING FOR NETWORK INTERFACE INITIALIZATION
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Patent #:
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Issue Dt:
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05/04/2004
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09322132
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Filing Dt:
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05/27/1999
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Title:
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PROMOTING ADHESION BETWEEN A POLYMER AND A METALLILC SUBSTRATE
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Issue Dt:
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02/13/2001
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Application #:
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09322546
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Filing Dt:
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05/28/1999
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Title:
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MASK QUALITY MEASUREMENTS BY FOURIER SPACE ANALYSIS
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Issue Dt:
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09/03/2002
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Application #:
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09323321
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Filing Dt:
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06/01/1999
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Title:
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COMPUTER SYSTEM INCLUDING A NOVEL ADDRESS TRANSLATION MECHANISM
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Patent #:
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Issue Dt:
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01/06/2004
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Application #:
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09323469
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Filing Dt:
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06/01/1999
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Title:
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INSERTION OF SCAN HARDWARE
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Patent #:
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Issue Dt:
|
02/05/2002
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Application #:
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09323804
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Filing Dt:
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06/02/1999
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Title:
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THIN-FILM FIELD-EFFECT TRANSISTOR WITH ORGANIC SEMICONDUCTOR REQUIRING LOW OPERATING VOLTAGES
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Patent #:
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Issue Dt:
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07/04/2000
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Application #:
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09323818
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Filing Dt:
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06/02/1999
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Title:
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COBALT SILICIDATION USING TUNGSTEN NITRIDE CAPPING LAYER
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09324183
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Filing Dt:
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06/02/1999
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Title:
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METHOD AND APPARATUS FOR MINIMIZING PARASITIC RESISTANCE OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
|
07/03/2001
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Application #:
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09324462
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Filing Dt:
|
06/02/1999
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Title:
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IMPROVED DEVICE WITH LOWER LDD RESISTANCE
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Patent #:
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Issue Dt:
|
06/05/2001
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Application #:
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09324879
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Filing Dt:
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06/02/1999
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Title:
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DEVICE IMPROVEMENT BY LOWERING LDD RESISTANCE WITH NEW SILICIDE PROCESS
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Patent #:
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Issue Dt:
|
02/13/2001
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Application #:
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09325023
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Filing Dt:
|
06/03/1999
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Title:
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METHOD FOR FABRICATION OF A LOW RESISTIVITY MOSFET GATE WITH THICK METAL SILICIDE ON POLYSILICON
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Patent #:
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Issue Dt:
|
02/12/2002
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Application #:
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09325942
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Filing Dt:
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06/04/1999
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Publication #:
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Pub Dt:
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11/29/2001
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Title:
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MODIFIED GATE CONDUCTOR PROCESSING FOR POLY LENGTH CONTROL IN HIGH DENSITY DRAMS
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Patent #:
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Issue Dt:
|
09/09/2003
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Application #:
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09326304
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Filing Dt:
|
06/04/1999
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Title:
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COMPUTER INTERCONNECTION BUS LINK LAYER
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Patent #:
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Issue Dt:
|
06/19/2001
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Application #:
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09326437
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Filing Dt:
|
06/04/1999
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Title:
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METHOD AND STRUCTURE FOR A SEMICONDUCTOR FUSE
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Patent #:
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Issue Dt:
|
02/13/2001
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Application #:
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09328148
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Filing Dt:
|
06/08/1999
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Title:
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CVD PLASMA PROCESS TO FILL CONTACT HOLE IN DAMASCENE PROCESS
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Patent #:
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Issue Dt:
|
05/06/2003
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Application #:
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09328189
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Filing Dt:
|
06/08/1999
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Title:
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STRAIN RELIEF FOR SUBSTRATES HAVING A LOW COEFFICIENT OF THERMAL EXPANSION
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Patent #:
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Issue Dt:
|
02/05/2002
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Application #:
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09328940
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Filing Dt:
|
06/09/1999
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Title:
|
GEAR BOX FOR MULTIPLE CLOCK DOMAINS
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Patent #:
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Issue Dt:
|
08/21/2001
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Application #:
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09329153
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Filing Dt:
|
06/09/1999
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Title:
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REVERSE LITHOGRAPHIC PROCESS FOR SEMICONDUTOR SPACES
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Patent #:
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Issue Dt:
|
01/09/2001
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Application #:
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09329155
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Filing Dt:
|
06/09/1999
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Title:
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LOW ENERGY PASSIVATION OF CONDUCTIVE MATERIAL IN DAMASCENE PROCESS FOR SEMICONDUCTORS
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|
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Patent #:
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Issue Dt:
|
08/27/2002
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Application #:
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09329497
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Filing Dt:
|
06/10/1999
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Title:
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APPARATUS AND METHOD FOR SUPERFORWARDING LOAD OPERANDS IN A MICROPROCESSOR
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|
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Patent #:
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Issue Dt:
|
03/20/2001
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Application #:
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09329843
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Filing Dt:
|
06/11/1999
|
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Title:
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METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A GROWN POLYSILICON LAYER
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Patent #:
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Issue Dt:
|
09/24/2002
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Application #:
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09330636
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Filing Dt:
|
06/11/1999
|
|
Title:
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PACKET PROTOCOL FOR READING AN INDETERMINATE NUMBER OF DATA BYTES ACROSS A COMPUTER INTERCONNECTION BUS
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|
|
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Patent #:
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|
Issue Dt:
|
07/16/2002
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Application #:
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09330637
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Filing Dt:
|
06/11/1999
|
|
Title:
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DETECTING A NO-TAGS-FREE CONDITION IN A COMPUTER SYSTEM HAVING MULTIPLE OUTSTANDING TRANSACTIONS
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Patent #:
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Issue Dt:
|
01/13/2004
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Application #:
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09330803
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Filing Dt:
|
06/11/1999
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|
Publication #:
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Pub Dt:
|
06/27/2002
| | | | |
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Title:
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INTRALEVEL DECOUPLING CAPACITOR, METHOD OF MANUFACTURE AND TESTING CIRCUIT OF THE SAME
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|
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Patent #:
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|
Issue Dt:
|
07/03/2001
|
Application #:
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09334121
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Filing Dt:
|
06/15/1999
|
|
Title:
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MOS TRANSISTOR WITH DUAL POCKET IMPLANT
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|
|
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Patent #:
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Issue Dt:
|
10/16/2001
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Application #:
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09334171
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Filing Dt:
|
06/15/1999
|
|
Title:
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PLACEMENT OF CONDUCTIVE STRIPES IN ELECTRONIC CIRCUITS TO SATISFY METAL DENSITY REQUIREMENTS
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|
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Patent #:
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|
Issue Dt:
|
10/23/2001
|
Application #:
|
09334926
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Filing Dt:
|
06/17/1999
|
|
Title:
|
MODULATION OF GATE POLYSILICON DOPING PROFILE BY SIDEWALL IMPLANTATION
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Patent #:
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|
Issue Dt:
|
09/05/2000
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Application #:
|
09335092
|
Filing Dt:
|
06/17/1999
|
|
Title:
|
SENSE AMPLIFIER AND METHOD OF USING THE SAME WITH PIPELINED READ, RESTORE AND WRITE OPERATIONS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/19/2002
|
Application #:
|
09335093
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Filing Dt:
|
06/17/1999
|
|
Title:
|
PROCESS FOR INSPECTING AN OBJECT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/19/2002
|
Application #:
|
09335405
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Filing Dt:
|
06/17/1999
|
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATIC ROUTING FOR REENTRANT PROCESS
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|
|
|
|
Patent #:
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|
Issue Dt:
|
06/04/2002
|
Application #:
|
09336619
|
Filing Dt:
|
06/18/1999
|
|
Title:
|
SUB-LITHOGRAPHIC CONTACTS AND VIAS THROUGH PATTERN, CVD AND ETCH BACK PROCESSING
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/16/2004
|
Application #:
|
09336711
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Filing Dt:
|
06/21/1999
|
|
Title:
|
ADAPTIVE ENERGY DETECTOR GAIN CONTROL IN PHYSICAL LAYER TRANSCEIVER FOR HOME TELEPHONE WIRE NETWORK
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|
|
|
|
Patent #:
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|
Issue Dt:
|
11/20/2001
|
Application #:
|
09338516
|
Filing Dt:
|
06/23/1999
|
|
Title:
|
BORDERLESS VIAS WITH HSQ GAP FILLED METAL PATTERNS HAVING HIGH ETCHING RESISTANCE
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|
|
|
|
Patent #:
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|
Issue Dt:
|
03/06/2001
|
Application #:
|
09338964
|
Filing Dt:
|
06/24/1999
|
|
Title:
|
BALL GRID ARRAY PACKAGE HAVING THERMOELECTRIC COOLER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2002
|
Application #:
|
09339783
|
Filing Dt:
|
06/24/1999
|
|
Title:
|
WAFER METROLOGY STRUCTURE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09340419
|
Filing Dt:
|
06/28/1999
|
|
Title:
|
STACKED MULTI-CHIP MODULES USING C4 INTERCONNECT TECHNOLOGY HAVING IMPROVED THERMAL MANAGEMENT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2002
|
Application #:
|
09340804
|
Filing Dt:
|
06/28/1999
|
|
Title:
|
CAPTURING SYNCHRONOUS DRAM FAILS IN A WORKING ENVIRONMENT
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|
