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Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
Total properties: 13706
Page 44 of 138
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138
1
Patent #:
7818542
Issue Dt:
10/19/2010
Application #:
11775451
Filing Dt:
07/10/2007
Publication #:
US20090019263
Pub Dt:
01/15/2009
Title:
METHOD AND APPARATUS FOR LENGTH DECODING VARIABLE LENGTH INSTRUCTIONS
2
Patent #:
7818543
Issue Dt:
10/19/2010
Application #:
11775456
Filing Dt:
07/10/2007
Publication #:
US20090019257
Pub Dt:
01/15/2009
Title:
METHOD AND APPARATUS FOR LENGTH DECODING AND IDENTIFYING BOUNDARIES OF VARIABLE LENGTH INSTRUCTIONS
3
Patent #:
7895028
Issue Dt:
02/22/2011
Application #:
11775531
Filing Dt:
07/10/2007
Publication #:
US20090016129
Pub Dt:
01/15/2009
Title:
DESIGN STRUCTURE FOR INCREASING FUSE PROGRAMMING YIELD
4
Patent #:
7521760
Issue Dt:
04/21/2009
Application #:
11775607
Filing Dt:
07/10/2007
Publication #:
US20070257314
Pub Dt:
11/08/2007
Title:
INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF
5
Patent #:
7737501
Issue Dt:
06/15/2010
Application #:
11776118
Filing Dt:
07/11/2007
Publication #:
US20090014798
Pub Dt:
01/15/2009
Title:
FINFET SRAM WITH ASYMMETRIC GATE AND METHOD OF MANUFACTURE THEREOF
6
Patent #:
7638428
Issue Dt:
12/29/2009
Application #:
11776155
Filing Dt:
07/11/2007
Publication #:
US20080128912
Pub Dt:
06/05/2008
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
7
Patent #:
7476578
Issue Dt:
01/13/2009
Application #:
11776710
Filing Dt:
07/12/2007
Publication #:
US20090017584
Pub Dt:
01/15/2009
Title:
PROCESS FOR FINFET SPACER FORMATION
8
Patent #:
7855104
Issue Dt:
12/21/2010
Application #:
11776738
Filing Dt:
07/12/2007
Publication #:
US20070259490
Pub Dt:
11/08/2007
Title:
STRUCTURE AND METHOD FOR LATCHUP SUPPRESSION
9
Patent #:
8020073
Issue Dt:
09/13/2011
Application #:
11776810
Filing Dt:
07/12/2007
Publication #:
US20090019341
Pub Dt:
01/15/2009
Title:
DYNAMIC MEMORY ARCHITECTURE EMPLOYING PASSIVE EXPIRATION OF DATA
10
Patent #:
7895421
Issue Dt:
02/22/2011
Application #:
11776986
Filing Dt:
07/12/2007
Publication #:
US20090019317
Pub Dt:
01/15/2009
Title:
MECHANISM FOR USING PERFORMANCE COUNTERS TO IDENTIFY REASONS AND DELAY TIMES FOR INSTRUCTIONS THAT ARE STALLED DURING RETIREMENT
11
Patent #:
7548822
Issue Dt:
06/16/2009
Application #:
11777329
Filing Dt:
07/13/2007
Publication #:
US20090018787
Pub Dt:
01/15/2009
Title:
APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PRODUCED BY AN INTEGRATED CIRCUIT
12
Patent #:
7882890
Issue Dt:
02/08/2011
Application #:
11777837
Filing Dt:
07/13/2007
Publication #:
US20090014155
Pub Dt:
01/15/2009
Title:
THERMALLY PUMPED LIQUID/GAS HEAT EXCHANGER FOR COOLING HEAT-GENERATING DEVICES
13
Patent #:
7911001
Issue Dt:
03/22/2011
Application #:
11778045
Filing Dt:
07/15/2007
Publication #:
US20090014808
Pub Dt:
01/15/2009
Title:
METHODS FOR FORMING SELF-ALIGNED DUAL STRESS LINERS FOR CMOS SEMICONDUCTOR DEVICES
14
Patent #:
7915670
Issue Dt:
03/29/2011
Application #:
11778185
Filing Dt:
07/16/2007
Publication #:
US20090020806
Pub Dt:
01/22/2009
Title:
ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
15
Patent #:
7732859
Issue Dt:
06/08/2010
Application #:
11778209
Filing Dt:
07/16/2007
Publication #:
US20090020764
Pub Dt:
01/22/2009
Title:
GRAPHENE-BASED TRANSISTOR
16
Patent #:
7692254
Issue Dt:
04/06/2010
Application #:
11778217
Filing Dt:
07/16/2007
Publication #:
US20090020819
Pub Dt:
01/22/2009
Title:
FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE
17
Patent #:
8709887
Issue Dt:
04/29/2014
Application #:
11778238
Filing Dt:
07/16/2007
Publication #:
US20080014692
Pub Dt:
01/17/2008
Title:
METHOD FOR FABRICATING A NITRIDED SILICON-OXIDE GATE DIELECTRIC
18
Patent #:
7562281
Issue Dt:
07/14/2009
Application #:
11778641
Filing Dt:
07/16/2007
Publication #:
US20080016416
Pub Dt:
01/17/2008
Title:
AUTONOMIC PARITY EXCHANGE
19
Patent #:
7718529
Issue Dt:
05/18/2010
Application #:
11778852
Filing Dt:
07/17/2007
Publication #:
US20090023298
Pub Dt:
01/22/2009
Title:
INVERSE SELF-ALIGNED SPACER LITHOGRAPHY
20
Patent #:
7811923
Issue Dt:
10/12/2010
Application #:
11778876
Filing Dt:
07/17/2007
Publication #:
US20090023284
Pub Dt:
01/22/2009
Title:
INTEGRATED WAFER PROCESSING SYSTEM FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS
21
Patent #:
8652913
Issue Dt:
02/18/2014
Application #:
11778930
Filing Dt:
07/17/2007
Publication #:
US20080182371
Pub Dt:
07/31/2008
Title:
METHOD FOR FORMING SILICON/GERMANIUM CONTAINING DRAIN/SOURCE REGIONS IN TRANSISTORS WITH REDUCED SILICON/GERMANIUM LOSS
22
Patent #:
8055925
Issue Dt:
11/08/2011
Application #:
11779432
Filing Dt:
07/18/2007
Publication #:
US20090024862
Pub Dt:
01/22/2009
Title:
STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS
23
Patent #:
7930485
Issue Dt:
04/19/2011
Application #:
11780283
Filing Dt:
07/19/2007
Publication #:
US20090024835
Pub Dt:
01/22/2009
Title:
SPECULATIVE MEMORY PREFETCH
24
Patent #:
7906390
Issue Dt:
03/15/2011
Application #:
11780519
Filing Dt:
07/20/2007
Publication #:
US20090020827
Pub Dt:
01/22/2009
Title:
THIN GATE ELECTRODE CMOS DEVICES AND METHODS OF FABRICATING SAME
25
Patent #:
8016482
Issue Dt:
09/13/2011
Application #:
11780530
Filing Dt:
07/20/2007
Publication #:
US20090022203
Pub Dt:
01/22/2009
Title:
METHOD AND SYSTEMS OF POWERING ON INTEGRATED CIRCUIT
26
Patent #:
7818696
Issue Dt:
10/19/2010
Application #:
11780712
Filing Dt:
07/20/2007
Publication #:
US20080027664
Pub Dt:
01/31/2008
Title:
ARCHITECTURAL LEVEL THROUGHPUT BASED POWER MODELING METHODOLOGY AND APPARATUS FOR PERVASIVELY CLOCK-GATED PROCESSOR CORES
27
Patent #:
8036860
Issue Dt:
10/11/2011
Application #:
11781363
Filing Dt:
07/23/2007
Publication #:
US20090031305
Pub Dt:
01/29/2009
Title:
MODELING HOMOGENEOUS PARALLELISM
28
Patent #:
7399665
Issue Dt:
07/15/2008
Application #:
11781370
Filing Dt:
07/23/2007
Publication #:
US20070262345
Pub Dt:
11/15/2007
Title:
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
29
Patent #:
8037034
Issue Dt:
10/11/2011
Application #:
11781833
Filing Dt:
07/23/2007
Publication #:
US20070285958
Pub Dt:
12/13/2007
Title:
METHODS OF CREATING A DICTIONARY FOR DATA COMPRESSION
30
Patent #:
7645641
Issue Dt:
01/12/2010
Application #:
11781854
Filing Dt:
07/23/2007
Publication #:
US20090027860
Pub Dt:
01/29/2009
Title:
COOLING DEVICE WITH A PREFORMED COMPLIANT INTERFACE
31
Patent #:
7751267
Issue Dt:
07/06/2010
Application #:
11782071
Filing Dt:
07/24/2007
Publication #:
US20090027983
Pub Dt:
01/29/2009
Title:
HALF-SELECT COMPLIANT MEMORY CELL PRECHARGE CIRCUIT
32
Patent #:
7859044
Issue Dt:
12/28/2010
Application #:
11782079
Filing Dt:
07/24/2007
Publication #:
US20090026523
Pub Dt:
01/29/2009
Title:
PARTIALLY GATED FINFET WITH GATE DIELECTRIC ON ONLY ONE SIDEWALL
33
Patent #:
7705352
Issue Dt:
04/27/2010
Application #:
11782734
Filing Dt:
07/25/2007
Publication #:
US20080157075
Pub Dt:
07/03/2008
Title:
TEST STRUCTURE FOR ESTIMATING ELECTROMIGRATION EFFECTS WITH INCREASED ROBUSTNESS WITH RESPECT TO BARRIER DEFECTS IN VIAS
34
Patent #:
7480170
Issue Dt:
01/20/2009
Application #:
11782808
Filing Dt:
07/25/2007
Publication #:
US20090027946
Pub Dt:
01/29/2009
Title:
METHOD AND APPARATUS FOR IMPLEMENTING ENHANCED SRAM READ PERFORMANCE SORT RING OSCILLATOR (PSRO)
35
Patent #:
7818592
Issue Dt:
10/19/2010
Application #:
11788215
Filing Dt:
04/18/2007
Publication #:
US20080263373
Pub Dt:
10/23/2008
Title:
TOKEN BASED POWER CONTROL MECHANISM
36
Patent #:
7906426
Issue Dt:
03/15/2011
Application #:
11788969
Filing Dt:
04/23/2007
Publication #:
US20080258308
Pub Dt:
10/23/2008
Title:
METHOD OF CONTROLLED LOW-K VIA ETCH FOR CU INTERCONNECTIONS
37
Patent #:
7387925
Issue Dt:
06/17/2008
Application #:
11799261
Filing Dt:
04/10/2007
Publication #:
US20070218621
Pub Dt:
09/20/2007
Title:
INTEGRATION OF STRAINED GE INTO ADVANCED CMOS TECHNOLOGY
38
Patent #:
8592312
Issue Dt:
11/26/2013
Application #:
11811418
Filing Dt:
06/07/2007
Publication #:
US20080305617
Pub Dt:
12/11/2008
Title:
METHOD FOR DEPOSITING A CONDUCTIVE CAPPING LAYER ON METAL LINES
39
Patent #:
7865789
Issue Dt:
01/04/2011
Application #:
11819748
Filing Dt:
06/28/2007
Publication #:
US20080215945
Pub Dt:
09/04/2008
Title:
SYSTEM AND METHOD FOR SYSTEM-ON-CHIP INTERCONNECT VERIFICATION
40
Patent #:
7348252
Issue Dt:
03/25/2008
Application #:
11820713
Filing Dt:
06/19/2007
Publication #:
US20070249144
Pub Dt:
10/25/2007
Title:
METHOD OF FORMING SILICON-ON-INSULATOR WAFER HAVING REENTRANT SHAPE DIELECTRIC TRENCHES
41
Patent #:
8678271
Issue Dt:
03/25/2014
Application #:
11823056
Filing Dt:
06/26/2007
Publication #:
US20090001138
Pub Dt:
01/01/2009
Title:
Method for preventing void formation in a solder joint
42
Patent #:
7882309
Issue Dt:
02/01/2011
Application #:
11828382
Filing Dt:
07/26/2007
Publication #:
US20090031088
Pub Dt:
01/29/2009
Title:
METHOD AND APPARATUS FOR HANDLING EXCESS DATA DURING MEMORY ACCESS
43
Patent #:
7761690
Issue Dt:
07/20/2010
Application #:
11828705
Filing Dt:
07/26/2007
Publication #:
US20090031111
Pub Dt:
01/29/2009
Title:
METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY SELECTING COMPILED INSTRUCTIONS
44
Patent #:
7930592
Issue Dt:
04/19/2011
Application #:
11829187
Filing Dt:
07/27/2007
Publication #:
US20080022149
Pub Dt:
01/24/2008
Title:
ENABLING MEMORY REDUNDANCY DURING TESTING
45
Patent #:
7607061
Issue Dt:
10/20/2009
Application #:
11830116
Filing Dt:
07/30/2007
Publication #:
US20090037788
Pub Dt:
02/05/2009
Title:
SHRINK TEST MODE TO IDENTIFY NTH ORDER SPEED PATHS
46
Patent #:
7496251
Issue Dt:
02/24/2009
Application #:
11830200
Filing Dt:
07/30/2007
Publication #:
US20080019633
Pub Dt:
01/24/2008
Title:
APPARATUS AND METHODS FOR INTEGRALLY PACKAGING OPTOELECTRONIC DEVICES, IC CHIPS AND OPTICAL TRANSMISSION LINES
47
Patent #:
7928419
Issue Dt:
04/19/2011
Application #:
11830213
Filing Dt:
07/30/2007
Publication #:
US20080314739
Pub Dt:
12/25/2008
Title:
ELECTROLYTIC DEVICE BASED ON A SOLUTION-PROCESSED ELECTROLYTE
48
Patent #:
7459981
Issue Dt:
12/02/2008
Application #:
11830221
Filing Dt:
07/30/2007
Publication #:
US20080030280
Pub Dt:
02/07/2008
Title:
CIRCUITS AND METHODS FOR IMPLEMENTING TRANSFORMER-COUPLED AMPLIFIERS AT MILLIMETER WAVE FREQUENCIES
49
Patent #:
8378469
Issue Dt:
02/19/2013
Application #:
11830239
Filing Dt:
07/30/2007
Publication #:
US20130016023
Pub Dt:
01/17/2013
Title:
APPARATUS AND METHODS FOR PACKAGING ANTENNAS WITH INTEGRATED CIRCUIT CHIPS FOR MILLIMETER WAVE APPLICATIONS
50
Patent #:
8110465
Issue Dt:
02/07/2012
Application #:
11830316
Filing Dt:
07/30/2007
Publication #:
US20090032889
Pub Dt:
02/05/2009
Title:
FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE
51
Patent #:
7619276
Issue Dt:
11/17/2009
Application #:
11830328
Filing Dt:
07/30/2007
Publication #:
US20090032859
Pub Dt:
02/05/2009
Title:
FINFET FLASH MEMORY DEVICE WITH AN EXTENDED FLOATING BACK GATE
52
Patent #:
7751924
Issue Dt:
07/06/2010
Application #:
11830349
Filing Dt:
07/30/2007
Publication #:
US20090037016
Pub Dt:
02/05/2009
Title:
C4NP SERVO CONTROLLED SOLDER FILL HEAD
53
Patent #:
7423303
Issue Dt:
09/09/2008
Application #:
11830464
Filing Dt:
07/30/2007
Publication #:
US20070262361
Pub Dt:
11/15/2007
Title:
STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS
54
Patent #:
7425483
Issue Dt:
09/16/2008
Application #:
11830489
Filing Dt:
07/30/2007
Publication #:
US20070269945
Pub Dt:
11/22/2007
Title:
STRUCTURE AND METHOD OF FABRICATING A HYBRID SUBSTRATE FOR HIGH-PERFORMANCE HYBRID-ORIENTATION SILICON-ON-INSULATOR CMOS DEVICES
55
Patent #:
7537985
Issue Dt:
05/26/2009
Application #:
11830872
Filing Dt:
07/31/2007
Publication #:
US20070269950
Pub Dt:
11/22/2007
Title:
DOUBLE GATE ISOLATION
56
Patent #:
7960036
Issue Dt:
06/14/2011
Application #:
11831005
Filing Dt:
07/31/2007
Publication #:
US20090035588
Pub Dt:
02/05/2009
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
57
Patent #:
7923202
Issue Dt:
04/12/2011
Application #:
11831099
Filing Dt:
07/31/2007
Publication #:
US20090035708
Pub Dt:
02/05/2009
Title:
LAYER PATTERNING USING DOUBLE EXPOSURE PROCESSES IN A SINGLE PHOTORESIST LAYER
58
Patent #:
8032897
Issue Dt:
10/04/2011
Application #:
11831119
Filing Dt:
07/31/2007
Publication #:
US20090037936
Pub Dt:
02/05/2009
Title:
PLACING VIRTUAL MACHINE MONITOR (VMM) CODE IN GUEST CONTEXT TO SPEED MEMORY MAPPED INPUT/OUTPUT VIRTUALIZATION
59
Patent #:
8110496
Issue Dt:
02/07/2012
Application #:
11831137
Filing Dt:
07/31/2007
Publication #:
US20080020198
Pub Dt:
01/24/2008
Title:
METHOD FOR PERFORMING CHEMICAL SHRINK PROCESS OVER BARC (BOTTOM ANTI-REFLECTIVE COATING)
60
Patent #:
7994639
Issue Dt:
08/09/2011
Application #:
11831138
Filing Dt:
07/31/2007
Publication #:
US20090032978
Pub Dt:
02/05/2009
Title:
MICROELECTRONIC STRUCTURE INCLUDING DUAL DAMASCENE STRUCTURE AND HIGH CONTRAST ALIGNMENT MARK
61
Patent #:
7566653
Issue Dt:
07/28/2009
Application #:
11831149
Filing Dt:
07/31/2007
Publication #:
US20090035954
Pub Dt:
02/05/2009
Title:
INTERCONNECT STRUCTURE WITH GRAIN GROWTH PROMOTION LAYER AND METHOD FOR FORMING THE SAME
62
Patent #:
7701037
Issue Dt:
04/20/2010
Application #:
11831208
Filing Dt:
07/31/2007
Publication #:
US20090032904
Pub Dt:
02/05/2009
Title:
ORIENTATION-INDEPENDENT MULTI-LAYER BEOL CAPACITOR
63
Patent #:
7913034
Issue Dt:
03/22/2011
Application #:
11832220
Filing Dt:
08/01/2007
Publication #:
US20070294471
Pub Dt:
12/20/2007
Title:
DRAM ACCESS COMMAND QUEUING
64
Patent #:
7917870
Issue Dt:
03/29/2011
Application #:
11832453
Filing Dt:
08/01/2007
Publication #:
US20080022233
Pub Dt:
01/24/2008
Title:
ENHANCING A POWER DISTRIBUTION SYSTEM IN A CERAMIC INTEGRATED CIRCUIT PACKAGE
65
Patent #:
7902069
Issue Dt:
03/08/2011
Application #:
11833112
Filing Dt:
08/02/2007
Publication #:
US20090032951
Pub Dt:
02/05/2009
Title:
SMALL AREA, ROBUST SILICON VIA STRUCTURE AND PROCESS
66
Patent #:
7729161
Issue Dt:
06/01/2010
Application #:
11833143
Filing Dt:
08/02/2007
Publication #:
US20090034323
Pub Dt:
02/05/2009
Title:
PHASE CHANGE MEMORY WITH DUAL WORD LINES AND SOURCE LINES AND METHOD OF OPERATING SAME
67
Patent #:
8276038
Issue Dt:
09/25/2012
Application #:
11833274
Filing Dt:
08/03/2007
Publication #:
US20080055125
Pub Dt:
03/06/2008
Title:
DATA STORAGE SYSTEMS
68
Patent #:
7969770
Issue Dt:
06/28/2011
Application #:
11833321
Filing Dt:
08/03/2007
Publication #:
US20090033358
Pub Dt:
02/05/2009
Title:
PROGRAMMABLE VIA DEVICES IN BACK END OF LINE LEVEL
69
Patent #:
7659534
Issue Dt:
02/09/2010
Application #:
11833354
Filing Dt:
08/03/2007
Publication #:
US20090033360
Pub Dt:
02/05/2009
Title:
PROGRAMMABLE VIA DEVICES WITH AIR GAP ISOLATION
70
Patent #:
7932552
Issue Dt:
04/26/2011
Application #:
11833538
Filing Dt:
08/03/2007
Publication #:
US20090033395
Pub Dt:
02/05/2009
Title:
MULTIPLE SOURCE-SINGLE DRAIN FIELD EFFECT SEMICONDUCTOR DEVICE AND CIRCUIT
71
Patent #:
7941772
Issue Dt:
05/10/2011
Application #:
11834110
Filing Dt:
08/06/2007
Publication #:
US20090044054
Pub Dt:
02/12/2009
Title:
DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
72
Patent #:
7749812
Issue Dt:
07/06/2010
Application #:
11834552
Filing Dt:
08/06/2007
Publication #:
US20090039499
Pub Dt:
02/12/2009
Title:
HEAT SINK WITH THERMALLY COMPLIANT BEAMS
73
Patent #:
8735243
Issue Dt:
05/27/2014
Application #:
11834641
Filing Dt:
08/06/2007
Publication #:
US20090039447
Pub Dt:
02/12/2009
Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Title:
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Assignor
1
GLOBALFOUNDRIES INC.
Exec Dt:
11/27/2018
Assignee
1
WILMINGTON TRUST, NATIONAL ASSOCIATION
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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