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Reel/Frame:	049490/0001			Pages:	892
		Recorded:	11/29/2018
Conveyance:	SECURITY AGREEMENT

Total properties: 13706
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Patent #:	8055822	Issue Dt:	11/08/2011	Application #:	11842206	Filing Dt:	08/21/2007
Publication #:	US20090055826	Pub Dt:	02/26/2009
Title:	MULTICORE PROCESSOR HAVING STORAGE FOR CORE-SPECIFIC OPERATIONAL DATA

Patent #:	7741658	Issue Dt:	06/22/2010	Application #:	11842437	Filing Dt:	08/21/2007
Publication #:	US20090050942	Pub Dt:	02/26/2009
Title:	SELF-ALIGNED SUPER STRESSED PFET

Patent #:	7957826	Issue Dt:	06/07/2011	Application #:	11842515	Filing Dt:	08/21/2007
Publication #:	US20090053627	Pub Dt:	02/26/2009
Title:	METHODS FOR NORMALIZING ERROR IN PHOTOLITHOGRAPHIC PROCESSES

Patent #:	7360188	Issue Dt:	04/15/2008	Application #:	11842533	Filing Dt:	08/21/2007
Publication #:	US20070288872	Pub Dt:	12/13/2007
Title:	METHOD AND APPARATUS FOR CHARACTERISTIC IMPEDANCE DISCONTINUITY REDUCTION IN HIGH-SPEED FLEXIBLE CIRCUIT APPLICATIONS

Patent #:	7763515	Issue Dt:	07/27/2010	Application #:	11843358	Filing Dt:	08/22/2007
Publication #:	US20080179628	Pub Dt:	07/31/2008
Title:	TRANSISTOR WITH EMBEDDED SILICON/GERMANIUM MATERIAL ON A STRAINED SEMICONDUCTOR ON INSULATOR SUBSTRATE

Patent #:	8006032	Issue Dt:	08/23/2011	Application #:	11843434	Filing Dt:	08/22/2007
Publication #:	US20090055572	Pub Dt:	02/26/2009
Title:	OPTIMAL SOLUTION TO CONTROL DATA CHANNELS

Patent #:	8095172	Issue Dt:	01/10/2012	Application #:	11843784	Filing Dt:	08/23/2007
Title:	CONNECTIVITY MANAGER TO MANAGE CONNECTIVITY SERVICES

Patent #:	7793167	Issue Dt:	09/07/2010	Application #:	11843791	Filing Dt:	08/23/2007
Publication #:	US20090055688	Pub Dt:	02/26/2009
Title:	DETECTION AND CORRECTION OF DROPPED WRITE ERRORS IN A DATA STORAGE SYSTEM

Patent #:	7960808	Issue Dt:	06/14/2011	Application #:	11844109	Filing Dt:	08/23/2007
Publication #:	US20070290233	Pub Dt:	12/20/2007
Title:	REPROGRAMMABLE FUSE STRUCTURE AND METHOD

Patent #:	8589832	Issue Dt:	11/19/2013	Application #:	11844397	Filing Dt:	08/24/2007
Publication #:	US20090052153	Pub Dt:	02/26/2009
Title:	ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE AND METHOD OF SHIELDING

Patent #:	7964081	Issue Dt:	06/21/2011	Application #:	11844587	Filing Dt:	08/24/2007
Publication #:	US20090050486	Pub Dt:	02/26/2009
Title:	ENHANCED MAGNETIC PLATING METHOD

Patent #:	7378542	Issue Dt:	05/27/2008	Application #:	11844831	Filing Dt:	08/24/2007
Publication #:	US20080033198	Pub Dt:	02/07/2008
Title:	PRECURSORS TO FLUOROALKANOL-CONTAINING OLEFIN MONOMERS, AND ASSOCIATED METHODS OF SYNTHESIS AND USE

Patent #:	7515489	Issue Dt:	04/07/2009	Application #:	11845386	Filing Dt:	08/27/2007
Publication #:	US20090059705	Pub Dt:	03/05/2009
Title:	SRAM HAVING ACTIVE WRITE ASSIST FOR IMPROVED OPERATIONAL MARGINS

Patent #:	8032851	Issue Dt:	10/04/2011	Application #:	11845852	Filing Dt:	08/28/2007
Publication #:	US20080184186	Pub Dt:	07/31/2008
Title:	A DESIGN STRUCTURE FOR AN INTEGRATED CIRCUIT DESIGN FOR REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT

Patent #:	7446395	Issue Dt:	11/04/2008	Application #:	11845888	Filing Dt:	08/28/2007
Publication #:	US20070292696	Pub Dt:	12/20/2007
Title:	DEVICE HAVING DUAL ETCH STOP LINER AND PROTECTIVE LAYER

Patent #:	7763531	Issue Dt:	07/27/2010	Application #:	11846544	Filing Dt:	08/29/2007
Publication #:	US20070292996	Pub Dt:	12/20/2007
Title:	METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING

Patent #:	7831935	Issue Dt:	11/09/2010	Application #:	11846578	Filing Dt:	08/29/2007
Publication #:	US20080024197	Pub Dt:	01/31/2008
Title:	METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE

Patent #:	7382055	Issue Dt:	06/03/2008	Application #:	11846595	Filing Dt:	08/29/2007
Publication #:	US20070290272	Pub Dt:	12/20/2007
Title:	INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT

Patent #:	7925614	Issue Dt:	04/12/2011	Application #:	11847203	Filing Dt:	08/29/2007
Publication #:	US20070295954	Pub Dt:	12/27/2007
Title:	METHOD AND STRUCTURE TO ISOLATE A QUBIT FROM THE ENVIRONMENT

Patent #:	7851885	Issue Dt:	12/14/2010	Application #:	11847379	Filing Dt:	08/30/2007
Publication #:	US20100237460	Pub Dt:	09/23/2010
Title:	METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES

Patent #:	7465649	Issue Dt:	12/16/2008	Application #:	11847384	Filing Dt:	08/30/2007
Publication #:	US20070293031	Pub Dt:	12/20/2007
Title:	A METHOD OF FORMING A SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK

Patent #:	7853443	Issue Dt:	12/14/2010	Application #:	11847391	Filing Dt:	08/30/2007
Publication #:	US20080004854	Pub Dt:	01/03/2008
Title:	TRANSIENT SIMULATION USING ADAPTIVE PIECEWISE CONSTANT MODEL

Patent #:	7429877	Issue Dt:	09/30/2008	Application #:	11848470	Filing Dt:	08/31/2007
Publication #:	US20080186054	Pub Dt:	08/07/2008
Title:	DESIGN STRUCTURE FOR A FLEXIBLE MULTIMODE LOGIC ELEMENT FOR USE IN A CONFIGURABLE MIXED-LOGIC SIGNAL DISTRIBUTION PATH

Patent #:	7885365	Issue Dt:	02/08/2011	Application #:	11848599	Filing Dt:	08/31/2007
Publication #:	US20090060091	Pub Dt:	03/05/2009
Title:	LOW-POWER, LOW-AREA HIGH-SPEED RECEIVER ARCHITECTURE

Patent #:	7592685	Issue Dt:	09/22/2009	Application #:	11849048	Filing Dt:	08/31/2007
Publication #:	US20080038915	Pub Dt:	02/14/2008
Title:	DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES

Patent #:	7827514	Issue Dt:	11/02/2010	Application #:	11849346	Filing Dt:	09/03/2007
Publication #:	US20070300191	Pub Dt:	12/27/2007
Title:	EFFICIENT ELECTROMAGNETIC MODELING OF IRREGULAR METAL PLANES

Patent #:	7843069	Issue Dt:	11/30/2010	Application #:	11849409	Filing Dt:	09/04/2007
Publication #:	US20090057908	Pub Dt:	03/05/2009
Title:	WIRE BOND PADS

Patent #:	7984329	Issue Dt:	07/19/2011	Application #:	11849452	Filing Dt:	09/04/2007
Publication #:	US20090063896	Pub Dt:	03/05/2009
Title:	SYSTEM AND METHOD FOR PROVIDING DRAM DEVICE-LEVEL REPAIR VIA ADDRESS REMAPPINGS EXTERNAL TO THE DEVICE

Patent #:	7710137	Issue Dt:	05/04/2010	Application #:	11849702	Filing Dt:	09/04/2007
Publication #:	US20090058444	Pub Dt:	03/05/2009
Title:	METHOD AND APPARATUS FOR RELATIVE TESTING OF INTEGRATED CIRCUIT DEVICES

Patent #:	7784012	Issue Dt:	08/24/2010	Application #:	11849908	Filing Dt:	09/04/2007
Publication #:	US20080010626	Pub Dt:	01/10/2008
Title:	SYSTEM AND METHOD FOR CREATING A STANDARD CELL LIBRARY FOR USE IN CIRCUIT DESIGNS

Patent #:	7816219	Issue Dt:	10/19/2010	Application #:	11850076	Filing Dt:	09/05/2007
Publication #:	US20070298572	Pub Dt:	12/27/2007
Title:	FIELD EFFECT TRANSISTORS (FETS) WITH MULTIPLE AND/OR STAIRCASE SILICIDE

Patent #:	7825000	Issue Dt:	11/02/2010	Application #:	11850427	Filing Dt:	09/05/2007
Publication #:	US20090059656	Pub Dt:	03/05/2009
Title:	METHOD FOR INTEGRATION OF MAGNETIC RANDOM ACCESS MEMORIES WITH IMPROVED LITHOGRAPHIC ALIGNMENT TO MAGNETIC TUNNEL JUNCTIONS

Patent #:	7825469	Issue Dt:	11/02/2010	Application #:	11850488	Filing Dt:	09/05/2007
Publication #:	US20090057804	Pub Dt:	03/05/2009
Title:	THRESHOLD VOLTAGE COMPENSATION FOR PIXEL DESIGN OF CMOS IMAGE SENSORS

Patent #:	7795677	Issue Dt:	09/14/2010	Application #:	11850608	Filing Dt:	09/05/2007
Publication #:	US20090057762	Pub Dt:	03/05/2009
Title:	NANOWIRE FIELD-EFFECT TRANSISTORS

Patent #:	7534675	Issue Dt:	05/19/2009	Application #:	11850644	Filing Dt:	09/05/2007
Publication #:	US20090061568	Pub Dt:	03/05/2009
Title:	TECHNIQUES FOR FABRICATING NANOWIRE FIELD-EFFECT TRANSISTORS

Patent #:	7633079	Issue Dt:	12/15/2009	Application #:	11850742	Filing Dt:	09/06/2007
Publication #:	US20090065761	Pub Dt:	03/12/2009
Title:	PROGRAMMABLE FUSE/NON-VOLATILE MEMORY STRUCTURES IN BEOL REGIONS USING EXTERNALLY HEATED PHASE CHANGE MATERIAL

Patent #:	7464217	Issue Dt:	12/09/2008	Application #:	11850840	Filing Dt:	09/06/2007
Publication #:	US20080055956	Pub Dt:	03/06/2008
Title:	DESIGN STRUCTURE FOR CONTENT ADDRESSABLE MEMORY

Patent #:	7884018	Issue Dt:	02/08/2011	Application #:	11850916	Filing Dt:	09/06/2007
Publication #:	US20080315429	Pub Dt:	12/25/2008
Title:	METHOD FOR IMPROVING THE SELECTIVITY OF A CVD PROCESS

Patent #:	7928571	Issue Dt:	04/19/2011	Application #:	11850968	Filing Dt:	09/06/2007
Publication #:	US20070296044	Pub Dt:	12/27/2007
Title:	DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS

Patent #:	7892940	Issue Dt:	02/22/2011	Application #:	11851123	Filing Dt:	09/06/2007
Publication #:	US20080038923	Pub Dt:	02/14/2008
Title:	DEVICE AND METHODOLOGY FOR REDUCING EFFECTIVE DIELECTRIC CONSTANT IN SEMICONDUCTOR DEVICES

Patent #:	7904658	Issue Dt:	03/08/2011	Application #:	11851128	Filing Dt:	09/06/2007
Publication #:	US20080040547	Pub Dt:	02/14/2008
Title:	STRUCTURE FOR POWER-EFFICIENT CACHE MEMORY

Patent #:	7839206	Issue Dt:	11/23/2010	Application #:	11851138	Filing Dt:	09/06/2007
Publication #:	US20080169867	Pub Dt:	07/17/2008
Title:	DESIGN STRUCTURE FOR LOW VOLTAGE APPLICATIONS IN AN INTEGRATED CIRCUIT

Patent #:	7569489	Issue Dt:	08/04/2009	Application #:	11851464	Filing Dt:	09/07/2007
Publication #:	US20070298552	Pub Dt:	12/27/2007
Title:	HIGH PERFORMANCE 3D FET STRUCTURES, AND METHODS FOR FORMING THE SAME USING PREFERENTIAL CRYSTALLOGRAPHIC ETCHING

Patent #:	8053810	Issue Dt:	11/08/2011	Application #:	11851858	Filing Dt:	09/07/2007
Publication #:	US20090067463	Pub Dt:	03/12/2009
Title:	STRUCTURES HAVING LATTICE-MISMATCHED SINGLE-CRYSTALLINE SEMICONDUCTOR LAYERS ON THE SAME LITHOGRAPHIC LEVEL AND METHODS OF MANUFACTURING THE SAME

Patent #:	7713789	Issue Dt:	05/11/2010	Application #:	11852317	Filing Dt:	09/09/2007
Publication #:	US20080017978	Pub Dt:	01/24/2008
Title:	SEMICONDUCTOR DEVICE WITH A HIGH THERMAL DISSIPATION EFFICIENCY

Patent #:	7939823	Issue Dt:	05/10/2011	Application #:	11852353	Filing Dt:	09/10/2007
Publication #:	US20090065955	Pub Dt:	03/12/2009
Title:	METHOD AND STRUCTURES FOR ACCELERATED SOFT-ERROR TESTING

Patent #:	7989229	Issue Dt:	08/02/2011	Application #:	11852493	Filing Dt:	09/10/2007
Publication #:	US20090068770	Pub Dt:	03/12/2009
Title:	TACTILE SURFACE INSPECTION DURING DEVICE FABRICATION OR ASSEMBLY

Patent #:	7919379	Issue Dt:	04/05/2011	Application #:	11852906	Filing Dt:	09/10/2007
Publication #:	US20090065817	Pub Dt:	03/12/2009
Title:	DIELECTRIC SPACER REMOVAL

Patent #:	7388261	Issue Dt:	06/17/2008	Application #:	11853040	Filing Dt:	09/11/2007
Publication #:	US20070296011	Pub Dt:	12/27/2007
Title:	STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT

Patent #:	7408229	Issue Dt:	08/05/2008	Application #:	11853045	Filing Dt:	09/11/2007
Publication #:	US20070296012	Pub Dt:	12/27/2007
Title:	STRUCTURE AND METHOD FOR ACCURATE DEEP TRENCH RESISTANCE MEASUREMENT

Patent #:	7679200	Issue Dt:	03/16/2010	Application #:	11853122	Filing Dt:	09/11/2007
Publication #:	US20090065952	Pub Dt:	03/12/2009
Title:	SEMICONDUCTOR CHIP WITH CRACK STOP

Patent #:	8006221	Issue Dt:	08/23/2011	Application #:	11853170	Filing Dt:	09/11/2007
Publication #:	US20090070629	Pub Dt:	03/12/2009
Title:	SYSTEM AND METHOD FOR TESTING MULTIPLE PROCESSOR MODES FOR PROCESSOR DESIGN VERIFICATION AND VALIDATION

Patent #:	7955921	Issue Dt:	06/07/2011	Application #:	11853284	Filing Dt:	09/11/2007
Publication #:	US20090065872	Pub Dt:	03/12/2009
Title:	FULL SILICIDE GATE FOR CMOS

Patent #:	7774670	Issue Dt:	08/10/2010	Application #:	11853304	Filing Dt:	09/11/2007
Publication #:	US20090070644	Pub Dt:	03/12/2009
Title:	METHOD AND APPARATUS FOR DYNAMICALLY DETERMINING TESTER RECIPES

Patent #:	7847683	Issue Dt:	12/07/2010	Application #:	11854035	Filing Dt:	09/12/2007
Publication #:	US20090066502	Pub Dt:	03/12/2009
Title:	EMERGENCY MACHINE OFF FEATURE WITH SAFETY CONTROL INTERFACE

Patent #:	7863089	Issue Dt:	01/04/2011	Application #:	11855325	Filing Dt:	09/14/2007
Publication #:	US20080045052	Pub Dt:	02/21/2008
Title:	PLANAR ARRAY CONTACT MEMORY CARDS

Patent #:	7904286	Issue Dt:	03/08/2011	Application #:	11855345	Filing Dt:	09/14/2007
Publication #:	US20090077441	Pub Dt:	03/19/2009
Title:	METHOD AND APPARATUS FOR SCHEDULING TEST VECTORS IN A MULTIPLE CORE INTEGRATED CIRCUIT

Patent #:	7425256	Issue Dt:	09/16/2008	Application #:	11855507	Filing Dt:	09/14/2007
Publication #:	US20080000777	Pub Dt:	01/03/2008
Title:	SELECTIVE SHIELD/MATERIAL FLOW MECHANISM

Patent #:	7642125	Issue Dt:	01/05/2010	Application #:	11855979	Filing Dt:	09/14/2007
Publication #:	US20090072215	Pub Dt:	03/19/2009
Title:	PHASE CHANGE MEMORY CELL IN VIA ARRAY WITH SELF-ALIGNED, SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING

Patent #:	8178386	Issue Dt:	05/15/2012	Application #:	11855983	Filing Dt:	09/14/2007
Publication #:	US20090072216	Pub Dt:	03/19/2009
Title:	PHASE CHANGE MEMORY CELL ARRAY WITH SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING

Patent #:	7833839	Issue Dt:	11/16/2010	Application #:	11856033	Filing Dt:	09/15/2007
Title:	METHOD FOR DECREASING SURFACE DELAMINATION OF GEL-TYPE THERMAL INTERFACE MATERIAL BY MANAGEMENT OF THE MATERIAL CURE TEMPERATURE

Patent #:	7918984	Issue Dt:	04/05/2011	Application #:	11856335	Filing Dt:	09/17/2007
Publication #:	US20090071836	Pub Dt:	03/19/2009
Title:	METHOD OF ELECTRODEPOSITING GERMANIUM COMPOUND MATERIALS ON A SUBSTRATE

Patent #:	7787108	Issue Dt:	08/31/2010	Application #:	11856799	Filing Dt:	09/18/2007
Publication #:	US20080158541	Pub Dt:	07/03/2008
Title:	INLINE STRESS EVALUATION IN MICROSTRUCTURE DEVICES

Patent #:	8148255	Issue Dt:	04/03/2012	Application #:	11856831	Filing Dt:	09/18/2007
Publication #:	US20090072392	Pub Dt:	03/19/2009
Title:	TECHNIQUES FOR FORMING SOLDER BUMP INTERCONNECTS

Patent #:	7610160	Issue Dt:	10/27/2009	Application #:	11857272	Filing Dt:	09/18/2007
Publication #:	US20090076750	Pub Dt:	03/19/2009
Title:	INTEGRATED CIRCUIT TESTER INFORMATION PROCESSING SYSTEM

Patent #:	7764533	Issue Dt:	07/27/2010	Application #:	11857321	Filing Dt:	09/18/2007
Publication #:	US20090073783	Pub Dt:	03/19/2009
Title:	MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION

Patent #:	7567473	Issue Dt:	07/28/2009	Application #:	11857332	Filing Dt:	09/18/2007
Publication #:	US20090073790	Pub Dt:	03/19/2009
Title:	MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION

Patent #:	7888959	Issue Dt:	02/15/2011	Application #:	11857596	Filing Dt:	09/19/2007
Publication #:	US20090134925	Pub Dt:	05/28/2009
Title:	APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES

Patent #:	7378890	Issue Dt:	05/27/2008	Application #:	11857632	Filing Dt:	09/19/2007
Publication #:	US20080007310	Pub Dt:	01/10/2008
Title:	PROGRAMMABLE LOW-POWER HIGH-FREQUENCY DIVIDER

Patent #:	8963294	Issue Dt:	02/24/2015	Application #:	11857806	Filing Dt:	09/19/2007
Publication #:	US20080006852	Pub Dt:	01/10/2008
Title:	DENSE CHEVRON finFET AND METHOD OF MANUFACTURING SAME

Patent #:	7867895	Issue Dt:	01/11/2011	Application #:	11858166	Filing Dt:	09/20/2007
Publication #:	US20090079077	Pub Dt:	03/26/2009
Title:	METHOD OF FABRICATING IMPROVED INTERCONNECT STRUCTURE WITH A VIA GOUGING FEATURE ABSENT PROFILE DAMAGE TO THE INTERCONNECT DIELECTRIC

Patent #:	7709370	Issue Dt:	05/04/2010	Application #:	11858615	Filing Dt:	09/20/2007
Publication #:	US20090081418	Pub Dt:	03/26/2009
Title:	SPIN-ON ANTIREFLECTIVE COATING FOR INTEGRATION OF PATTERNABLE DIELECTRIC MATERIALS AND INTERCONNECT STRUCTURES

Patent #:	8084862	Issue Dt:	12/27/2011	Application #:	11858624	Filing Dt:	09/20/2007
Publication #:	US20090079075	Pub Dt:	03/26/2009
Title:	INTERCONNECT STRUCTURES WITH PATTERNABLE LOW-K DIELECTRICS AND METHOD OF FABRICATING SAME

Patent #:	8618663	Issue Dt:	12/31/2013	Application #:	11858636	Filing Dt:	09/20/2007
Publication #:	US20090079076	Pub Dt:	03/26/2009
Title:	PATTERNABLE DIELECTRIC FILM STRUCTURE WITH IMPROVED LITHOGRAPHY AND METHOD OF FABRICATING SAME

Patent #:	8341344	Issue Dt:	12/25/2012	Application #:	11859044	Filing Dt:	09/21/2007
Publication #:	US20090083741	Pub Dt:	03/26/2009
Title:	TECHNIQUES FOR ACCESSING A RESOURCE IN A PROCESSOR SYSTEM

Patent #:	7876131	Issue Dt:	01/25/2011	Application #:	11859351	Filing Dt:	09/21/2007
Publication #:	US20090302894	Pub Dt:	12/10/2009
Title:	DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC

Patent #:	8677404	Issue Dt:	03/18/2014	Application #:	11859423	Filing Dt:	09/21/2007
Publication #:	US20090083789	Pub Dt:	03/26/2009
Title:	SYSTEM AND METHOD FOR CONTROLLING VIDEO INPUTS TO A COMPUTER

Patent #:	7671413	Issue Dt:	03/02/2010	Application #:	11859865	Filing Dt:	09/24/2007
Publication #:	US20080006901	Pub Dt:	01/10/2008
Title:	SOI DEVICE WITH REDUCED JUNCTION CAPACITANCE

Patent #:	7838336	Issue Dt:	11/23/2010	Application #:	11860226	Filing Dt:	09/24/2007
Publication #:	US20090079060	Pub Dt:	03/26/2009
Title:	METHOD AND STRUCTURE FOR DISPENSING CHIP UNDERFILL THROUGH AN OPENING IN THE CHIP

Patent #:	7892956	Issue Dt:	02/22/2011	Application #:	11860459	Filing Dt:	09/24/2007
Publication #:	US20110012085	Pub Dt:	01/20/2011
Title:	METHODS OF MANUFACTURE OF VERTICAL NANOWIRE FET DEVICES

Patent #:	7763965	Issue Dt:	07/27/2010	Application #:	11860613	Filing Dt:	09/25/2007
Publication #:	US20090079071	Pub Dt:	03/26/2009
Title:	STRESS RELIEF STRUCTURES FOR SILICON INTERPOSERS

Patent #:	8115254	Issue Dt:	02/14/2012	Application #:	11860851	Filing Dt:	09/25/2007
Publication #:	US20090079026	Pub Dt:	03/26/2009
Title:	SEMICONDUCTOR-ON-INSULATOR STRUCTURES INCLUDING A TRENCH CONTAINING AN INSULATOR STRESSOR PLUG AND METHOD OF FABRICATING SAME

Patent #:	7638837	Issue Dt:	12/29/2009	Application #:	11861051	Filing Dt:	09/25/2007
Publication #:	US20090078991	Pub Dt:	03/26/2009
Title:	STRESS ENHANCED SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME

Patent #:	7761838	Issue Dt:	07/20/2010	Application #:	11861492	Filing Dt:	09/26/2007
Publication #:	US20090081837	Pub Dt:	03/26/2009
Title:	METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EXTENDED STRESS LINER

Patent #:	8003488	Issue Dt:	08/23/2011	Application #:	11861614	Filing Dt:	09/26/2007
Publication #:	US20090079027	Pub Dt:	03/26/2009
Title:	SHALLOW TRENCH ISOLATION STRUCTURE COMPATIBLE WITH SOI EMBEDDED DRAM

Patent #:	8134208	Issue Dt:	03/13/2012	Application #:	11861928	Filing Dt:	09/26/2007
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Title:	SEMICONDUCTOR DEVICE HAVING DECREASED CONTACT RESISTANCE

Patent #:	7955988	Issue Dt:	06/07/2011	Application #:	11862255	Filing Dt:	09/27/2007
Publication #:	US20080020586	Pub Dt:	01/24/2008
Title:	PHOTORESIST TRIMMING PROCESS

Patent #:	7700377	Issue Dt:	04/20/2010	Application #:	11862345	Filing Dt:	09/27/2007
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Title:	METHOD FOR REDUCING ETCH-INDUCED PROCESS UNIFORMITIES BY OMITTING DEPOSITION OF AN ENDPOINT DETECTION LAYER DURING PATTERNING OF STRESSED OVERLAYERS IN A SEMICONDUCTOR DEVICE

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Title:	SLIP RING POSITIVE Z FORCE LIQUID ISOLATION FIXTURE PERMITTING ZERO NET FORCE ON WORKPIECE

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Title:	STRUCTURES AND METHODS FOR REDUCTION OF PARASITIC CAPACITANCES IN SEMICONDUCTOR INTEGRATED CIRCUITS

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Title:	HIGH MOBILITY CMOS CIRCUITS

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Title:	LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES

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Title:	LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES

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Title:	LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES

100

Patent #:	7354277	Issue Dt:	04/08/2008	Application #:	11865293	Filing Dt:	10/01/2007
Publication #:	US20080020600	Pub Dt:	01/24/2008
Title:	LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

11/27/2018

Assignee

WILMINGTON TRUST, NATIONAL ASSOCIATION

1100 NORTH MARKET STREET

WILMINGTON, DELAWARE 19801

Correspondence name and address
	CT CORPORATION
	4400 EASTON COMMONS WAY
	SUITE 125
	COLUMBUS, OH 43219

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