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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
1
Patent #:
Issue Dt:
06/28/2011
Application #:
12103301
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
10/15/2009
Title:
COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS
2
Patent #:
Issue Dt:
05/31/2011
Application #:
12103538
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
08/14/2008
Title:
SYSTEM AND PROGRAM PRODUCT FOR SEQUENTIAL COORDINATION OF EXTERNAL DATABASE APPLICATION EVENTS WITH ASYNCHRONOUS INTERNAL DATABASE EVENTS
3
Patent #:
Issue Dt:
07/12/2011
Application #:
12103548
Filing Dt:
04/15/2008
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD, SYSTEM, AND PROGRAM PRODUCT FOR SEQUENTIAL COORDINATION OF EXTERNAL DATABASE APPLICATION EVENTS WITH ASYNCHRONOUS INTERNAL DATABASE EVENTS
4
Patent #:
Issue Dt:
06/12/2012
Application #:
12103765
Filing Dt:
04/16/2008
Publication #:
Pub Dt:
04/30/2009
Title:
SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS
5
Patent #:
Issue Dt:
06/02/2009
Application #:
12103775
Filing Dt:
04/16/2008
Publication #:
Pub Dt:
05/14/2009
Title:
METHOD FOR TRACKING CONTAINERS USING A LOW-RATE WIRELESS PERSONAL AREA NETWORK SYSTEM
6
Patent #:
Issue Dt:
08/09/2011
Application #:
12104461
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENERATOR (CWG), DESIGN STRUCTURE AND METHOD
7
Patent #:
Issue Dt:
06/21/2011
Application #:
12104475
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
TRANSISTORS HAVING ASYMMETRIC STRAINED SOURCE/DRAIN PORTIONS
8
Patent #:
Issue Dt:
07/19/2011
Application #:
12104513
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
TRANSISTORS HAVING ASYMMETRIC STRAINED SOURCE/DRAIN PORTIONS
9
Patent #:
Issue Dt:
02/14/2012
Application #:
12104643
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE
10
Patent #:
Issue Dt:
05/17/2011
Application #:
12104683
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
FULLY-DEPLETED LOW-BODY DOPING FIELD EFFECT TRANSISTOR (FET) WITH REVERSE SHORT CHANNEL EFFECTS (SCE) INDUCED BY SELF-ALIGNED EDGE BACK-GATE(S)
11
Patent #:
Issue Dt:
07/19/2011
Application #:
12105217
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
10/22/2009
Title:
METHOD, APPARATUS AND SYSTEM FOR REDUCING POWER CONSUMPTION INVOLVING DATA STORAGE DEVICES
12
Patent #:
Issue Dt:
09/20/2011
Application #:
12105311
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
10/22/2009
Title:
TEST METHOD FOR DETERMINING RETICLE TRANSMISSION STABILITY
13
Patent #:
Issue Dt:
05/24/2011
Application #:
12105349
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
10/22/2009
Title:
SYSTEM AND METHODS TO EXTEND THE SERVICE LIFE OF PORTABLE DEVICES
14
Patent #:
Issue Dt:
07/19/2011
Application #:
12105366
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
PROGRAMMING OF LASER FUSE
15
Patent #:
Issue Dt:
06/21/2011
Application #:
12105449
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
INTEGRATED CIRCUIT DESIGN STRUCTURE FOR AN ASYCHRONOUS DATA INTERFACE
16
Patent #:
Issue Dt:
04/17/2012
Application #:
12105494
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
APPARATUS FOR PROVIDING UNIAXIAL LOAD DISTRIBUTION FOR LAMINATE LAYERS OF MULTILAYER CERAMIC CHIP CARRIERS
17
Patent #:
Issue Dt:
11/23/2010
Application #:
12105600
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
APPARATUS FOR PROVIDING UNIAXIAL LOAD DISTRIBUTION FOR LAMINATE LAYERS OF MULTILAYER CERAMIC CHIP CARRIERS
18
Patent #:
Issue Dt:
05/24/2011
Application #:
12105622
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD FOR PROVIDING UNIAXIAL LOAD DISTRIBUTION FOR LAMINATE LAYERS OF MULTILAYER CERAMIC CHIP CARRIERS
19
Patent #:
Issue Dt:
09/27/2011
Application #:
12106053
Filing Dt:
04/18/2008
Publication #:
Pub Dt:
11/27/2008
Title:
PROGRAM PRODUCT PROVIDING A CONFIGURATION SPECIFICATION LANGUAGE HAVING CLONE LATCH SUPPORT
20
Patent #:
Issue Dt:
02/08/2011
Application #:
12106361
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
08/07/2008
Title:
HDL DESIGN STRUCTURE FOR INTEGRATING TEST STRUCTURES INTO AN INTEGRATED CIRCUIT DESIGN
21
Patent #:
Issue Dt:
11/23/2010
Application #:
12106462
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
12/31/2009
Title:
A METHOD OF OPERATIVELY COMBINING A PLURALITY OF COMPONENTS TO FORM A LAND GRIP ARRAY INTERPOSER (LGA) STRUCTURE UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES
22
Patent #:
Issue Dt:
02/21/2012
Application #:
12106531
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
08/14/2008
Title:
INTEGRATED CIRCUIT TRANSFORMER DEVICES FOR ON-CHIP MILLIMETER-WAVE APPLICATIONS
23
Patent #:
Issue Dt:
02/01/2011
Application #:
12106539
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
07/30/2009
Title:
CROSS POINT SWITCH USING PHASE CHANGE MATERIAL
24
Patent #:
Issue Dt:
03/08/2011
Application #:
12106557
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
10/22/2009
Title:
METAL-GATE THERMOCOUPLE
25
Patent #:
Issue Dt:
06/16/2015
Application #:
12106586
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
10/23/2008
Title:
Methods and structures for protecting one area while processing another area on a chip
26
Patent #:
Issue Dt:
02/07/2012
Application #:
12106983
Filing Dt:
04/21/2008
Publication #:
Pub Dt:
09/11/2008
Title:
ELECTRONIC COMPONENT AND TAPE HEAD HAVING A CLOSURE
27
Patent #:
Issue Dt:
01/04/2011
Application #:
12107158
Filing Dt:
04/22/2008
Publication #:
Pub Dt:
08/14/2008
Title:
METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION
28
Patent #:
Issue Dt:
08/02/2011
Application #:
12107303
Filing Dt:
04/22/2008
Publication #:
Pub Dt:
08/14/2008
Title:
PREVENTION OF BACKSIDE CRACKS IN SEMICONDUCTOR CHIPS OR WAFERS USING BACKSIDE FILM OR BACKSIDE WET ETCH
29
Patent #:
Issue Dt:
09/07/2010
Application #:
12107573
Filing Dt:
04/22/2008
Publication #:
Pub Dt:
10/22/2009
Title:
MEMORY CELL HAVING A BURIED PHASE CHANGE REGION AND METHOD FOR FABRICATING THE SAME
30
Patent #:
Issue Dt:
12/13/2011
Application #:
12107825
Filing Dt:
04/23/2008
Publication #:
Pub Dt:
10/29/2009
Title:
METHODS FOR ENHANCING QUALITY OF PIXEL SENSOR IMAGE FRAMES FOR GLOBAL SHUTTER IMAGING
31
Patent #:
Issue Dt:
12/07/2010
Application #:
12107940
Filing Dt:
04/23/2008
Publication #:
Pub Dt:
11/20/2008
Title:
FORMALLY DERIVING A MINIMAL CLOCK-GATING SCHEME
32
Patent #:
Issue Dt:
11/16/2010
Application #:
12107980
Filing Dt:
04/23/2008
Publication #:
Pub Dt:
10/29/2009
Title:
CMP METHODS AVOIDING EDGE EROSION AND RELATED WAFER
33
Patent #:
Issue Dt:
04/10/2012
Application #:
12107992
Filing Dt:
04/23/2008
Publication #:
Pub Dt:
09/11/2008
Title:
SELF-ALIGNED METAL TO FORM CONTACTS TO GE CONTAINING SUBSTRATES AND STRUCTURE FORMED THEREBY
34
Patent #:
Issue Dt:
01/18/2011
Application #:
12108119
Filing Dt:
04/23/2008
Publication #:
Pub Dt:
10/29/2009
Title:
NON-PLASMA CAPPING LAYER FOR INTERCONNECT APPLICATIONS
35
Patent #:
Issue Dt:
09/06/2011
Application #:
12108165
Filing Dt:
04/23/2008
Publication #:
Pub Dt:
06/18/2009
Title:
DESIGN STRUCTURES FOR ELECTROSTATIC DISCHARGE PROTECTION FOR BIPOLAR SEMICONDUCTOR CIRCUITRY
36
Patent #:
Issue Dt:
04/07/2009
Application #:
12108512
Filing Dt:
04/24/2008
Title:
CHIP-TO-WAFER INTEGRATION TECHNOLOGY FOR THREE-DIMENSIONAL CHIP STACKING
37
Patent #:
Issue Dt:
10/26/2010
Application #:
12108629
Filing Dt:
04/24/2008
Publication #:
Pub Dt:
08/21/2008
Title:
METHOD OF GENERATING WIRING ROUTES WITH MATCHING DELAY IN THE PRESENCE OF PROCESS VARIATION
38
Patent #:
Issue Dt:
07/12/2011
Application #:
12108992
Filing Dt:
04/24/2008
Publication #:
Pub Dt:
04/30/2009
Title:
DOPANT PROFILE TUNING FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION
39
Patent #:
Issue Dt:
04/26/2011
Application #:
12109025
Filing Dt:
04/24/2008
Publication #:
Pub Dt:
10/29/2009
Title:
SOURCE/DRAIN JUNCTION FOR HIGH PERFORMANCE MOSFET FORMED BY SELECTIVE EPI PROCESS
40
Patent #:
Issue Dt:
03/08/2011
Application #:
12109379
Filing Dt:
04/25/2008
Publication #:
Pub Dt:
10/29/2009
Title:
DESIGN STRUCTURE FOR ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH, METHOD OF ESTIMATING AND/OR PREDICTING POWER CYCLE LENGTH AND CIRCUIT THEREOF
41
Patent #:
Issue Dt:
12/28/2010
Application #:
12110375
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
06/04/2009
Title:
DESIGN STRUCTURE FOR IMPLEMENTING MATRIX-BASED SEARCH CAPABILITY IN CONTENT ADDRESSABLE MEMORY DEVICES
42
Patent #:
Issue Dt:
02/14/2012
Application #:
12110456
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
06/04/2009
Title:
STRUCTURE FOR IMPLEMENTING MEMORY ARRAY DEVICE WITH BUILT IN COMPUTATION CAPABILITY
43
Patent #:
Issue Dt:
01/25/2011
Application #:
12110465
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
09/25/2008
Title:
METHOD AND STRUCTURE FOR SELF-ALIGNED DEVICE CONTACTS
44
Patent #:
Issue Dt:
08/30/2011
Application #:
12110579
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
10/29/2009
Title:
BRIDGES FOR INTERCONNECTING INTERPOSERS IN MULTI-CHIP INTEGRATED CIRCUITS
45
Patent #:
Issue Dt:
10/19/2010
Application #:
12110633
Filing Dt:
06/20/2008
Publication #:
Pub Dt:
10/09/2008
Title:
SEMICONDUCTOR STRUCTURE INCLUDING LAMINATED ISOLATION REGION
46
Patent #:
Issue Dt:
09/27/2011
Application #:
12110639
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
10/29/2009
Title:
METHODS AND APPARATUS FOR DETERMINING A SWITCHING HISTORY TIME CONSTANT IN AN INTEGRATED CIRCUIT DEVICE
47
Patent #:
Issue Dt:
06/19/2012
Application #:
12110644
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
09/25/2008
Title:
RECTIFYING ELEMENT FOR A CROSSPOINT BASED MEMORY ARRAY ARCHITECTURE
48
Patent #:
Issue Dt:
07/13/2010
Application #:
12110698
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
11/13/2008
Title:
APPARATUS FOR THREE-DIMENSIONAL MEASUREMENTS OF PHYSICAL CHARACTERISTICS WITHIN A DATA CENTER
49
Patent #:
Issue Dt:
06/15/2010
Application #:
12110732
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
10/02/2008
Title:
METHOD AND APPARATUS FOR THREE-DIMENSIONAL MEASUREMENTS OF PHYSICAL CHARACTERISTICS WITHIN A DATA CENTER
50
Patent #:
Issue Dt:
09/27/2011
Application #:
12110765
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
09/04/2008
Title:
STRUCTURE FOR DATA BUS BANDWIDTH SCHEDULING IN AN FBDIMM MEMORY SYSTEM OPERATING IN VARIABLE LATENCY MODE
51
Patent #:
Issue Dt:
11/16/2010
Application #:
12110851
Filing Dt:
04/28/2008
Publication #:
Pub Dt:
10/29/2009
Title:
METHOD FOR MONITORING DEPENDENT METRIC STREAMS FOR ANOMALIES
52
Patent #:
Issue Dt:
01/25/2011
Application #:
12111529
Filing Dt:
04/29/2008
Publication #:
Pub Dt:
08/21/2008
Title:
COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE
53
Patent #:
Issue Dt:
04/19/2011
Application #:
12111609
Filing Dt:
04/29/2008
Publication #:
Pub Dt:
08/21/2008
Title:
STRUCTURE FOR INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIMES FOR A LATCH ELEMENT
54
Patent #:
Issue Dt:
06/07/2011
Application #:
12112329
Filing Dt:
04/30/2008
Publication #:
Pub Dt:
11/05/2009
Title:
STITCHED CIRCUITRY REGION BOUNDARY INDENTIFICATION FOR STITCHED IC CHIP LAYOUT
55
Patent #:
Issue Dt:
08/23/2011
Application #:
12112336
Filing Dt:
04/30/2008
Publication #:
Pub Dt:
11/05/2009
Title:
IC CHIP AND DESIGN STRUCTURE INCLUDING STITCHED CIRCUITRY REGION BOUNDARY IDENTIFICATION
56
Patent #:
Issue Dt:
05/31/2011
Application #:
12112391
Filing Dt:
04/30/2008
Publication #:
Pub Dt:
11/05/2009
Title:
SYSTEM FOR PROVIDING ON-DIE TERMINATION OF A CONTROL SIGNAL BUS
57
Patent #:
Issue Dt:
02/09/2010
Application #:
12112454
Filing Dt:
04/30/2008
Publication #:
Pub Dt:
11/05/2009
Title:
METHOD AND APPARATUS FOR IMPLEMENTING SELF-REFERENCING READ OPERATION FOR PCRAM DEVICES
58
Patent #:
Issue Dt:
09/07/2010
Application #:
12112611
Filing Dt:
04/30/2008
Publication #:
Pub Dt:
08/28/2008
Title:
TRANSLATION DATA PREFETCH IN AN IOMMU
59
Patent #:
Issue Dt:
12/03/2013
Application #:
12113064
Filing Dt:
04/30/2008
Publication #:
Pub Dt:
11/05/2009
Title:
PENTACENE-CARBON NANOTUBE COMPOSITE, METHOD OF FORMING THE COMPOSITE, AND SEMICONDUCTOR DEVICE INCLUDING THE COMPOSITE
60
Patent #:
Issue Dt:
08/19/2014
Application #:
12113230
Filing Dt:
05/01/2008
Publication #:
Pub Dt:
11/05/2009
Title:
PAD CUSHION STRUCTURE AND METHOD OF FABRICATION FOR PB-FREE C4 INTEGRATED CIRCUIT CHIP JOINING
61
Patent #:
Issue Dt:
11/30/2010
Application #:
12113288
Filing Dt:
05/01/2008
Publication #:
Pub Dt:
11/05/2009
Title:
METHODS OF OPTIMIZING TIMING OF SIGNALS IN AN INTEGRATED CIRCUIT DESIGN USING PROXY SLACK VALUES
62
Patent #:
Issue Dt:
02/22/2011
Application #:
12113374
Filing Dt:
05/01/2008
Publication #:
Pub Dt:
11/05/2009
Title:
TEST PATTERN BASED PROCESS MODEL CALIBRATION
63
Patent #:
Issue Dt:
06/28/2011
Application #:
12113457
Filing Dt:
05/01/2008
Publication #:
Pub Dt:
09/04/2008
Title:
METHOD FOR FACILITATING ACCESS TO ELECTRONIC COMPONENTS
64
Patent #:
Issue Dt:
01/04/2011
Application #:
12113462
Filing Dt:
05/01/2008
Publication #:
Pub Dt:
11/05/2009
Title:
HIGH PERFORMANCE SCHOTTKY-BARRIER-SOURCE ASYMMETRIC MOSFETS
65
Patent #:
Issue Dt:
07/31/2012
Application #:
12113510
Filing Dt:
05/01/2008
Publication #:
Pub Dt:
11/05/2009
Title:
TRANSISTOR WITH HIGH-K DIELECTRIC SIDEWALL SPACER
66
Patent #:
Issue Dt:
02/15/2011
Application #:
12113559
Filing Dt:
05/01/2008
Publication #:
Pub Dt:
11/05/2009
Title:
METHOD OF DETECTING REPEATING DEFECTS IN LITHOGRAPHY MASKS ON THE BASIS OF TEST SUBSTRATES EXPOSED UNDER VARYING CONDITIONS
67
Patent #:
Issue Dt:
08/30/2011
Application #:
12113663
Filing Dt:
05/01/2008
Publication #:
Pub Dt:
11/05/2009
Title:
COMPUTATIONAL DEVICE POWER-SAVINGS
68
Patent #:
Issue Dt:
09/27/2011
Application #:
12114070
Filing Dt:
05/02/2008
Publication #:
Pub Dt:
06/18/2009
Title:
STRUCTURE FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM
69
Patent #:
Issue Dt:
07/21/2009
Application #:
12114145
Filing Dt:
05/02/2008
Publication #:
Pub Dt:
09/25/2008
Title:
CHIP AND WAFER INTEGRATION PROCESS USING VERTICAL CONNECTIONS
70
Patent #:
Issue Dt:
09/06/2011
Application #:
12114203
Filing Dt:
05/02/2008
Publication #:
Pub Dt:
08/21/2008
Title:
SYSTEM AND METHOD FOR ACCOMMODATING NON-GAUSSIAN AND NON-LINEAR SOURCES OF VARIATION IN STATISTICAL STATIC TIMING ANALYSIS
71
Patent #:
Issue Dt:
10/06/2009
Application #:
12114636
Filing Dt:
05/02/2008
Publication #:
Pub Dt:
10/02/2008
Title:
METHOD OF FABRICATING A MAGNETIC SHIFT REGISTER
72
Patent #:
Issue Dt:
01/18/2011
Application #:
12114853
Filing Dt:
05/05/2008
Publication #:
Pub Dt:
08/28/2008
Title:
PROGRAMMABLE VOLTAGE DIVIDER
73
Patent #:
Issue Dt:
11/09/2010
Application #:
12114857
Filing Dt:
05/05/2008
Publication #:
Pub Dt:
08/28/2008
Title:
DEMULTIPLEXERS USING TRANSISTORS FOR ACCESSING MEMORY CELL ARRAYS
74
Patent #:
Issue Dt:
09/13/2011
Application #:
12115056
Filing Dt:
05/05/2008
Publication #:
Pub Dt:
11/05/2009
Title:
OPTICALLY TRANSPARENT WIRES FOR SECURE CIRCUITS AND METHODS OF MAKING SAME
75
Patent #:
Issue Dt:
11/16/2010
Application #:
12115065
Filing Dt:
05/05/2008
Publication #:
Pub Dt:
08/28/2008
Title:
HYBRID ORIENTATION SOI SUBSTRATES, AND METHOD FOR FORMING THE SAME
76
Patent #:
Issue Dt:
02/15/2011
Application #:
12115166
Filing Dt:
05/05/2008
Publication #:
Pub Dt:
12/31/2009
Title:
SYSTEMS FOR STRUCTURAL CLUSTERING OF TIME SEQUENCES
77
Patent #:
Issue Dt:
11/01/2011
Application #:
12115355
Filing Dt:
05/05/2008
Publication #:
Pub Dt:
11/05/2009
Title:
TRANSIENT TRANSACTIONAL CACHE
78
Patent #:
Issue Dt:
06/08/2010
Application #:
12115473
Filing Dt:
05/05/2008
Publication #:
Pub Dt:
09/04/2008
Title:
SHALLOW TRENCH ISOLATION PROCESS AND STRUCTURE WITH MINIMIZED STRAINED SILICON CONSUMPTION
79
Patent #:
Issue Dt:
08/23/2011
Application #:
12115618
Filing Dt:
05/06/2008
Publication #:
Pub Dt:
11/12/2009
Title:
METHOD AND APPARATUS OF WATER COOLING SEVERAL PARALLEL CIRCUIT CARDS EACH CONTAINING SEVERAL CHIP PACKAGES
80
Patent #:
Issue Dt:
12/21/2010
Application #:
12115699
Filing Dt:
05/06/2008
Publication #:
Pub Dt:
11/12/2009
Title:
CONDUCTIVE LINER AT AN INTERFACE BETWEEN A SHALLOW TRENCH ISOLATION STRUCTURE AND A BURIED OXIDE LAYER
81
Patent #:
Issue Dt:
05/17/2011
Application #:
12115731
Filing Dt:
05/06/2008
Publication #:
Pub Dt:
08/28/2008
Title:
ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> SI UNDER BIAXIAL COMPRESSIVE STRAIN
82
Patent #:
Issue Dt:
03/20/2012
Application #:
12115817
Filing Dt:
05/06/2008
Publication #:
Pub Dt:
11/12/2009
Title:
REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY
83
Patent #:
Issue Dt:
11/08/2011
Application #:
12116151
Filing Dt:
05/06/2008
Publication #:
Pub Dt:
08/28/2008
Title:
CLOCK AND DATA RECOVERY SYSTEM AND METHOD FOR CLOCK AND DATA RECOVERY BASED ON A FORWARD ERROR CORRECTION
84
Patent #:
Issue Dt:
06/05/2012
Application #:
12116317
Filing Dt:
05/07/2008
Publication #:
Pub Dt:
10/02/2008
Title:
METHOD OF FORMING A LAND GRID ARRAY (LGA) INTERPOSER
85
Patent #:
Issue Dt:
05/15/2012
Application #:
12116470
Filing Dt:
05/07/2008
Publication #:
Pub Dt:
11/12/2009
Title:
AN ELECTRICAL CONTACT STRUCTURE HAVING MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER.
86
Patent #:
Issue Dt:
06/23/2009
Application #:
12116626
Filing Dt:
05/07/2008
Title:
METHODS INVOLVING SILICON-ON-INSULATOR TRENCH MEMORY WITH IMPLANTED PLATE
87
Patent #:
Issue Dt:
10/18/2011
Application #:
12116655
Filing Dt:
05/07/2008
Publication #:
Pub Dt:
12/11/2008
Title:
METHOD OF FORMING A FLIP-CHIP PACKAGE
88
Patent #:
Issue Dt:
07/26/2011
Application #:
12116771
Filing Dt:
05/07/2008
Publication #:
Pub Dt:
08/28/2008
Title:
METHOD FOR ACHIEVING VERY HIGH BANDWIDTH BETWEEN THE LEVELS OF A CACHE HIERARCHY IN 3-DIMENSIONAL STRUCTURES, AND A 3-DIMENSIONAL STRUCTURE RESULTING THEREFROM
89
Patent #:
Issue Dt:
03/02/2010
Application #:
12117098
Filing Dt:
05/08/2008
Publication #:
Pub Dt:
10/02/2008
Title:
SERIAL LINK OUTPUT STAGE DIFFERENTIAL AMPLIFIER AND METHOD
90
Patent #:
Issue Dt:
02/01/2011
Application #:
12117784
Filing Dt:
05/09/2008
Publication #:
Pub Dt:
11/12/2009
Title:
CIRCUIT AND METHOD USING DISTRIBUTED PHASE CHANGE ELEMENTS FOR ACROSS-CHIP TEMPERATURE PROFILING
91
Patent #:
Issue Dt:
02/08/2011
Application #:
12117803
Filing Dt:
05/09/2008
Publication #:
Pub Dt:
08/28/2008
Title:
INTERCONNECTING (MAPPING) A TWO-DIMENSIONAL OPTOELECTRONIC (OE) DEVICE ARRAY TO A ONE-DIMENSIONAL WAVEGUIDE ARRAY
92
Patent #:
Issue Dt:
01/11/2011
Application #:
12117841
Filing Dt:
05/09/2008
Publication #:
Pub Dt:
09/04/2008
Title:
SYSTEM FOR USING PARTITIONED MASKS TO BUILD A CHIP
93
Patent #:
Issue Dt:
03/17/2009
Application #:
12118441
Filing Dt:
05/09/2008
Title:
SYSTEMS INVOLVING SPIN-TRANSFER MAGNETIC RANDOM ACCESS MEMORY
94
Patent #:
Issue Dt:
02/17/2009
Application #:
12118496
Filing Dt:
05/09/2008
Title:
METHODS INVOLVING RESETTING SPIN-TORQUE MAGNETIC RANDOM ACCESS MEMORY
95
Patent #:
Issue Dt:
06/22/2010
Application #:
12118776
Filing Dt:
05/12/2008
Publication #:
Pub Dt:
10/09/2008
Title:
POLYCRYSTALLINE SIGE JUNCTIONS FOR ADVANCED DEVICES
96
Patent #:
Issue Dt:
02/23/2010
Application #:
12118818
Filing Dt:
05/12/2008
Publication #:
Pub Dt:
09/04/2008
Title:
METHOD AND APPARATUS FOR FILTERING MEMORY WRITE SNOOP ACTIVITY IN A DISTRIBUTED SHARED MEMORY COMPUTER
97
Patent #:
Issue Dt:
10/26/2010
Application #:
12118875
Filing Dt:
05/12/2008
Publication #:
Pub Dt:
10/16/2008
Title:
STRUCTURE FOR LOW CAPACITANCE ESD ROBUST DIODES
98
Patent #:
Issue Dt:
05/22/2012
Application #:
12119042
Filing Dt:
05/12/2008
Publication #:
Pub Dt:
02/05/2009
Title:
METHOD AND SYSTEM FOR SCHEDULING A STREAM OF PRODUCTS IN A MANUFACTURING ENVIRONMENT BY USING PROCESS-SPECIFIC WIP LIMITS
99
Patent #:
Issue Dt:
12/15/2009
Application #:
12119384
Filing Dt:
05/12/2008
Publication #:
Pub Dt:
11/12/2009
Title:
METHOD OF FORMING STEPPED RECESSES FOR EMBEDDED STRAIN ELEMENTS IN A SEMICONDUCTOR DEVICE
100
Patent #:
Issue Dt:
04/17/2012
Application #:
12119526
Filing Dt:
05/13/2008
Publication #:
Pub Dt:
11/19/2009
Title:
METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR
Assignor
1
Exec Dt:
11/27/2018
Assignee
1
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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