|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12348391
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SOI CMOS CIRCUITS WITH SUBSTRATE BIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12348404
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/2010
|
Application #:
|
12348707
|
Filing Dt:
|
01/05/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING HIGH-Q WAFER BACK-SIDE CAPACITORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2009
|
Application #:
|
12348779
|
Filing Dt:
|
01/05/2009
|
Title:
|
UNIDIRECTIONAL RACETRACK MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12348934
|
Filing Dt:
|
01/06/2009
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
Title:
|
TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/2011
|
Application #:
|
12349018
|
Filing Dt:
|
01/06/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12349094
|
Filing Dt:
|
01/06/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
OPC MODEL CALIBRATION PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2011
|
Application #:
|
12349877
|
Filing Dt:
|
01/07/2009
|
Publication #:
|
|
Pub Dt:
|
04/30/2009
| | | | |
Title:
|
EXECUTING AN OVERALL QUANTITY OF DATA PROCESSING WITHIN AN OVERALL PROCESSING PERIOD
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
12350250
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
SUBSTRATE PLANARIZATION WITH IMPRINT MATERIALS AND PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12350251
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
METHODOLOGY OF PLACING PRINTING ASSIST FEATURE FOR RANDOM MASK LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/12/2011
|
Application #:
|
12350306
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/08/2010
| | | | |
Title:
|
TEST AND BRING-UP OF AN ENHANCED CASCADE INTERCONNECT MEMORY SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/2010
|
Application #:
|
12350312
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
DESIGN STRUCTURE FOR A HIGH-SPEED LEVEL SHIFTER
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12350329
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
LOGIC ELEMENT, AND INTEGRATED CIRCUIT OR FIELD PROGRAMMABLE GATE ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2013
|
Application #:
|
12350469
|
Filing Dt:
|
01/08/2009
|
Publication #:
|
|
Pub Dt:
|
07/09/2009
| | | | |
Title:
|
PROGRAMMABLE ELEMENT, AND MEMORY DEVICE OR LOGIC CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12350991
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
PHOTO DETECTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12351010
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
05/07/2009
| | | | |
Title:
|
AUTOMATED DYNAMIC METROLOGY SAMPLING SYSTEM AND METHOD FOR PROCESS CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12351201
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
07/16/2009
| | | | |
Title:
|
SIMULATING AN OPERATION OF A DIGITAL CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12351263
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
12351738
|
Filing Dt:
|
01/09/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
ECC INTERLEAVING FOR MULTI-TRACK RECORDING ON MAGNETIC TAPE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12351872
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
MEMORY ELEMENTS AND METHODS OF USING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12352051
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
METHOD FOR REDUCING TIP-TO-TIP SPACING BETWEEN LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/2010
|
Application #:
|
12352504
|
Filing Dt:
|
01/12/2009
|
Publication #:
|
|
Pub Dt:
|
06/11/2009
| | | | |
Title:
|
STRUCTURES AND METHODS FOR MANUFACTURING OF DISLOCATION FREE STRESSED CHANNELS IN BULK SILICON AND SOI MOS DEVICES BY GATE STRESS ENGINEERING WITH SIGE AND/OR SI:C
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2012
|
Application #:
|
12352718
|
Filing Dt:
|
01/13/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
HIGH-YIELD METHOD OF EXPOSING AND CONTACTING THROUGH-SILICON VIAS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/04/2011
|
Application #:
|
12353219
|
Filing Dt:
|
01/13/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
POLYSILICON PLUG BIPOLAR TRANSISTOR FOR PHASE CHANGE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/11/2014
|
Application #:
|
12353329
|
Filing Dt:
|
01/14/2009
|
Publication #:
|
|
Pub Dt:
|
07/15/2010
| | | | |
Title:
|
ENABLING ACCESS TO A SUBSET OF DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
05/25/2010
|
Application #:
|
12354088
|
Filing Dt:
|
01/15/2009
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
DAMASCENE GATE FIELD EFFECT TRANSISTOR WITH AN INTERNAL SPACER STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12354958
|
Filing Dt:
|
01/16/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
THREE DIMENSIONAL CHIP FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12354996
|
Filing Dt:
|
01/16/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
EFUSE WITH PARTIAL SIGE LAYER AND DESIGN STRUCTURE THEREFOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2013
|
Application #:
|
12355112
|
Filing Dt:
|
01/16/2009
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
12355189
|
Filing Dt:
|
01/16/2009
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
SOLUTION-BASED DEPOSITION PROCESS FOR METAL CHALCOGENIDES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12355250
|
Filing Dt:
|
01/16/2009
|
Publication #:
|
|
Pub Dt:
|
10/01/2009
| | | | |
Title:
|
METHOD FOR ENCAPSULATING A HIGH-K GATE STACK BY FORMING A LINER AT TWO DIFFERENT PROCESS TEMPERATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12355495
|
Filing Dt:
|
01/16/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
MOTOR CONTROL MECHANISM FOR ELECTRIC VEHICLES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12355547
|
Filing Dt:
|
01/16/2009
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
Title:
|
GILBERT MIXERS WITH IMPROVED ISOLATION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12355757
|
Filing Dt:
|
01/16/2009
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
METHODS AND APPARATUS FOR BOOLEAN EQUIVALENCY CHECKING IN THE PRESENCE OF VOTING LOGIC
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12355814
|
Filing Dt:
|
01/19/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
SHORT PATH CUSTOMIZED MASK CORRECTION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2012
|
Application #:
|
12355815
|
Filing Dt:
|
01/19/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
METHOD OF OPERATING TRANSISTORS AND STRUCTURES THEREOF FOR IMPROVED RELIABILITY AND LIFETIME
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
12355889
|
Filing Dt:
|
01/19/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
SIGNAL AND POWER SUPPLY INTEGRATED ESD PROTECTION DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2013
|
Application #:
|
12355900
|
Filing Dt:
|
01/19/2009
|
Publication #:
|
|
Pub Dt:
|
11/05/2009
| | | | |
Title:
|
COMPUTER SYSTEM COMPRISING A SECURE BOOT MECHANISM ON THE BASIS OF SYMMETRIC KEY ENCRYPTION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
12355953
|
Filing Dt:
|
01/19/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
DIRECT CONTACT BETWEEN HIGH-K/METAL GATE AND WIRING PROCESS FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2013
|
Application #:
|
12355954
|
Filing Dt:
|
01/19/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12356105
|
Filing Dt:
|
01/20/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12356187
|
Filing Dt:
|
01/20/2009
|
Publication #:
|
|
Pub Dt:
|
06/18/2009
| | | | |
Title:
|
PHOTORESIST COMPOSITIONS AND METHOD FOR MULTIPLE EXPOSURES WITH MULTIPLE LAYER RESIST SYSTEMS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12356394
|
Filing Dt:
|
01/20/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
AUTONOMIC INFORMATION MANAGEMENT SYSTEM (IMS) MAINFRAME DATABASE POINTER ERROR DIAGNOSTIC DATA EXTRACTION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
12356624
|
Filing Dt:
|
01/21/2009
|
Publication #:
|
|
Pub Dt:
|
07/22/2010
| | | | |
Title:
|
PROCESSOR POWER MANAGEMENT AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12357648
|
Filing Dt:
|
01/22/2009
|
Publication #:
|
|
Pub Dt:
|
05/14/2009
| | | | |
Title:
|
MULTILAYER OPC FOR DESIGN AWARE MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12358736
|
Filing Dt:
|
01/23/2009
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
OPTIMAL DITHERING OF A DIGITALLY CONTROLLED OSCILLATOR WITH CLOCK DITHERING FOR GAIN AND BANDWIDTH CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
12359369
|
Filing Dt:
|
01/26/2009
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
SCHEDULING FOR PARALLEL PROCESSING OF REGIONALLY-CONSTRAINED PLACEMENT PROBLEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2011
|
Application #:
|
12359484
|
Filing Dt:
|
01/26/2009
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
IMPLEMENTING TAMPER EVIDENT AND RESISTANT DETECTION THROUGH MODULATION OF CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/2010
|
Application #:
|
12359520
|
Filing Dt:
|
01/26/2009
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
SEMICONDUCTOR DEVICE HAVING DUAL METAL GATES AND METHOD OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
12359764
|
Filing Dt:
|
01/26/2009
|
Title:
|
METHODS FOR FABRICATING MOS DEVICES HAVING EPITAXIALLY GROWN STRESS-INDUCING SOURCE AND DRAIN REGIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
12360132
|
Filing Dt:
|
01/27/2009
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
TARGET AND METHOD FOR MASK-TO-WAFER CD, PATTERN PLACEMENT AND OVERLAY MEASUREMENT AND CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/2010
|
Application #:
|
12360230
|
Filing Dt:
|
01/27/2009
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
IMPLEMENTING ENHANCED DUAL MODE SRAM PERFORMANCE SCREEN RING OSCILLATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2011
|
Application #:
|
12360242
|
Filing Dt:
|
01/27/2009
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
IMPLEMENTING ENHANCED SRAM STABILITY AND ENHANCED CHIP YIELD WITH CONFIGURABLE WORDLINE VOLTAGE LEVELS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2012
|
Application #:
|
12360402
|
Filing Dt:
|
01/27/2009
|
Publication #:
|
|
Pub Dt:
|
06/25/2009
| | | | |
Title:
|
COLLECTING FAILURE INFORMATION ON ERROR CORRECTION CODE (ECC) PROTECTED DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2012
|
Application #:
|
12360538
|
Filing Dt:
|
01/27/2009
|
Publication #:
|
|
Pub Dt:
|
07/29/2010
| | | | |
Title:
|
SIMPLE RADIO FREQUENCY INTEGRATED CIRCUIT (RFIC) PACKAGES WITH INTEGRATED ANTENNAS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2012
|
Application #:
|
12360961
|
Filing Dt:
|
01/28/2009
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
STRESSED FIELD EFFECT TRANSISTOR AND METHODS FOR ITS FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12362877
|
Filing Dt:
|
01/30/2009
|
Publication #:
|
|
Pub Dt:
|
05/21/2009
| | | | |
Title:
|
STRIPED ON-CHIP INDUCTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
03/01/2011
|
Application #:
|
12363239
|
Filing Dt:
|
01/30/2009
|
Publication #:
|
|
Pub Dt:
|
05/28/2009
| | | | |
Title:
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STRAINED SEMICONDUCTOR-ON-INSULATOR (SSOI) BY A SIMOX METHOD
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Patent #:
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Issue Dt:
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12/14/2010
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Application #:
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12364088
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Filing Dt:
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02/02/2009
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Publication #:
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Pub Dt:
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05/28/2009
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Title:
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COMPRESSIVE NITRIDE FILM AND METHOD OF MANUFACTURING THEREOF
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Patent #:
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Issue Dt:
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01/05/2010
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Application #:
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12364427
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Filing Dt:
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02/02/2009
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Publication #:
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Pub Dt:
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05/28/2009
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Title:
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WEAR GAUGE AND METHOD OF USE
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Patent #:
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Issue Dt:
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10/02/2012
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Application #:
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12365543
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Filing Dt:
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02/04/2009
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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PROCESSOR INSTRUCTIONS FOR IMPROVED AES ENCRYPTION AND DECRYPTION
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Patent #:
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Issue Dt:
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05/22/2012
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Application #:
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12365919
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Filing Dt:
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02/05/2009
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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COMPENSATION OF VCO GAIN CURVE OFFSETS USING AUTO-CALIBRATION
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Patent #:
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Issue Dt:
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05/22/2012
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Application #:
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12365921
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Filing Dt:
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02/05/2009
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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AUTO-CALIBRATION FOR RING OSCILLATOR VCO
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Patent #:
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Issue Dt:
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10/25/2011
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Application #:
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12365963
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Filing Dt:
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02/05/2009
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Publication #:
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Pub Dt:
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10/01/2009
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Title:
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WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEMICONDUCTOR DEVICE BY PROVIDING A PROTECTIVE LAYER
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Patent #:
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Issue Dt:
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06/12/2012
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Application #:
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12365990
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Filing Dt:
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02/05/2009
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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HEAT FLOW MEASUREMENT TOOL FOR A RACK MOUNTED ASSEMBLY OF ELECTRONIC EQUIPMENT
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Patent #:
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Issue Dt:
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10/12/2010
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Application #:
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12366005
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Filing Dt:
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02/05/2009
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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IMPLEMENTING CML MULTIPLEXER LOAD BALANCING
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Patent #:
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Issue Dt:
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05/03/2011
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Application #:
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12366356
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Filing Dt:
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02/05/2009
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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STRESS OPTIMIZATION IN DUAL EMBEDDED EPITAXIALLY GROWN SEMICONDUCTOR PROCESSING
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Patent #:
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Issue Dt:
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08/09/2011
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Application #:
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12366378
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Filing Dt:
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02/05/2009
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Publication #:
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Pub Dt:
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08/05/2010
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Title:
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METHOD TO REDUCE MOL DAMAGE ON NISI
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Patent #:
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Issue Dt:
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01/05/2010
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Application #:
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12366425
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Filing Dt:
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02/05/2009
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Publication #:
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Pub Dt:
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05/28/2009
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Title:
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TRANSISTOR STRUCTURE WITH MINIMIZED PARASITICS AND METHOD OF FABRICATING THE SAME
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Patent #:
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Issue Dt:
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06/05/2012
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Application #:
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12366721
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Filing Dt:
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02/06/2009
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Publication #:
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Pub Dt:
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08/12/2010
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Title:
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LINK-BASED DVR SCHEDULING WITH CONFLICT RESOLUTION
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Patent #:
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Issue Dt:
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10/11/2011
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Application #:
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12367951
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Filing Dt:
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02/09/2009
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Publication #:
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Pub Dt:
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06/04/2009
| | | | |
Title:
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HIGH-DENSITY 3-DIMENSIONAL RESISTORS
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Patent #:
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Issue Dt:
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11/02/2010
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Application #:
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12368452
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Filing Dt:
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02/10/2009
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Publication #:
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Pub Dt:
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06/04/2009
| | | | |
Title:
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POST INITIAL MICROCODE LOAD CO-SIMULATION
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Patent #:
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Issue Dt:
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07/17/2012
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Application #:
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12368561
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Filing Dt:
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02/10/2009
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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FIN AND FINFET FORMATION BY ANGLED ION IMPLANTATION
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Patent #:
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Issue Dt:
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10/25/2011
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Application #:
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12369021
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Filing Dt:
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02/11/2009
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Publication #:
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Pub Dt:
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08/13/2009
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Title:
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CONTINUOUSLY TUNABLE INDUCTOR AND METHOD TO CONTINUOUSLY TUNE AN INDUCTOR
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Patent #:
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Issue Dt:
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09/13/2011
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Application #:
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12369036
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Filing Dt:
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02/11/2009
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Publication #:
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Pub Dt:
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08/13/2009
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Title:
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INDUCTOR AND METHOD OF OPERATING AN INDUCTOR BY COMBINING PRIMARY AND SECONDARY COILS WITH COUPLING STRUCTURES
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Patent #:
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Issue Dt:
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03/01/2011
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Application #:
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12369066
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Filing Dt:
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02/11/2009
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Publication #:
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Pub Dt:
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08/12/2010
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Title:
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CRITICAL PATH REDUNDANT LOGIC FOR MITIGATION OF HARDWARE ACROSS CHIP VARIATION
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12369099
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Filing Dt:
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02/11/2009
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Publication #:
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Pub Dt:
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08/12/2010
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Title:
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SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND STRUCTURE INCLUDING MULTIPLE ORDER RADIO FERQUENCY HARMONIC SUPRESSING REGION
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Patent #:
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Issue Dt:
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11/30/2010
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Application #:
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12369249
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Filing Dt:
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02/11/2009
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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SOI RADIO FREQUENCY SWITCH WITH REDUCED SIGNAL DISTORTION
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Patent #:
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Issue Dt:
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03/12/2013
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Application #:
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12370356
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Filing Dt:
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02/12/2009
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Publication #:
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Pub Dt:
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08/12/2010
| | | | |
Title:
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HIGH-SPEED ELECTROSTATIC ACTUATION OF MEMS-BASED DEVICES
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Patent #:
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Issue Dt:
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01/17/2012
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Application #:
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12371180
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Filing Dt:
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02/13/2009
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Publication #:
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Pub Dt:
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06/11/2009
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Title:
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ULTRA LOW K PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION PROCESSES USING A SINGLE BIFUNCTIONAL PRECURSOR CONTAINING BOTH A SICOH MATRIX FUNCTIONALITY AND ORGANIC POROGEN FUNCTIONALITY
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Patent #:
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Issue Dt:
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12/28/2010
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Application #:
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12371756
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Filing Dt:
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02/16/2009
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Publication #:
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Pub Dt:
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06/18/2009
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Title:
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HIGH YIELD, HIGH DENSITY ON-CHIP CAPACITOR DESIGN
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Patent #:
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Issue Dt:
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02/22/2011
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Application #:
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12371943
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Filing Dt:
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02/17/2009
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Publication #:
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Pub Dt:
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08/19/2010
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Title:
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NANOWIRE MESH DEVICE AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
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04/24/2012
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Application #:
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12371956
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Filing Dt:
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02/17/2009
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Publication #:
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Pub Dt:
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08/19/2010
| | | | |
Title:
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METHOD FOR SELECTIVELY ADJUSTING LOCAL RESIST PATTERN DIMENSION WITH CHEMICAL TREATMENT
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Patent #:
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Issue Dt:
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01/24/2012
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Application #:
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12388060
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Filing Dt:
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02/18/2009
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Publication #:
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Pub Dt:
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11/05/2009
| | | | |
Title:
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METHOD AND SYSTEM FOR SEMICONDUCTOR PROCESS CONTROL AND MONITORING BY USING PCA MODELS OF REDUCED SIZE
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Patent #:
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Issue Dt:
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09/27/2011
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Application #:
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12388094
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Filing Dt:
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02/18/2009
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Publication #:
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Pub Dt:
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08/19/2010
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Title:
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METAL OXIDE SEMICONDUCTOR DEVICES HAVING DOPED SILICON-COMPROMISING CAPPING LAYERS AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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12388586
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Filing Dt:
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02/19/2009
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Publication #:
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Pub Dt:
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08/19/2010
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Title:
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ASYMMETRIC JUNCTION FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12388932
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Filing Dt:
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02/19/2009
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Publication #:
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Pub Dt:
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08/19/2010
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Title:
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PERFORMING A STATISTICAL TIMING ABSTRACTION FOR A HIERARCHICAL TIMING ANALYSIS OF VLSI CIRCUITS
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Patent #:
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Issue Dt:
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01/11/2011
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Application #:
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12389618
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Filing Dt:
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02/20/2009
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Publication #:
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Pub Dt:
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06/25/2009
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Title:
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DIGITAL TO ANALOG CONVERTER HAVING FASTPATHS
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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12390739
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Filing Dt:
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02/23/2009
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Publication #:
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Pub Dt:
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08/26/2010
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Title:
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EDRAM MEMORY CELL STRUCTURE AND METHOD OF FABRICATING
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Patent #:
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Issue Dt:
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07/03/2012
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Application #:
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12390816
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Filing Dt:
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02/23/2009
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Publication #:
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Pub Dt:
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12/03/2009
| | | | |
Title:
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COLD TEMPERATURE CONTROL IN A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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11/01/2011
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Application #:
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12390907
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Filing Dt:
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02/23/2009
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Publication #:
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Pub Dt:
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08/26/2010
| | | | |
Title:
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METHOD OF FORMING A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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02/26/2013
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Application #:
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12391547
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Filing Dt:
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02/24/2009
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Publication #:
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Pub Dt:
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08/26/2010
| | | | |
Title:
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LENGTHENING LIFE OF A LIMITED LIFE MEMORY
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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12391631
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Filing Dt:
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02/24/2009
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Publication #:
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Pub Dt:
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08/26/2010
| | | | |
Title:
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EDRAM INCLUDING METAL PLATES
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Patent #:
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Issue Dt:
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04/24/2012
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Application #:
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12391678
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Filing Dt:
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02/24/2009
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Publication #:
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Pub Dt:
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08/26/2010
| | | | |
Title:
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WRITING A SPECIAL SYMBOL TO A MEMORY TO INDICATE THE ABSENCE OF A DATA SIGNAL
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Patent #:
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Issue Dt:
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09/20/2011
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Application #:
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12391693
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Filing Dt:
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02/24/2009
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Publication #:
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Pub Dt:
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08/26/2010
| | | | |
Title:
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ITERATIVELY WRITING CONTENTS TO MEMORY LOCATIONS USING A STATISTICAL MODEL
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12392032
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Filing Dt:
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02/24/2009
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Publication #:
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Pub Dt:
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08/26/2010
| | | | |
Title:
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MEMORY READING METHOD FOR RESISTANCE DRIFT MITIGATION
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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12392049
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Filing Dt:
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02/24/2009
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Publication #:
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Pub Dt:
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08/26/2010
| | | | |
Title:
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CODING TECHNIQUES FOR IMPROVING THE SENSE MARGIN IN CONTENT ADDRESSABLE MEMORIES
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Patent #:
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Issue Dt:
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04/12/2011
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Application #:
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12393156
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Filing Dt:
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02/26/2009
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Publication #:
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Pub Dt:
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08/26/2010
| | | | |
Title:
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IMPLEMENTING ENHANCED ARRAY ACCESS TIME TRACKING WITH LOGIC BUILT IN SELF TEST OF DYNAMIC MEMORY AND RANDOM LOGIC
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Patent #:
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Issue Dt:
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11/16/2010
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Application #:
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12393346
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Filing Dt:
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02/26/2009
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Publication #:
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Pub Dt:
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08/13/2009
| | | | |
Title:
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HEATPLATES FOR HEATSINK ATTACHMENT FOR SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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08/28/2012
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Application #:
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12394560
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Filing Dt:
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02/27/2009
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Publication #:
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Pub Dt:
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09/02/2010
| | | | |
Title:
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LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING
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