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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
1
Patent #:
Issue Dt:
02/24/2015
Application #:
12553475
Filing Dt:
09/03/2009
Publication #:
Pub Dt:
04/01/2010
Title:
SEMICONDUCTOR DEVICE COMPRISING A BURIED POLY RESISTOR
2
Patent #:
Issue Dt:
05/15/2012
Application #:
12553505
Filing Dt:
09/03/2009
Publication #:
Pub Dt:
01/21/2010
Title:
DIFFERENTIAL ALTERNATING PHASE SHIFT MASK OPTIMIZATION
3
Patent #:
Issue Dt:
01/08/2013
Application #:
12554175
Filing Dt:
09/04/2009
Publication #:
Pub Dt:
03/10/2011
Title:
METHOD OF FORMING SELF-ASSEMBLED PATTERNS USING BLOCK COPOLYMERS, AND ARTICLES THEREOF
4
Patent #:
Issue Dt:
04/05/2011
Application #:
12554344
Filing Dt:
09/04/2009
Publication #:
Pub Dt:
12/31/2009
Title:
PARTIALLY DEPLETED SOI FIELD EFFECT TRANSISTOR HAVING A METALLIZED SOURCE SIDE HALO REGION
5
Patent #:
Issue Dt:
02/14/2012
Application #:
12555241
Filing Dt:
09/08/2009
Publication #:
Pub Dt:
12/31/2009
Title:
ELECTRICAL ANTIFUSE
6
Patent #:
Issue Dt:
05/15/2012
Application #:
12555337
Filing Dt:
09/08/2009
Publication #:
Pub Dt:
03/10/2011
Title:
METHOD AND SYSTEM FOR PROBLEM DETERMINATION USING PROBE COLLECTIONS AND PROBLEM CLASSIFICATION FOR THE TECHNICAL SUPPORT SERVICES
7
Patent #:
Issue Dt:
08/07/2012
Application #:
12555350
Filing Dt:
09/08/2009
Publication #:
Pub Dt:
12/31/2009
Title:
CMOS DEVICES INCORPORATING HYBRID ORIENTATION TECHNOLOGY (HOT) WITH EMBEDDED CONNECTORS
8
Patent #:
Issue Dt:
03/20/2012
Application #:
12555879
Filing Dt:
09/09/2009
Publication #:
Pub Dt:
04/01/2010
Title:
TRANSISTOR DEVICE COMPRISING AN ASYMMETRIC EMBEDDED SEMICONDUCTOR ALLOY
9
Patent #:
Issue Dt:
12/18/2012
Application #:
12556139
Filing Dt:
09/09/2009
Publication #:
Pub Dt:
03/10/2011
Title:
PIXEL SENSORS OF MULTIPLE PIXEL SIZE AND METHODS OF IMPLANT DOSE CONTROL
10
Patent #:
Issue Dt:
01/31/2012
Application #:
12556198
Filing Dt:
09/09/2009
Publication #:
Pub Dt:
03/10/2011
Title:
IN VIA FORMED PHASE CHANGE MEMORY CELL WITH RECESSED PILLAR HEATER
11
Patent #:
Issue Dt:
12/07/2010
Application #:
12556261
Filing Dt:
09/09/2009
Publication #:
Pub Dt:
12/31/2009
Title:
HIGH PERFORMANCE CMOS DEVICES COMPRISING GAPPED DUAL STRESSORS WITH DIELECTRIC GAP FILLERS, AND METHODS OF FABRICATING THE SAME
12
Patent #:
Issue Dt:
04/12/2011
Application #:
12556335
Filing Dt:
09/09/2009
Publication #:
Pub Dt:
09/02/2010
Title:
METHOD OF CONTROLLING THE COMPOSITION OF A PHOTOVOLTAIC THIN FILM
13
Patent #:
Issue Dt:
03/01/2011
Application #:
12556604
Filing Dt:
09/10/2009
Publication #:
Pub Dt:
03/10/2011
Title:
DEVICE HAVING SELF-ALIGNED DOUBLE GATE FORMED BY BACKSIDE ENGINEERING, AND DEVICE HAVING SUPER-STEEP RETROGRADED ISLAND
14
Patent #:
Issue Dt:
10/16/2012
Application #:
12557122
Filing Dt:
09/10/2009
Publication #:
Pub Dt:
03/10/2011
Title:
PIEZOELECTRIC BASED ENERGY SUPPLY USING INDEPENDENT PIEZOELECTRIC COMPONENTS
15
Patent #:
Issue Dt:
02/22/2011
Application #:
12557139
Filing Dt:
09/10/2009
Publication #:
Pub Dt:
03/10/2011
Title:
ADAPTIVE COMMON MODE BIAS FOR DIFFERENTIAL AMPLIFIER INPUT CIRCUITS
16
Patent #:
Issue Dt:
08/23/2011
Application #:
12557557
Filing Dt:
09/11/2009
Publication #:
Pub Dt:
01/07/2010
Title:
BIPOLAR TRANSISTOR WITH SILICIDED SUB-COLLECTOR
17
Patent #:
Issue Dt:
07/31/2012
Application #:
12558839
Filing Dt:
09/14/2009
Publication #:
Pub Dt:
03/17/2011
Title:
SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO
18
Patent #:
Issue Dt:
11/23/2010
Application #:
12559052
Filing Dt:
09/14/2009
Title:
SPRAY PYROLYSIS FOR LARGE-SCALE PRODUCTION OF CHALCOPYRITE ABSORBER LAYER IN PHOTOVOLTAIC DEVICES
19
Patent #:
Issue Dt:
07/26/2011
Application #:
12559115
Filing Dt:
09/14/2009
Publication #:
Pub Dt:
03/17/2011
Title:
PLANARIZATION STOP LAYER IN PHASE CHANGE MEMORY INTEGRATION
20
Patent #:
Issue Dt:
10/04/2011
Application #:
12560031
Filing Dt:
09/15/2009
Publication #:
Pub Dt:
03/17/2011
Title:
DEVICE AND METHOD FOR PROVIDING AN INTEGRATED CIRCUIT WITH A UNIQUE INDENTIFICATION
21
Patent #:
Issue Dt:
07/09/2013
Application #:
12560585
Filing Dt:
09/16/2009
Publication #:
Pub Dt:
03/17/2011
Title:
METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR
22
Patent #:
Issue Dt:
04/05/2011
Application #:
12560593
Filing Dt:
09/16/2009
Publication #:
Pub Dt:
03/17/2011
Title:
DELAY CIRCUIT WITH DELAY EQUAL TO PERCENTAGE OF INPUT PULSE WIDTH
23
Patent #:
Issue Dt:
06/07/2011
Application #:
12560878
Filing Dt:
09/16/2009
Publication #:
Pub Dt:
03/17/2011
Title:
LARGE GRAIN SIZE CONDUCTIVE STRUCTURE FOR NARROW INTERCONNECT OPENINGS
24
Patent #:
Issue Dt:
12/27/2011
Application #:
12560938
Filing Dt:
09/16/2009
Publication #:
Pub Dt:
03/17/2011
Title:
THIN BODY SEMICONDUCTOR DEVICES HAVING IMPROVED CONTACT RESISTANCE AND METHODS FOR THE FABRICATION THEREOF
25
Patent #:
Issue Dt:
03/20/2012
Application #:
12561581
Filing Dt:
09/17/2009
Publication #:
Pub Dt:
03/17/2011
Title:
STRUCTURES, DESIGN STRUCTURES AND METHODS OF FABRICATING GLOBAL SHUTTER PIXEL SENSOR CELLS
26
Patent #:
Issue Dt:
02/21/2012
Application #:
12561638
Filing Dt:
09/17/2009
Publication #:
Pub Dt:
03/17/2011
Title:
FABRICATION OF SEMICONDUCTORS WITH HIGH-K/METAL GATE ELECTRODES
27
Patent #:
Issue Dt:
02/21/2012
Application #:
12561685
Filing Dt:
09/17/2009
Publication #:
Pub Dt:
03/17/2011
Title:
EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY
28
Patent #:
Issue Dt:
08/14/2012
Application #:
12561694
Filing Dt:
09/17/2009
Publication #:
Pub Dt:
03/17/2011
Title:
MOSFET WITH A NANOWIRE CHANNEL AND FULLY SILICIDED (FUSI) WRAPPED AROUND GATE
29
Patent #:
Issue Dt:
11/08/2011
Application #:
12561701
Filing Dt:
09/17/2009
Publication #:
Pub Dt:
05/06/2010
Title:
REDUCED WAFER WARPAGE IN SEMICONDUCTORS BY STRESS ENGINEERING IN THE METALLIZATION SYSTEM
30
Patent #:
Issue Dt:
07/31/2012
Application #:
12561704
Filing Dt:
09/17/2009
Publication #:
Pub Dt:
03/17/2011
Title:
STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS
31
Patent #:
Issue Dt:
11/01/2011
Application #:
12561708
Filing Dt:
09/17/2009
Publication #:
Pub Dt:
03/17/2011
Title:
METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION
32
Patent #:
Issue Dt:
05/14/2013
Application #:
12561827
Filing Dt:
09/17/2009
Publication #:
Pub Dt:
01/14/2010
Title:
BEOL COMPATIBLE FET STRUCTURE
33
Patent #:
Issue Dt:
05/24/2011
Application #:
12561880
Filing Dt:
09/17/2009
Publication #:
Pub Dt:
03/17/2011
Title:
DUAL DIELECTRIC TRI-GATE FIELD EFFECT TRANSISTOR
34
Patent #:
Issue Dt:
02/01/2011
Application #:
12562262
Filing Dt:
09/18/2009
Publication #:
Pub Dt:
01/14/2010
Title:
VIRTUALIZING AN IOMMU
35
Patent #:
Issue Dt:
04/17/2012
Application #:
12562419
Filing Dt:
09/18/2009
Publication #:
Pub Dt:
03/24/2011
Title:
METHOD OF FABRICATING A TRENCH-GENERATED TRANSISTOR STRUCTURE
36
Patent #:
Issue Dt:
12/11/2012
Application #:
12562540
Filing Dt:
09/18/2009
Publication #:
Pub Dt:
03/24/2011
Title:
SYSTEM TO REDUCE THE TIME AND COMPLEXITY OF SELF CONFIGURING SYSTEMS
37
Patent #:
Issue Dt:
10/22/2013
Application #:
12562556
Filing Dt:
09/18/2009
Publication #:
Pub Dt:
05/06/2010
Title:
METHOD AND DEVICE FOR FABRICATING BONDING WIRES ON THE BASIS OF MICROELECTRONIC MANUFACTURING TECHNIQUES
38
Patent #:
Issue Dt:
08/27/2013
Application #:
12562659
Filing Dt:
09/18/2009
Publication #:
Pub Dt:
03/24/2011
Title:
METHOD TO COMPUTE WAIT TIME
39
Patent #:
Issue Dt:
02/09/2016
Application #:
12562849
Filing Dt:
09/18/2009
Publication #:
Pub Dt:
03/24/2011
Title:
SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING ISOLATION BETWEEN FIN STRUCTURES OF FINFET DEVICES
40
Patent #:
Issue Dt:
07/26/2011
Application #:
12562873
Filing Dt:
09/18/2009
Publication #:
Pub Dt:
03/24/2011
Title:
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTIVE RESISTOR STRUCTURE
41
Patent #:
Issue Dt:
09/25/2012
Application #:
12563021
Filing Dt:
09/18/2009
Publication #:
Pub Dt:
03/24/2011
Title:
AUTOMATIC POSITIONING OF GATE ARRAY CIRCUITS IN AN INTEGRATED CIRCUIT DESIGN
42
Patent #:
Issue Dt:
10/30/2012
Application #:
12563032
Filing Dt:
09/18/2009
Publication #:
Pub Dt:
03/24/2011
Title:
METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SIGE
43
Patent #:
Issue Dt:
02/15/2011
Application #:
12563183
Filing Dt:
09/21/2009
Title:
HYBRID SUPERCONDUCTOR-OPTICAL QUANTUM REPEATER
44
Patent #:
Issue Dt:
06/25/2013
Application #:
12563186
Filing Dt:
09/21/2009
Publication #:
Pub Dt:
03/24/2011
Title:
MEMORY LEAK MONITORING SYSTEM AND ASSOCIATED METHODS
45
Patent #:
Issue Dt:
02/28/2012
Application #:
12563553
Filing Dt:
09/21/2009
Publication #:
Pub Dt:
03/24/2011
Title:
LOCAL BOTTOM GATES FOR GRAPHENE AND CARBON NANOTUBE DEVICES
46
Patent #:
Issue Dt:
06/28/2011
Application #:
12563610
Filing Dt:
09/21/2009
Publication #:
Pub Dt:
03/24/2011
Title:
BIDIRECTIONAL ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS
47
Patent #:
Issue Dt:
09/18/2012
Application #:
12564061
Filing Dt:
09/22/2009
Publication #:
Pub Dt:
03/24/2011
Title:
METHOD AND SYSTEM FOR DESIGN AND MODELING OF TRANSMISSION LINES
48
Patent #:
Issue Dt:
08/07/2012
Application #:
12564482
Filing Dt:
09/22/2009
Publication #:
Pub Dt:
01/14/2010
Title:
DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE
49
Patent #:
Issue Dt:
02/15/2011
Application #:
12564570
Filing Dt:
09/22/2009
Title:
LOW-VOLTAGE CMOS ERROR AMPLIFIER WITH IMPLICIT REFERENCE
50
Patent #:
Issue Dt:
05/28/2013
Application #:
12564996
Filing Dt:
09/23/2009
Publication #:
Pub Dt:
03/24/2011
Title:
THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE
51
Patent #:
Issue Dt:
06/12/2012
Application #:
12565020
Filing Dt:
09/23/2009
Publication #:
Pub Dt:
05/06/2010
Title:
STRESS TRANSFER ENHANCEMENT IN TRANSISTORS BY A LATE GATE RE-CRYSTALLIZATION
52
Patent #:
Issue Dt:
05/29/2012
Application #:
12565802
Filing Dt:
09/24/2009
Publication #:
Pub Dt:
03/24/2011
Title:
MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY
53
Patent #:
Issue Dt:
09/20/2011
Application #:
12566004
Filing Dt:
09/24/2009
Publication #:
Pub Dt:
03/24/2011
Title:
HIGH-PERFORMANCE FETS WITH EMBEDDED STRESSORS
54
Patent #:
Issue Dt:
06/23/2015
Application #:
12566255
Filing Dt:
09/24/2009
Publication #:
Pub Dt:
03/24/2011
Title:
Parallel Processing of ETL Jobs Involving Extensible Markup Language Documents
55
Patent #:
Issue Dt:
02/28/2012
Application #:
12566430
Filing Dt:
09/24/2009
Publication #:
Pub Dt:
03/24/2011
Title:
ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES
56
Patent #:
Issue Dt:
06/05/2012
Application #:
12566717
Filing Dt:
09/25/2009
Publication #:
Pub Dt:
03/31/2011
Title:
ASYMMETRIC SILICON-ON-INSULATOR SRAM CELL
57
Patent #:
Issue Dt:
12/25/2012
Application #:
12566862
Filing Dt:
09/25/2009
Publication #:
Pub Dt:
03/31/2011
Title:
DUAL BETA RATIO SRAM
58
Patent #:
Issue Dt:
08/14/2012
Application #:
12566870
Filing Dt:
09/25/2009
Publication #:
Pub Dt:
03/31/2011
Title:
ACTIVATION OF GRAPHENE BUFFER LAYERS ON SILICON CARBIDE BY ULTRA LOW TEMPERATURE OXIDATION
59
Patent #:
Issue Dt:
05/24/2011
Application #:
12567279
Filing Dt:
09/25/2009
Publication #:
Pub Dt:
02/04/2010
Title:
APPARATUS AND METHOD FOR REMOVING BUBBLES FROM A PROCESS LIQUID
60
Patent #:
Issue Dt:
09/13/2011
Application #:
12567490
Filing Dt:
09/25/2009
Publication #:
Pub Dt:
01/21/2010
Title:
INTEGRATED CIRCUIT HARD MASK PROCESSING SYSTEM
61
Patent #:
Issue Dt:
05/15/2012
Application #:
12567963
Filing Dt:
09/28/2009
Publication #:
Pub Dt:
03/31/2011
Title:
REPLACEMENT SPACER FOR TUNNEL FETS
62
Patent #:
Issue Dt:
07/24/2012
Application #:
12568035
Filing Dt:
09/28/2009
Publication #:
Pub Dt:
03/31/2011
Title:
WRITING TO MEMORY USING ADAPTIVE WRITE TECHNIQUES
63
Patent #:
Issue Dt:
07/31/2012
Application #:
12568083
Filing Dt:
09/28/2009
Publication #:
Pub Dt:
03/31/2011
Title:
TOOL COMMONALITY AND STRATIFICATION ANALYSIS TO ENHANCE A PRODUCTION PROCESS
64
Patent #:
Issue Dt:
08/07/2012
Application #:
12568287
Filing Dt:
09/28/2009
Publication #:
Pub Dt:
03/31/2011
Title:
SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE
65
Patent #:
Issue Dt:
08/07/2012
Application #:
12568985
Filing Dt:
09/29/2009
Publication #:
Pub Dt:
03/31/2011
Title:
SYSTEM AND METHOD FOR ESTIMATING LEAKAGE CURRENT OF AN ELECTRONIC CIRCUIT
66
Patent #:
Issue Dt:
06/19/2012
Application #:
12569200
Filing Dt:
09/29/2009
Publication #:
Pub Dt:
03/31/2011
Title:
PATTERNABLE LOW-K DIELECTRIC INTERCONNECT STRUCTURE WITH A GRADED CAP LAYER AND METHOD OF FABRICATION
67
Patent #:
Issue Dt:
12/18/2012
Application #:
12569421
Filing Dt:
09/29/2009
Publication #:
Pub Dt:
03/31/2011
Title:
CHARACTERIZATION OF LONG RANGE VARIABILITY
68
Patent #:
Issue Dt:
03/27/2012
Application #:
12570333
Filing Dt:
09/30/2009
Publication #:
Pub Dt:
03/31/2011
Title:
BUSINESS PROCESS ERROR HANDLING THROUGH PROCESS INSTANCE BACKUP AND RECOVERY
69
Patent #:
Issue Dt:
12/27/2011
Application #:
12570384
Filing Dt:
09/30/2009
Publication #:
Pub Dt:
03/31/2011
Title:
ENHANCED STRESS-RETENTION FIN-FET DEVICES AND METHODS OF FABRICATING ENHANCED STRESS RETENTION FIN-FET DEVICES
70
Patent #:
Issue Dt:
08/07/2012
Application #:
12570418
Filing Dt:
09/30/2009
Publication #:
Pub Dt:
03/31/2011
Title:
METHOD FOR CALCULATING CAPACITANCE GRADIENTS IN VLSI LAYOUTS USING A SHAPE PROCESSING ENGINE
71
Patent #:
Issue Dt:
12/25/2012
Application #:
12571477
Filing Dt:
10/01/2009
Publication #:
Pub Dt:
04/07/2011
Title:
CLEANING EXHAUST SCREENS IN A MANUFACTURING PROCESS
72
Patent #:
Issue Dt:
07/24/2012
Application #:
12572297
Filing Dt:
10/02/2009
Publication #:
Pub Dt:
01/28/2010
Title:
METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING
73
Patent #:
Issue Dt:
03/31/2015
Application #:
12573188
Filing Dt:
10/05/2009
Publication #:
Pub Dt:
04/07/2011
Title:
STRUCTURE AND METHOD TO CREATE A DAMASCENE LOCAL INTERCONNECT DURING METAL GATE DEPOSITION
74
Patent #:
Issue Dt:
01/11/2011
Application #:
12573407
Filing Dt:
10/05/2009
Publication #:
Pub Dt:
01/28/2010
Title:
LOW LEAKAGE METAL-CONTAINING CAP PROCESS USING OXIDATION
75
Patent #:
Issue Dt:
10/01/2013
Application #:
12573440
Filing Dt:
10/05/2009
Publication #:
Pub Dt:
04/07/2011
Title:
METAL GATE FET HAVING REDUCED THRESHOLD VOLTAGE ROLL-OFF
76
Patent #:
Issue Dt:
04/19/2011
Application #:
12574118
Filing Dt:
10/06/2009
Publication #:
Pub Dt:
04/07/2011
Title:
VARYING CAPACITANCE VOLTAGE CONTRAST STRUCTURES TO DETERMINE DEFECT RESISTANCE
77
Patent #:
Issue Dt:
03/25/2014
Application #:
12574126
Filing Dt:
10/06/2009
Publication #:
Pub Dt:
04/07/2011
Title:
SPLIT LEVEL SHALLOW TRENCH ISOLATION FOR AREA EFFICIENT BODY CONTACTS IN SOI MOSFETS
78
Patent #:
Issue Dt:
02/03/2015
Application #:
12574296
Filing Dt:
10/06/2009
Publication #:
Pub Dt:
04/07/2011
Title:
MERGED FINFETS AND METHOD OF MANUFACTURING THE SAME
79
Patent #:
Issue Dt:
05/17/2011
Application #:
12574318
Filing Dt:
10/06/2009
Publication #:
Pub Dt:
04/07/2011
Title:
METHODS FOR OBTAINING GATE STACKS WITH TUNABLE THRESHOLD VOLTAGE AND SCALING
80
Patent #:
Issue Dt:
02/28/2012
Application #:
12574926
Filing Dt:
10/07/2009
Publication #:
Pub Dt:
04/07/2011
Title:
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
81
Patent #:
Issue Dt:
02/05/2013
Application #:
12575068
Filing Dt:
10/07/2009
Publication #:
Pub Dt:
04/07/2011
Title:
SHAPE CHARACTERIZATION WITH ELLIPTIC FOURIER DESCRIPTOR FOR CONTACT OR ANY CLOSED STRUCTURES ON THE CHIP
82
Patent #:
Issue Dt:
01/24/2012
Application #:
12575344
Filing Dt:
10/07/2009
Publication #:
Pub Dt:
04/07/2011
Title:
METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL
83
Patent #:
Issue Dt:
03/05/2013
Application #:
12575515
Filing Dt:
10/08/2009
Publication #:
Pub Dt:
04/14/2011
Title:
PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF
84
Patent #:
Issue Dt:
03/20/2012
Application #:
12575962
Filing Dt:
10/08/2009
Publication #:
Pub Dt:
04/14/2011
Title:
SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL)
85
Patent #:
Issue Dt:
07/09/2013
Application #:
12575980
Filing Dt:
10/08/2009
Publication #:
Pub Dt:
04/14/2011
Title:
PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT
86
Patent #:
Issue Dt:
03/27/2012
Application #:
12575989
Filing Dt:
10/08/2009
Publication #:
Pub Dt:
04/14/2011
Title:
EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE
87
Patent #:
Issue Dt:
03/06/2012
Application #:
12576275
Filing Dt:
10/09/2009
Publication #:
Pub Dt:
04/14/2011
Title:
METHOD AND APPARATUS FOR CONFIGURING A CONTENT-ADDRESSABLE MEMORY (CAM) DESIGN AS BINARY CAM OR TERNARY CAM
88
Patent #:
Issue Dt:
09/17/2013
Application #:
12576597
Filing Dt:
10/09/2009
Publication #:
Pub Dt:
04/14/2011
Title:
MASK PROGRAM DEFECT TEST
89
Patent #:
Issue Dt:
10/04/2011
Application #:
12576987
Filing Dt:
10/09/2009
Publication #:
Pub Dt:
04/14/2011
Title:
SEMICONDUCTOR DEVICE WITH STRESSED FIN SECTIONS, AND RELATED FABRICATION METHODS
90
Patent #:
Issue Dt:
10/16/2012
Application #:
12577259
Filing Dt:
10/12/2009
Publication #:
Pub Dt:
04/14/2011
Title:
NOISE COUPLING REDUCTION AND IMPEDANCE DISCONTINUITY CONTROL IN HIGH-SPEED CERAMIC MODULES
91
Patent #:
Issue Dt:
12/20/2011
Application #:
12578372
Filing Dt:
10/13/2009
Publication #:
Pub Dt:
04/14/2011
Title:
MANAGING AVAILABILITY OF A COMPONENT HAVING A CLOSED ADDRESS SPACE
92
Patent #:
Issue Dt:
07/10/2012
Application #:
12579089
Filing Dt:
10/14/2009
Publication #:
Pub Dt:
04/14/2011
Title:
WORD-LINE LEVEL SHIFT CIRCUIT
93
Patent #:
Issue Dt:
09/17/2013
Application #:
12579124
Filing Dt:
10/14/2009
Publication #:
Pub Dt:
04/14/2011
Title:
REAL-TIME PERFORMANCE MODELING OF SOFTWARE SYSTEMS WITH MULTI-CLASS WORKLOAD
94
Patent #:
Issue Dt:
08/14/2012
Application #:
12579216
Filing Dt:
10/14/2009
Publication #:
Pub Dt:
04/14/2011
Title:
METHODS RELATING TO CAPACITIVE MONITORING OF LAYER CHARACTERISTICS DURING BACK END-OF-THE-LINE PROCESSING
95
Patent #:
Issue Dt:
10/23/2012
Application #:
12579442
Filing Dt:
10/15/2009
Publication #:
Pub Dt:
04/21/2011
Title:
SAT-BASED SYNTHESIS OF A CLOCK GATING FUNCTION
96
Patent #:
Issue Dt:
09/18/2012
Application #:
12579654
Filing Dt:
10/15/2009
Publication #:
Pub Dt:
05/06/2010
Title:
SEMICONDUCTOR DEVICE COMPRISING EFUSES OF ENHANCED PROGRAMMING EFFICIENCY
97
Patent #:
Issue Dt:
12/04/2012
Application #:
12580330
Filing Dt:
10/16/2009
Publication #:
Pub Dt:
04/21/2011
Title:
TECHNIQUES FOR ANALYSIS OF LOGIC DESIGNS WITH TRANSIENT LOGIC
98
Patent #:
Issue Dt:
07/31/2012
Application #:
12581440
Filing Dt:
10/19/2009
Publication #:
Pub Dt:
04/21/2011
Title:
SRAM DELAY CIRCUIT THAT TRACKS BITCELL CHARACTERISTICS
99
Patent #:
Issue Dt:
10/11/2011
Application #:
12581924
Filing Dt:
10/20/2009
Publication #:
Pub Dt:
04/21/2011
Title:
STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES
100
Patent #:
Issue Dt:
10/16/2012
Application #:
12582139
Filing Dt:
10/20/2009
Publication #:
Pub Dt:
04/21/2011
Title:
APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS
Assignor
1
Exec Dt:
11/27/2018
Assignee
1
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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