skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
1
Patent #:
Issue Dt:
06/12/2012
Application #:
12583030
Filing Dt:
08/12/2009
Publication #:
Pub Dt:
12/10/2009
Title:
METHODS OF FABRICATING PLASTICIZED, ANTIPLASTICIZED AND CRYSTALLINE CONDUCTING POLYMERS AND PRECURSORS THEREOF
2
Patent #:
Issue Dt:
10/30/2012
Application #:
12603567
Filing Dt:
10/21/2009
Publication #:
Pub Dt:
04/21/2011
Title:
SPIN-MOUNTED FABRICATION OF INJECTION MOLDED MICRO-OPTICS
3
Patent #:
Issue Dt:
01/24/2012
Application #:
12603569
Filing Dt:
10/21/2009
Publication #:
Pub Dt:
04/21/2011
Title:
FABRICATION OF OPTICAL FILTERS INTEGRATED WITH INJECTION MOLDED MICROLENSES
4
Patent #:
Issue Dt:
04/28/2015
Application #:
12603668
Filing Dt:
10/22/2009
Publication #:
Pub Dt:
04/28/2011
Title:
CREATING EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) HAVING SUBSTANTIALLY UNIFORM THICKNESS
5
Patent #:
Issue Dt:
02/28/2012
Application #:
12603671
Filing Dt:
10/22/2009
Publication #:
Pub Dt:
04/28/2011
Title:
METHOD OF CREATING AN EXTREMELY THIN SEMICONDUCTOR-ON- INSULATOR (ETSOI) LAYER HAVING A UNIFORM THICKNESS
6
Patent #:
Issue Dt:
10/30/2012
Application #:
12603679
Filing Dt:
10/22/2009
Publication #:
Pub Dt:
04/28/2011
Title:
SYSTEM AND METHOD FOR CORRECTING SYSTEMATIC PARAMETRIC VARIATIONS ON INTEGRATED CIRCUIT CHIPS IN ORDER TO MINIMIZE CIRCUIT LIMITED YIELD LOSS
7
Patent #:
Issue Dt:
02/07/2012
Application #:
12603737
Filing Dt:
10/22/2009
Publication #:
Pub Dt:
04/28/2011
Title:
FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER
8
Patent #:
Issue Dt:
06/26/2012
Application #:
12603838
Filing Dt:
10/22/2009
Publication #:
Pub Dt:
02/18/2010
Title:
TRIPLE GATE AND DOUBLE GATE FINFETS WITH DIFFERENT VERTICAL DIMENSION FINS
9
Patent #:
Issue Dt:
04/26/2011
Application #:
12604281
Filing Dt:
10/22/2009
Publication #:
Pub Dt:
04/28/2011
Title:
METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS
10
Patent #:
Issue Dt:
05/31/2011
Application #:
12604614
Filing Dt:
10/23/2009
Publication #:
Pub Dt:
04/28/2011
Title:
SOLID STATE DRIVE WITH FLASH SPARING
11
Patent #:
Issue Dt:
11/11/2014
Application #:
12604703
Filing Dt:
10/23/2009
Publication #:
Pub Dt:
06/03/2010
Title:
MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES
12
Patent #:
Issue Dt:
03/26/2013
Application #:
12605417
Filing Dt:
10/26/2009
Publication #:
Pub Dt:
04/28/2011
Title:
DYNAMICALLY RECONFIGURABLE SELF-MONITORING CIRCUIT
13
Patent #:
Issue Dt:
12/24/2013
Application #:
12605523
Filing Dt:
10/26/2009
Publication #:
Pub Dt:
04/28/2011
Title:
NANOWIRE STRESS SENSORS, STRESS SENSOR INTEGRATED CIRCUITS, AND DESIGN STRUCTURES FOR A STRESS SENSOR INTEGRATED CIRCUIT
14
Patent #:
Issue Dt:
10/11/2011
Application #:
12607104
Filing Dt:
10/28/2009
Publication #:
Pub Dt:
04/28/2011
Title:
BI-LAYER NFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT
15
Patent #:
Issue Dt:
02/21/2012
Application #:
12607116
Filing Dt:
10/28/2009
Publication #:
Pub Dt:
04/28/2011
Title:
HIGH-DRIVE CURRENT MOSFET
16
Patent #:
Issue Dt:
11/13/2012
Application #:
12607258
Filing Dt:
10/28/2009
Publication #:
Pub Dt:
04/28/2011
Title:
SURFACE CHARGE ENABLED NANOPOROUS SEMI-PERMEABLE MEMBRANE FOR DESALINATION
17
Patent #:
Issue Dt:
04/17/2012
Application #:
12608368
Filing Dt:
10/29/2009
Publication #:
Pub Dt:
05/05/2011
Title:
HYBRID BONDING INTERFACE FOR 3-DIMENSIONAL CHIP INTEGRATION
18
Patent #:
Issue Dt:
06/14/2011
Application #:
12608518
Filing Dt:
10/29/2009
Publication #:
Pub Dt:
02/25/2010
Title:
COUPLING DEVICE FOR USE IN OPTICAL WAVEGUIDES
19
Patent #:
Issue Dt:
12/25/2012
Application #:
12610090
Filing Dt:
10/30/2009
Publication #:
Pub Dt:
05/05/2011
Title:
METHOD AND APPARATUS FOR SELECTING PATHS FOR USE IN AT-SPEED TESTING
20
Patent #:
Issue Dt:
07/15/2014
Application #:
12610291
Filing Dt:
10/31/2009
Publication #:
Pub Dt:
05/05/2011
Title:
Yield Computation and Optimization for Selective Voltage Binning
21
Patent #:
Issue Dt:
04/26/2011
Application #:
12610563
Filing Dt:
11/02/2009
Publication #:
Pub Dt:
02/25/2010
Title:
METHOD OF FORMING A SEMICONDUCTOR STRUCTURE
22
Patent #:
Issue Dt:
01/15/2013
Application #:
12610630
Filing Dt:
11/02/2009
Publication #:
Pub Dt:
02/25/2010
Title:
SERIAL IRRADIATION OF A SUBSTRATE BY MULTIPLE RADIATION SOURCES
23
Patent #:
Issue Dt:
12/24/2013
Application #:
12611421
Filing Dt:
11/03/2009
Publication #:
Pub Dt:
05/05/2011
Title:
UTILIZATION OF ORGANIC BUFFER LAYER TO FABRICATE HIGH PERFORMANCE CARBON NANOELECTRONIC DEVICES
24
Patent #:
Issue Dt:
07/03/2012
Application #:
12611519
Filing Dt:
11/03/2009
Publication #:
Pub Dt:
02/25/2010
Title:
APPARATUS FOR THERMAL CHARACTERIZATION UNDER NON-UNIFORM HEAT LOAD
25
Patent #:
Issue Dt:
04/01/2014
Application #:
12611561
Filing Dt:
11/03/2009
Publication #:
Pub Dt:
05/05/2011
Title:
SYSTEMS AND METHODS FOR RESOURCE LEAK DETECTION
26
Patent #:
Issue Dt:
09/20/2011
Application #:
12611946
Filing Dt:
11/04/2009
Publication #:
Pub Dt:
05/05/2011
Title:
STRUCTURE AND METHOD TO FORM A THERMALLY STABLE SILICIDE IN NARROW DIMENSION GATE STACKS
27
Patent #:
Issue Dt:
08/20/2013
Application #:
12611947
Filing Dt:
11/04/2009
Publication #:
Pub Dt:
05/05/2011
Title:
ALIGNMENT METHOD FOR SEMICONDUCTOR PROCESSING
28
Patent #:
Issue Dt:
01/31/2012
Application #:
12612018
Filing Dt:
11/04/2009
Publication #:
Pub Dt:
05/05/2011
Title:
GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
29
Patent #:
Issue Dt:
03/25/2014
Application #:
12612035
Filing Dt:
11/04/2009
Publication #:
Pub Dt:
02/25/2010
Title:
ASYMMETRIC MULTI-GATED TRANSISTOR AND METHOD FOR FORMING
30
Patent #:
Issue Dt:
05/01/2012
Application #:
12612258
Filing Dt:
11/04/2009
Publication #:
Pub Dt:
05/05/2011
Title:
TEMPLATE-REGISTERED DIBLOCK COPOLYMER MASK FOR MRAM DEVICE FORMATION
31
Patent #:
Issue Dt:
06/02/2015
Application #:
12612624
Filing Dt:
11/04/2009
Publication #:
Pub Dt:
05/05/2011
Title:
SYSTEM AND METHOD FOR PROVIDING QUALITY-OF-SERVICES IN A MULTI-EVENT PROCESSING ENVIRONMENT
32
Patent #:
Issue Dt:
11/09/2010
Application #:
12612743
Filing Dt:
11/05/2009
Publication #:
Pub Dt:
02/25/2010
Title:
METHOD OF FABRICATING A HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR
33
Patent #:
Issue Dt:
08/02/2011
Application #:
12612957
Filing Dt:
11/05/2009
Publication #:
Pub Dt:
02/25/2010
Title:
DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
34
Patent #:
Issue Dt:
10/30/2012
Application #:
12613551
Filing Dt:
11/06/2009
Publication #:
Pub Dt:
05/12/2011
Title:
CAPPING OF COPPER INTERCONNECT LINES IN INTEGRATED CIRCUIT DEVICES
35
Patent #:
Issue Dt:
11/19/2013
Application #:
12613574
Filing Dt:
11/06/2009
Publication #:
Pub Dt:
05/12/2011
Title:
HYBRID DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH ENHANCED MOBILITY CHANNELS
36
Patent #:
Issue Dt:
12/04/2012
Application #:
12613800
Filing Dt:
11/06/2009
Publication #:
Pub Dt:
05/12/2011
Title:
BILAYER SYSTEMS INCLUDING A POLYDIMETHYLGLUTARIMIDE-BASED BOTTOM LAYER AND COMPOSITIONS THEREOF
37
Patent #:
Issue Dt:
09/11/2012
Application #:
12614224
Filing Dt:
11/06/2009
Publication #:
Pub Dt:
05/12/2011
Title:
AXIOCENTRIC SCRUBBING LAND GRID ARRAY CONTACTS AND METHODS FOR FABRICATION
38
Patent #:
Issue Dt:
02/24/2015
Application #:
12614231
Filing Dt:
11/06/2009
Publication #:
Pub Dt:
05/12/2011
Title:
METALLURGICAL CLAMSHELL METHODS FOR MICRO LAND GRID ARRAY FABRICATION
39
Patent #:
Issue Dt:
08/09/2011
Application #:
12614906
Filing Dt:
11/09/2009
Publication #:
Pub Dt:
05/12/2011
Title:
HIGH-K/METAL GATE CMOS FINFET WITH IMPROVED PFET THRESHOLD VOLTAGE
40
Patent #:
Issue Dt:
06/23/2015
Application #:
12615175
Filing Dt:
11/09/2009
Publication #:
Pub Dt:
05/12/2011
Title:
Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced Thereby
41
Patent #:
Issue Dt:
02/21/2012
Application #:
12615354
Filing Dt:
11/10/2009
Publication #:
Pub Dt:
05/12/2011
Title:
AIR GAP INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME
42
Patent #:
Issue Dt:
11/20/2012
Application #:
12615358
Filing Dt:
11/10/2009
Publication #:
Pub Dt:
05/12/2011
Title:
NONVOLATILE NANO-ELECTROMECHANICAL SYSTEM DEVICE
43
Patent #:
Issue Dt:
01/22/2013
Application #:
12615796
Filing Dt:
11/10/2009
Publication #:
Pub Dt:
05/12/2011
Title:
METAL CAPACITOR DESIGN FOR IMPROVED RELIABILITY AND GOOD ELECTRICAL CONNECTION
44
Patent #:
Issue Dt:
02/19/2013
Application #:
12615856
Filing Dt:
11/10/2009
Publication #:
Pub Dt:
05/12/2011
Title:
CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR
45
Patent #:
Issue Dt:
05/10/2011
Application #:
12616259
Filing Dt:
11/11/2009
Publication #:
Pub Dt:
05/12/2011
Title:
PROCESS FOR REVERSING TONE OF PATTERNS ON INTEGERATED CIRCUIT AND STRUCTURAL PROCESS FOR NANOSCALE FABRICATION
46
Patent #:
Issue Dt:
10/18/2011
Application #:
12616389
Filing Dt:
11/11/2009
Publication #:
Pub Dt:
05/12/2011
Title:
DAMASCENE GATE HAVING PROTECTED SHORTING REGIONS
47
Patent #:
Issue Dt:
08/28/2012
Application #:
12616534
Filing Dt:
11/11/2009
Publication #:
Pub Dt:
05/12/2011
Title:
METHODS AND SYSTEMS FOR VARIABLE GROUP SELECTION AND TEMPORAL CAUSAL MODELING
48
Patent #:
Issue Dt:
11/13/2012
Application #:
12616861
Filing Dt:
11/12/2009
Publication #:
Pub Dt:
05/12/2011
Title:
BI-DIRECTIONAL SELF-ALIGNED FET CAPACITOR
49
Patent #:
Issue Dt:
09/24/2013
Application #:
12616941
Filing Dt:
11/12/2009
Publication #:
Pub Dt:
05/12/2011
Title:
SINGLE METAL GATE CMOS INTEGRATION BY INTERMIXING POLARITY SPECIFIC CAPPING LAYERS
50
Patent #:
Issue Dt:
01/08/2013
Application #:
12616965
Filing Dt:
11/12/2009
Publication #:
Pub Dt:
05/12/2011
Title:
PIEZORESISTIVE STRAIN SENSOR BASED NANOWIRE MECHANICAL OSCILLATOR
51
Patent #:
Issue Dt:
09/10/2013
Application #:
12617084
Filing Dt:
11/12/2009
Publication #:
Pub Dt:
05/12/2011
Title:
BORDERLESS CONTACTS FOR SEMICONDUCTOR DEVICES
52
Patent #:
Issue Dt:
01/31/2012
Application #:
12617770
Filing Dt:
11/13/2009
Publication #:
Pub Dt:
05/19/2011
Title:
SELF-ALIGNED GRAPHENE TRANSISTOR
53
Patent #:
Issue Dt:
02/28/2012
Application #:
12618830
Filing Dt:
11/16/2009
Publication #:
Pub Dt:
05/19/2011
Title:
MIM CAPACITOR STRUCTURE IN FEOL AND RELATED METHOD
54
Patent #:
Issue Dt:
07/23/2013
Application #:
12618871
Filing Dt:
11/16/2009
Publication #:
Pub Dt:
05/19/2011
Title:
ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATHIN BOX
55
Patent #:
Issue Dt:
11/22/2011
Application #:
12618895
Filing Dt:
11/16/2009
Publication #:
Pub Dt:
05/19/2011
Title:
EMBEDDED PHOTODETECTOR APPARATUS IN A 3D CMOS CHIP STACK
56
Patent #:
Issue Dt:
09/25/2012
Application #:
12619209
Filing Dt:
11/16/2009
Publication #:
Pub Dt:
05/19/2011
Title:
CONTROL OF THRESHOLD VOLTAGES IN HIGH-K METAL GATE STACK AND STRUCTURES FOR CMOS DEVICES
57
Patent #:
Issue Dt:
06/28/2016
Application #:
12619285
Filing Dt:
11/16/2009
Publication #:
Pub Dt:
05/19/2011
Title:
SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE
58
Patent #:
Issue Dt:
01/28/2014
Application #:
12619298
Filing Dt:
11/16/2009
Publication #:
Pub Dt:
05/19/2011
Title:
METHODS FOR PHOTO-PATTERNABLE LOW-K (PPLK) INTEGRATION WITH CURING AFTER PATTERN TRANSFER
59
Patent #:
Issue Dt:
03/06/2012
Application #:
12619375
Filing Dt:
11/16/2009
Publication #:
Pub Dt:
05/19/2011
Title:
SELF-ALIGNED LOWER BOTTOM ELECTRODE
60
Patent #:
Issue Dt:
01/01/2013
Application #:
12619771
Filing Dt:
11/17/2009
Publication #:
Pub Dt:
05/19/2011
Title:
NON VOLATILE CELL AND ARCHITECTURE WITH SINGLE BIT RANDOM ACCESS READ, PROGRAM AND ERASE
61
Patent #:
Issue Dt:
07/29/2014
Application #:
12620083
Filing Dt:
11/17/2009
Publication #:
Pub Dt:
06/03/2010
Title:
MULTIPLE GATE TRANSISTOR HAVING HOMOGENOUSLY SILICIDED FIN END PORTIONS
62
Patent #:
Issue Dt:
11/06/2012
Application #:
12620234
Filing Dt:
11/17/2009
Publication #:
Pub Dt:
05/19/2011
Title:
STRUCTURE AND METHOD TO OBTAIN EOT SCALED DIELECTRIC STACKS
63
Patent #:
Issue Dt:
03/18/2014
Application #:
12620320
Filing Dt:
11/17/2009
Publication #:
Pub Dt:
05/19/2011
Title:
FABRICATION OF GRAPHENE NANOELECTRONIC DEVICES ON SOI STRUCTURES
64
Patent #:
Issue Dt:
04/12/2011
Application #:
12620629
Filing Dt:
11/18/2009
Publication #:
Pub Dt:
03/18/2010
Title:
SEMICONDUCTOR STRUCTURE INCLUDING MIXED RARE EARTH OXIDE FORMED ON SILICON
65
Patent #:
Issue Dt:
11/20/2012
Application #:
12620664
Filing Dt:
11/18/2009
Publication #:
Pub Dt:
06/03/2010
Title:
BUILT-IN COMPLIANCE IN TEST STRUCTURES FOR LEAKAGE AND DIELECTRIC BREAKDOWN OF DIELECTRIC MATERIALS OF METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES
66
Patent #:
Issue Dt:
03/27/2012
Application #:
12621000
Filing Dt:
11/18/2009
Publication #:
Pub Dt:
03/18/2010
Title:
PHASE CHANGE MEMORY CELL IN VIA ARRAY WITH SELF-ALIGNED, SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING
67
Patent #:
Issue Dt:
10/18/2011
Application #:
12621226
Filing Dt:
11/18/2009
Publication #:
Pub Dt:
09/02/2010
Title:
HOLEY ELECTRODE GRIDS FOR PHOTOVOLTAIC CELLS WITH SUBWAVELENGTH AND SUPERWAVELENGTH FEATURE SIZES
68
Patent #:
Issue Dt:
11/06/2012
Application #:
12621299
Filing Dt:
11/18/2009
Publication #:
Pub Dt:
05/19/2011
Title:
IMPLANT FREE EXTREMELY THIN SEMICONDUCTOR DEVICES
69
Patent #:
Issue Dt:
03/20/2012
Application #:
12621460
Filing Dt:
11/18/2009
Publication #:
Pub Dt:
05/19/2011
Title:
HYBRID FINFET/PLANAR SOI FETS
70
Patent #:
Issue Dt:
05/07/2013
Application #:
12621564
Filing Dt:
11/19/2009
Publication #:
Pub Dt:
10/21/2010
Title:
AUTOMATED GENERATION OF OXIDE PILLAR SLOT SHAPES IN SILICON-ON-INSULATOR FORMATION TECHNOLOGY
71
Patent #:
Issue Dt:
02/14/2012
Application #:
12621685
Filing Dt:
11/19/2009
Publication #:
Pub Dt:
09/02/2010
Title:
GRID-LINE-FREE CONTACT FOR A PHOTOVOLTAIC CELL
72
Patent #:
Issue Dt:
07/26/2011
Application #:
12621956
Filing Dt:
11/19/2009
Publication #:
Pub Dt:
05/19/2011
Title:
SEMISPHERICAL INTEGRATED CIRCUIT STRUCTURES
73
Patent #:
Issue Dt:
03/06/2012
Application #:
12622461
Filing Dt:
11/20/2009
Publication #:
Pub Dt:
10/14/2010
Title:
METHODS, PHOTOMASKS AND METHODS OF FABRICATING PHOTOMASKS FOR IMPROVING DAMASCENE WIRE UNIFORMITY WITHOUT REDUCING PERFORMANCE
74
Patent #:
Issue Dt:
10/30/2012
Application #:
12622464
Filing Dt:
11/20/2009
Publication #:
Pub Dt:
09/30/2010
Title:
METHODS FOR NORMALIZING STRAIN IN SEMICONDUCTOR DEVICES AND STRAIN NORMALIZED SEMICONDUCTOR DEVICES
75
Patent #:
Issue Dt:
09/27/2011
Application #:
12622504
Filing Dt:
11/20/2009
Publication #:
Pub Dt:
09/02/2010
Title:
SOLAR CONCENTRATION SYSTEM
76
Patent #:
Issue Dt:
07/31/2012
Application #:
12622557
Filing Dt:
11/20/2009
Publication #:
Pub Dt:
10/14/2010
Title:
SPACER LINEWIDTH CONTROL
77
Patent #:
Issue Dt:
09/25/2012
Application #:
12623462
Filing Dt:
11/23/2009
Publication #:
Pub Dt:
05/26/2011
Title:
POWER DELIVERY IN A HETEROGENEOUS 3-D STACKED APPARATUS
78
Patent #:
Issue Dt:
01/08/2013
Application #:
12623493
Filing Dt:
11/23/2009
Publication #:
Pub Dt:
06/03/2010
Title:
REDUCED TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF TWO DIFFERENT STRESS-INDUCING LAYERS IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE
79
Patent #:
Issue Dt:
05/15/2012
Application #:
12623836
Filing Dt:
11/23/2009
Publication #:
Pub Dt:
05/26/2011
Title:
OPTICAL ALIGNMENT MODULE UTILIZING TRANSPARENT RETICLE TO FACILITATE TOOL CALIBRATION DURING HIGH TEMPERATURE PROCESS
80
Patent #:
Issue Dt:
04/24/2012
Application #:
12624065
Filing Dt:
11/23/2009
Publication #:
Pub Dt:
03/18/2010
Title:
METHODS OF FORMING SOLDER CONNECTIONS AND STRUCTURE THEREOF
81
Patent #:
Issue Dt:
07/03/2012
Application #:
12624141
Filing Dt:
11/23/2009
Publication #:
Pub Dt:
05/26/2011
Title:
HIGH DENSITY LOW POWER NANOWIRE PHASE CHANGE MATERIAL MEMORY DEVICE
82
Patent #:
Issue Dt:
01/15/2013
Application #:
12624605
Filing Dt:
11/24/2009
Publication #:
Pub Dt:
05/26/2011
Title:
POLYMERIC FILMS MADE FROM POLYHEDRAL OLIGOMERIC SILSESQUIOXANE (POSS) AND A HYDROPHILIC COMONOMER
83
Patent #:
Issue Dt:
09/06/2011
Application #:
12624633
Filing Dt:
11/24/2009
Publication #:
Pub Dt:
05/26/2011
Title:
COMPOSITE MEMBRANES WITH PERFORMANCE ENHANCING LAYERS
84
Patent #:
Issue Dt:
03/20/2012
Application #:
12624677
Filing Dt:
11/24/2009
Publication #:
Pub Dt:
05/26/2011
Title:
FREQUENCY LOCKED FEEDBACK LOOP FOR WIRELESS COMMUNICATIONS
85
Patent #:
Issue Dt:
09/20/2011
Application #:
12625701
Filing Dt:
11/25/2009
Publication #:
Pub Dt:
05/26/2011
Title:
SIMULTANEOUSLY FORMED ISOLATION TRENCH AND THROUGH-BOX CONTACT FOR SILICON-ON-INSULATOR TECHNOLOGY
86
Patent #:
Issue Dt:
02/19/2013
Application #:
12625703
Filing Dt:
11/25/2009
Publication #:
Pub Dt:
05/26/2011
Title:
METHOD AND APPARATUS FOR INCREASED EFFECTIVENESS OF DELAY AND TRANSISTION FAULT TESTING
87
Patent #:
Issue Dt:
12/25/2012
Application #:
12625827
Filing Dt:
11/25/2009
Publication #:
Pub Dt:
05/26/2011
Title:
EMBEDDED STRESSOR FOR SEMICONDUCTOR STRUCTURES
88
Patent #:
Issue Dt:
05/17/2011
Application #:
12625855
Filing Dt:
11/25/2009
Publication #:
Pub Dt:
05/26/2011
Title:
SINGLE MASK ADDER PHASE CHANGE MEMORY ELEMENT
89
Patent #:
Issue Dt:
07/03/2012
Application #:
12627076
Filing Dt:
11/30/2009
Publication #:
Pub Dt:
06/02/2011
Title:
DOSIMETER POWERED BY PASSIVE RF ABSORPTION
90
Patent #:
Issue Dt:
09/23/2014
Application #:
12627120
Filing Dt:
11/30/2009
Publication #:
Pub Dt:
06/02/2011
Title:
SELF ALIGNED CARBIDE SOURCE/DRAIN FET
91
Patent #:
Issue Dt:
03/15/2011
Application #:
12627249
Filing Dt:
11/30/2009
Publication #:
Pub Dt:
03/25/2010
Title:
METHOD AND APPARATUS FOR FORMING PLANAR ALLOY DEPOSITS ON A SUBSTRATE
92
Patent #:
Issue Dt:
06/14/2011
Application #:
12627282
Filing Dt:
11/30/2009
Publication #:
Pub Dt:
06/02/2011
Title:
METHOD OF AND STRUCTURE FOR RECOVERING GAIN IN A BIPOLAR TRANSISTOR
93
Patent #:
Issue Dt:
06/25/2013
Application #:
12627343
Filing Dt:
11/30/2009
Publication #:
Pub Dt:
06/02/2011
Title:
SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE
94
Patent #:
Issue Dt:
08/30/2011
Application #:
12627424
Filing Dt:
11/30/2009
Publication #:
Pub Dt:
06/02/2011
Title:
EXTREMELY THIN SEMICONDUCTOR ON INSULATOR SEMICONDUCTOR DEVICE WITH SUPPRESSED DOPANT SEGREGATION
95
Patent #:
Issue Dt:
01/01/2013
Application #:
12627747
Filing Dt:
11/30/2009
Publication #:
Pub Dt:
06/02/2011
Title:
NANOPILLAR E-FUSE STRUCTURE AND PROCESS
96
Patent #:
Issue Dt:
09/20/2011
Application #:
12628663
Filing Dt:
12/01/2009
Publication #:
Pub Dt:
06/02/2011
Title:
METHOD AND STRUCTURE FOR FORMING FINFETS WITH MULTIPLE DOPING REGIONS ON A SAME CHIP
97
Patent #:
Issue Dt:
01/15/2013
Application #:
12628686
Filing Dt:
12/01/2009
Publication #:
Pub Dt:
06/02/2011
Title:
MULTIPLYING PATTERN DENSITY BY SINGLE SIDEWALL IMAGING TRANSFER
98
Patent #:
Issue Dt:
12/18/2012
Application #:
12629156
Filing Dt:
12/02/2009
Publication #:
Pub Dt:
06/02/2011
Title:
MODELING COMPLEX HIEARCHICAL SYSTEMS ACROSS SPACE AND TIME
99
Patent #:
Issue Dt:
03/27/2012
Application #:
12630939
Filing Dt:
12/04/2009
Publication #:
Pub Dt:
06/09/2011
Title:
OMEGA SHAPED NANOWIRE TUNNEL FIELD EFFECT TRANSISTORS FABRICATION
100
Patent #:
Issue Dt:
05/08/2012
Application #:
12630942
Filing Dt:
12/04/2009
Publication #:
Pub Dt:
06/09/2011
Title:
GATE-ALL-AROUND NANOWIRE TUNNEL FIELD EFFECT TRANSISTORS
Assignor
1
Exec Dt:
11/27/2018
Assignee
1
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

Search Results as of: 05/08/2024 11:36 AM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT