|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12630946
|
Filing Dt:
|
12/04/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
EVENT TRACKING HARDWARE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
12630993
|
Filing Dt:
|
12/04/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
HIGH-SPEED CERAMIC MODULES WITH HYBRID REFERENCING SCHEME FOR IMPROVED PERFORMANCE AND REDUCED COST
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
12631199
|
Filing Dt:
|
12/04/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
GATE-ALL-AROUND NANOWIRE FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2012
|
Application #:
|
12631203
|
Filing Dt:
|
12/04/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
NANOWIRE FET HAVING INDUCED RADIAL STRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2012
|
Application #:
|
12631205
|
Filing Dt:
|
12/04/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
OMEGA SHAPED NANOWIRE FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/17/2012
|
Application #:
|
12631213
|
Filing Dt:
|
12/04/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
SELF-ALIGNED CONTACTS FOR NANOWIRE FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2012
|
Application #:
|
12631218
|
Filing Dt:
|
12/04/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
NANOWIRE FET HAVING INDUCED RADIAL STRAIN
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12631310
|
Filing Dt:
|
12/04/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
RESISTIVE MEMORY DEVICES HAVING A NOT-AND (NAND) STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12631900
|
Filing Dt:
|
12/07/2009
|
Publication #:
|
|
Pub Dt:
|
04/01/2010
| | | | |
Title:
|
INTEGRATING NONVOLATILE MEMORY CAPABILITY WITHIN SRAM DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12632015
|
Filing Dt:
|
12/07/2009
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
ELECTRICAL OVERSTRESS PROTECTION CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2013
|
Application #:
|
12632030
|
Filing Dt:
|
12/07/2009
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
CHIP INDUCTOR WITH FREQUENCY DEPENDENT INDUCTANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12632040
|
Filing Dt:
|
12/07/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
MICRO-ELECTRO-MECHANICAL SYSTEM TILTABLE LENS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2012
|
Application #:
|
12632154
|
Filing Dt:
|
12/07/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
COUPLING PIEZOELECTRIC MATERIAL GENERATED STRESSES TO DEVICES FORMED IN INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2012
|
Application #:
|
12632351
|
Filing Dt:
|
12/07/2009
|
Publication #:
|
|
Pub Dt:
|
06/09/2011
| | | | |
Title:
|
NMOS ARCHITECTURE INVOLVING EPITAXIALLY-GROWN IN-SITU N-TYPE-DOPED EMBEDDED ESIGE:C SOURCE/DRAIN TARGETING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12632836
|
Filing Dt:
|
12/08/2009
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
HORIZONTAL MICRO-ELECTRO-MECHANICAL-SYSTEM SWITCH
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12632838
|
Filing Dt:
|
12/08/2009
|
Publication #:
|
|
Pub Dt:
|
10/21/2010
| | | | |
Title:
|
METAL FILL STRUCTURES FOR REDUCING PARASITIC CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
12634137
|
Filing Dt:
|
12/09/2009
|
Publication #:
|
|
Pub Dt:
|
04/08/2010
| | | | |
Title:
|
SEMICONDUCTOR DEVICE STRUCTURES WITH FLOATING BODY CHARGE STORAGE AND METHODS FOR FORMING SUCH SEMICONDUCTOR DEVICE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12634742
|
Filing Dt:
|
12/10/2009
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
INTERCONNECT STRUCTURES, METHODS FOR FABRICATING INTERCONNECT STRUCTURES, AND DESIGN STRUCTURES FOR A RADIOFREQUENCY INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2014
|
Application #:
|
12634893
|
Filing Dt:
|
12/10/2009
|
Publication #:
|
|
Pub Dt:
|
06/02/2011
| | | | |
Title:
|
SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12634898
|
Filing Dt:
|
12/10/2009
|
Publication #:
|
|
Pub Dt:
|
04/08/2010
| | | | |
Title:
|
CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/2010
|
Application #:
|
12635385
|
Filing Dt:
|
12/10/2009
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
Title:
|
DIRECT MEMORY ACCESS (DMA) ADDRESS TRANSLATION IN AN INPUT/OUTPUT MEMORY MANAGEMENT UNIT (IOMMU)
|
|
|
Patent #:
|
|
Issue Dt:
|
10/25/2011
|
Application #:
|
12635599
|
Filing Dt:
|
12/10/2009
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
IMPROVING DATA AVAILABILITY DURING FAILURE DETECTION AND RECOVERY PROCESSING IN A SHARED RESOURCE SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12636015
|
Filing Dt:
|
12/11/2009
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
REMOVAL OF MASKING MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/2015
|
Application #:
|
12636057
|
Filing Dt:
|
12/11/2009
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
ANALYZING COMPUTER PROGRAMS TO IDENTIFY ERRORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
12636426
|
Filing Dt:
|
12/11/2009
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
ISOLATION OF SINGLE-WALLED CARBON NANOTUBES FROM DOUBLE AND MULTI-WALLED CARBON NANOTUBES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
12637016
|
Filing Dt:
|
12/14/2009
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
Modeling for Soft Error Specification
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2014
|
Application #:
|
12637048
|
Filing Dt:
|
12/14/2009
|
Publication #:
|
|
Pub Dt:
|
04/15/2010
| | | | |
Title:
|
WAFER WITH DESIGN PRINTED OUTSIDE ACTIVE REGION AND SPACED BY DESIGN TOLERANCE OF RETICLE BLIND
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12638004
|
Filing Dt:
|
12/15/2009
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURE INCORPORATING MULTIPLE NITRIDE LAYERS TO IMPROVE THERMAL DISSIPATION AWAY FROM A DEVICE AND A METHOD OF FORMING THE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/27/2011
|
Application #:
|
12639454
|
Filing Dt:
|
12/16/2009
|
Publication #:
|
|
Pub Dt:
|
06/16/2011
| | | | |
Title:
|
LEAKAGE COMPENSATED REFERENCE VOLTAGE GENERATION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12640129
|
Filing Dt:
|
12/17/2009
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
PROPAGATING DESIGN TOLERANCES TO SHAPE TOLERANCES FOR LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2012
|
Application #:
|
12640444
|
Filing Dt:
|
12/17/2009
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
LOCAL SILICIDATION OF VIA BOTTOMS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12640752
|
Filing Dt:
|
12/17/2009
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
STRUCTURES AND METHODS TO REDUCE MAXIMUM CURRENT DENSITY IN A SOLDER BALL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/02/2014
|
Application #:
|
12641959
|
Filing Dt:
|
12/18/2009
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
METHODS OF DIRECTED SELF-ASSEMBLY AND LAYERED STRUCTURES FORMED THEREFROM
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/2014
|
Application #:
|
12642018
|
Filing Dt:
|
12/18/2009
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
METHODS OF DIRECTED SELF-ASSEMBLY, AND LAYERED STRUCTURES FORMED THEREFROM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/2014
|
Application #:
|
12642331
|
Filing Dt:
|
12/18/2009
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
METHOD OF MANUFACTURING SUPERCONDUCTING LOW PASS FILTER FOR QUANTUM COMPUTING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12642806
|
Filing Dt:
|
12/19/2009
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
SYSTEM TO IMPROVE CORELESS PACKAGE CONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12642989
|
Filing Dt:
|
12/21/2009
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
HEAT DISSIPATION IN TEMPERATURE CRITICAL DEVICE AREAS OF SEMICONDUCTOR DEVICES BY HEAT PIPES CONNECTING TO THE SUBSTRATE BACKSIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2012
|
Application #:
|
12643454
|
Filing Dt:
|
12/21/2009
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
SPIN-ON FORMULATION AND METHOD FOR STRIPPING AN ION IMPLANTED PHOTORESIST
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
12644895
|
Filing Dt:
|
12/22/2009
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
Title:
|
SEMICONDUCTOR SWITCHING DEVICE EMPLOYING A QUANTUM DOT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2012
|
Application #:
|
12644980
|
Filing Dt:
|
12/22/2009
|
Publication #:
|
|
Pub Dt:
|
06/23/2011
| | | | |
Title:
|
SIGNAL CONTROL ELEMENTS IN FERROMAGNETIC LOGIC
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2013
|
Application #:
|
12645583
|
Filing Dt:
|
12/23/2009
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
ELECTROCHEMICAL PLANARIZATION SYSTEM COMPRISING ENHANCED ELECTROLYTE FLOW
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12645981
|
Filing Dt:
|
12/23/2009
|
Publication #:
|
|
Pub Dt:
|
04/22/2010
| | | | |
Title:
|
SEMICONDUCTOR TRANSISTORS HAVING HIGH-K GATE DIELECTRIC LAYERS, METAL GATE ELECTRODE REGIONS, AND LOW FRINGING CAPACITANCES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/29/2011
|
Application #:
|
12646292
|
Filing Dt:
|
12/23/2009
|
Publication #:
|
|
Pub Dt:
|
04/22/2010
| | | | |
Title:
|
ON DEMAND CIRCUIT FUNCTION EXECUTION EMPLOYING OPTICAL SENSING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2015
|
Application #:
|
12647999
|
Filing Dt:
|
12/28/2009
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
ELECTROMIGRATION-RESISTANT UNDER-BUMP METALLIZATION OF NICKEL-IRON ALLOYS FOR SN-RICH SOLDER BUMPS IN PB-FREE FLIP-CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2013
|
Application #:
|
12648400
|
Filing Dt:
|
12/29/2009
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
ADJUSTING CONFIGURATION OF A MULTIPLE GATE TRANSISTOR BY CONTROLLING INDIVIDUAL FINS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12648442
|
Filing Dt:
|
12/29/2009
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
AUTOMATED RELATIONSHIP CLASSIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2012
|
Application #:
|
12648456
|
Filing Dt:
|
12/29/2009
|
Publication #:
|
|
Pub Dt:
|
06/30/2011
| | | | |
Title:
|
GENERATING CAPACITANCE LOOK-UP TABLES FOR WIRING PATTERNS IN THE PRESENCE OF METAL FILLS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
12648744
|
Filing Dt:
|
12/29/2009
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
ADJUSTING OF STRAIN CAUSED IN A TRANSISTOR CHANNEL BY SEMICONDUCTOR MATERIAL PROVIDED FOR THRESHOLD ADJUSTMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/25/2012
|
Application #:
|
12648867
|
Filing Dt:
|
12/29/2009
|
Publication #:
|
|
Pub Dt:
|
07/01/2010
| | | | |
Title:
|
TRANSISTOR DEVICE COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY HAVING AN ASYMMETRIC CONFIGURATION
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/2011
|
Application #:
|
12649199
|
Filing Dt:
|
12/29/2009
|
Publication #:
|
|
Pub Dt:
|
04/29/2010
| | | | |
Title:
|
PRODUCT-RELATED FEEDBACK FOR PROCESS CONTROL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2012
|
Application #:
|
12649391
|
Filing Dt:
|
12/30/2009
|
Publication #:
|
|
Pub Dt:
|
05/06/2010
| | | | |
Title:
|
OPTICAL INSPECTION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12651499
|
Filing Dt:
|
01/04/2010
|
Publication #:
|
|
Pub Dt:
|
04/29/2010
| | | | |
Title:
|
SOI FET WITH SOURCE-SIDE BODY DOPING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12651504
|
Filing Dt:
|
01/04/2010
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
ULTRA LOW-POWER CMOS BASED BIO-SENSOR CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2011
|
Application #:
|
12651608
|
Filing Dt:
|
01/04/2010
|
Publication #:
|
|
Pub Dt:
|
04/29/2010
| | | | |
Title:
|
TRENCH MEMORY WITH SELF-ALIGNED STRAP FORMED BY SELF-LIMITING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2012
|
Application #:
|
12651804
|
Filing Dt:
|
01/04/2010
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
MAGNETIC TUNNEL JUNCTION TRANSISTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2012
|
Application #:
|
12652338
|
Filing Dt:
|
01/05/2010
|
Publication #:
|
|
Pub Dt:
|
07/07/2011
| | | | |
Title:
|
TIMING POINT SELECTION FOR A STATIC TIMING ANALYSIS IN THE PRESENCE OF INTERCONNECT ELECTRICAL ELEMENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2011
|
Application #:
|
12652428
|
Filing Dt:
|
01/05/2010
|
Publication #:
|
|
Pub Dt:
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06/10/2010
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Title:
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METAL-GATED MOSFET DEVICES HAVING SCALED GATE STACK THICKNESS INCLUDING GETTERING SPECIES IN A BURIED OXIDE
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Patent #:
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Issue Dt:
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07/24/2012
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Application #:
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12652546
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Filing Dt:
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01/05/2010
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Publication #:
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Pub Dt:
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07/07/2011
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Title:
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ANALYZING ANTICIPATED VALUE AND EFFORT IN USING CLOUD COMPUTING TO PROCESS A SPECIFIED WORKLOAD
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Patent #:
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Issue Dt:
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08/08/2017
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Application #:
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12658615
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Filing Dt:
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02/08/2010
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Publication #:
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Pub Dt:
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11/25/2010
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Title:
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COATING COMPOSITIONS SUITABLE FOR USE WITH AN OVERCOATED PHOTORESIST
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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12674065
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Filing Dt:
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02/18/2010
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Publication #:
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Pub Dt:
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04/28/2011
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Title:
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APPARATUS FOR EXTERNALLY CHANGING THE DIRECTION OF AIR FLOWING THROUGH ELECTRONIC EQUIPMENT
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Patent #:
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Issue Dt:
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01/29/2013
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Application #:
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12678298
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Filing Dt:
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07/08/2010
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Publication #:
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Pub Dt:
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11/18/2010
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Title:
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INTEGRATED CIRCUIT STACK
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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12683080
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Filing Dt:
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01/06/2010
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Publication #:
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Pub Dt:
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07/07/2011
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Title:
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TUNNEL JUNCTION VIA
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Patent #:
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Issue Dt:
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07/31/2012
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Application #:
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12683456
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Filing Dt:
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01/07/2010
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Publication #:
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Pub Dt:
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07/07/2011
| | | | |
Title:
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BULK SUBSTRATE FET INTEGRATED ON CMOS SOI
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Patent #:
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Issue Dt:
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04/08/2014
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Application #:
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12683465
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Filing Dt:
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01/07/2010
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Publication #:
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Pub Dt:
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07/07/2011
| | | | |
Title:
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SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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04/17/2012
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Application #:
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12683535
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Filing Dt:
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01/07/2010
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Publication #:
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Pub Dt:
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05/06/2010
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Title:
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CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS
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Patent #:
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Issue Dt:
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04/23/2013
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Application #:
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12683606
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Filing Dt:
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01/07/2010
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Publication #:
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Pub Dt:
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07/07/2011
| | | | |
Title:
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BODY-TIED ASYMMETRIC P-TYPE FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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12683634
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Filing Dt:
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01/07/2010
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Publication #:
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Pub Dt:
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07/07/2011
| | | | |
Title:
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Body-Tied Asymmetric N-Type Field Effect Transistor
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Patent #:
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Issue Dt:
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07/24/2012
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Application #:
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12683720
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Filing Dt:
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01/07/2010
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Publication #:
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Pub Dt:
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07/07/2011
| | | | |
Title:
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METHOD AND SYSTEM FOR FEATURE FUNCTION AWARE PRIORITY PRINTING
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Patent #:
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Issue Dt:
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04/29/2014
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Application #:
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12683759
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Filing Dt:
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01/07/2010
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Publication #:
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Pub Dt:
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07/07/2011
| | | | |
Title:
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METHOD TO DYNAMICALLY TUNE PRECISION RESISTANCE
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Patent #:
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Issue Dt:
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12/06/2011
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Application #:
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12683770
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Filing Dt:
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01/07/2010
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Publication #:
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Pub Dt:
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07/07/2011
| | | | |
Title:
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LOW CAPACITANCE PRECISION RESISTOR
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Patent #:
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Issue Dt:
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09/18/2012
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Application #:
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12684174
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Filing Dt:
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01/08/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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PRECAST THERMAL INTERFACE ADHESIVE FOR EASY AND REPEATED, SEPARATION AND REMATING
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Patent #:
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Issue Dt:
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09/13/2011
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Application #:
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12684185
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Filing Dt:
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01/08/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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DEPOSITION OF AMORPHOUS PHASE CHANGE MATERIAL
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Patent #:
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Issue Dt:
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10/04/2011
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Application #:
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12684225
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Filing Dt:
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01/08/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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BACK-GATED FULLY DEPLETED SOI TRANSISTOR
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Patent #:
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Issue Dt:
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05/13/2014
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Application #:
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12684280
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Filing Dt:
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01/08/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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NANOWIRE PIN TUNNEL FIELD EFFECT DEVICES
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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12684372
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Filing Dt:
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01/08/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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OPTIMIZED FREE LAYER FOR SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12684510
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Filing Dt:
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01/08/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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READ DIRECTION FOR SPIN-TORQUE BASED MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/20/2011
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Application #:
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12684551
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Filing Dt:
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01/08/2010
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Publication #:
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Pub Dt:
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05/06/2010
| | | | |
Title:
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FABRICATING SEMICONDUCTOR STRUCTURES
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|
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Patent #:
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Issue Dt:
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07/30/2013
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Application #:
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12684697
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Filing Dt:
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01/08/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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METHOD OF FABRICATING MULTI-FINGERED SEMICONDUCTOR DEVICES ON A COMMON SUBSTRATE
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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12685022
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Filing Dt:
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01/11/2010
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Publication #:
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Pub Dt:
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08/05/2010
| | | | |
Title:
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METHOD AND SYSTEM FOR SEMICONDUCTOR PROCESS CONTROL AND MONITORING BY USING A DATA QUALITY METRIC
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Patent #:
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Issue Dt:
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04/26/2011
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Application #:
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12685027
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Filing Dt:
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01/11/2010
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Publication #:
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Pub Dt:
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05/06/2010
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE STRUCTURE
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Patent #:
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Issue Dt:
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04/19/2011
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Application #:
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12685054
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Filing Dt:
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01/11/2010
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Publication #:
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Pub Dt:
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05/06/2010
| | | | |
Title:
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METHOD AND STRUCTURE FOR FORMING STRAINED SI FOR CMOS DEVICES
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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12685156
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Filing Dt:
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01/11/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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DEEP TRENCH DECOUPLING CAPACITOR
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|
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Patent #:
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Issue Dt:
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05/22/2012
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Application #:
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12685393
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Filing Dt:
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01/11/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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METHOD AND SYSTEM FOR DETERMINING MANUFACTURING THROUGHPUT TARGET
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Patent #:
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Issue Dt:
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05/08/2012
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Application #:
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12685491
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Filing Dt:
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01/11/2010
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Publication #:
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Pub Dt:
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07/15/2010
| | | | |
Title:
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METHOD AND APPARATUS FOR SUB-PELLICLE DEFECT REDUCTION ON PHOTOMASKS
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12685734
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Filing Dt:
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01/12/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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NANOPOROUS SEMI-PERMEABLE MEMBRANE AND METHODS FOR FABRICATING THE SAME
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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12685938
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Filing Dt:
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01/12/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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Chemical-Mechanical Polishing Formulation and Methods of Use
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12686013
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Filing Dt:
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01/12/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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CHARGE PUMP SYSTEM AND METHOD UTILIZING ADJUSTABLE OUTPUT CHARGE AND COMPILATION SYSTEM AND METHOD FOR USE BY THE CHARGE PUMP
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Patent #:
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Issue Dt:
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04/17/2012
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Application #:
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12686403
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Filing Dt:
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01/13/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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METHOD AND STRUCTURE FOR FORMING CAPACITORS AND MEMORY DEVICES ON SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES
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Patent #:
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Issue Dt:
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10/15/2013
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Application #:
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12686457
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Filing Dt:
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01/13/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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METHOD OF MANAGING ELECTRO MIGRATION IN LOGIC DESIGNS AND DESIGN STRUCTURE THEREOF
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Patent #:
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Issue Dt:
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07/10/2012
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Application #:
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12687147
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Filing Dt:
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01/14/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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METHOD FOR CREATING ELECTRICALLY TESTABLE PATTERNS
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Patent #:
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Issue Dt:
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01/01/2013
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Application #:
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12687273
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Filing Dt:
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01/14/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT WITH ON-CHIP RESISTORS AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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02/12/2013
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Application #:
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12687607
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Filing Dt:
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01/14/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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SEMICONDUCTOR TRANSISTOR DEVICE STRUCTURE WITH BACK SIDE SOURCE/DRAIN CONTACT PLUGS, AND RELATED MANUFACTURING METHOD
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Patent #:
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Issue Dt:
|
10/23/2012
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Application #:
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12687610
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Filing Dt:
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01/14/2010
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Publication #:
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Pub Dt:
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07/14/2011
| | | | |
Title:
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SEMICONDUCTOR TRANSISTOR DEVICE STRUCTURE WITH BACK SIDE GATE CONTACT PLUGS, AND RELATED MANUFACTURING METHOD
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|
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Patent #:
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Issue Dt:
|
02/21/2012
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Application #:
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12688243
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Filing Dt:
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01/15/2010
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Publication #:
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Pub Dt:
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05/13/2010
| | | | |
Title:
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HIGH PERFORMANCE CAPACITORS IN PLANAR BACK GATES CMOS
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|
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Patent #:
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Issue Dt:
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09/17/2013
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Application #:
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12688254
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Filing Dt:
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01/15/2010
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Publication #:
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Pub Dt:
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05/13/2010
| | | | |
Title:
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METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES
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|
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Patent #:
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Issue Dt:
|
08/14/2012
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Application #:
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12688347
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Filing Dt:
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01/15/2010
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Publication #:
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Pub Dt:
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07/21/2011
| | | | |
Title:
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FINFET WITH THIN GATE DIELECTRIC LAYER
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|
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Patent #:
|
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Issue Dt:
|
02/15/2011
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Application #:
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12688470
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Filing Dt:
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01/15/2010
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Publication #:
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Pub Dt:
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05/13/2010
| | | | |
Title:
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SEMICONDUCTOR STRUCTURES INCORPORATING MULTIPLE CRYSTALLOGRAPHIC PLANES AND METHODS FOR FABRICATION THEREOF
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|
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Patent #:
|
|
Issue Dt:
|
07/17/2012
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Application #:
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12688471
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Filing Dt:
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01/15/2010
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Publication #:
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Pub Dt:
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07/21/2011
| | | | |
Title:
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CMOS CIRCUIT WITH LOW-K SPACER AND STRESS LINER
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|
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Patent #:
|
|
Issue Dt:
|
10/09/2012
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Application #:
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12688929
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Filing Dt:
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01/18/2010
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Publication #:
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Pub Dt:
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07/29/2010
| | | | |
Title:
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HIGH PERFORMANCE FLASH MEMORY DEVICES
|
|
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Patent #:
|
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Issue Dt:
|
01/29/2013
|
Application #:
|
12689268
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Filing Dt:
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01/19/2010
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Publication #:
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Pub Dt:
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07/21/2011
| | | | |
Title:
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METHOD AND STRUCTURE TO REDUCE SOFT ERROR RATE SUSCEPTIBILITY IN SEMICONDUCTOR STRUCTURES
|
|