|
|
Patent #:
|
|
Issue Dt:
|
08/16/2011
|
Application #:
|
12775084
|
Filing Dt:
|
05/06/2010
|
Publication #:
|
|
Pub Dt:
|
08/26/2010
| | | | |
Title:
|
OPTOELECTRONIC DEVICE WITH GERMANIUM PHOTODETECTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2012
|
Application #:
|
12775107
|
Filing Dt:
|
05/06/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
ENHANCING INVESTIGATION OF VARIABILITY BY INCLUSION OF SIMILAR OBJECTS WITH KNOWN DIFFERENCES TO THE ORIGINAL ONES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/15/2013
|
Application #:
|
12775532
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
ENHANCED CAPACITANCE DEEP TRENCH CAPACITOR FOR EDRAM
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
12775607
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
MINIMIZING MEMORY ARRAY REPRESENTATIONS FOR ENHANCED SYNTHESIS AND VERIFICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/18/2012
|
Application #:
|
12775622
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
ELIMINATING, COALESCING, OR BYPASSING PORTS IN MEMORY ARRAY REPRESENTATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12775863
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY AN IN SITU ETCH PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
12775939
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
METHOD AND STRUCTURE OF PHOTOVOLTAIC GRID STACKS BY SOLUTION BASED PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/08/2011
|
Application #:
|
12775970
|
Filing Dt:
|
05/07/2010
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
Title:
|
PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2013
|
Application #:
|
12776369
|
Filing Dt:
|
05/08/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
MOSFET GATE AND SOURCE/DRAIN CONTACT METALLIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12776444
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
MILLIMETER-WAVE SWITCHES AND ATTENUATORS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2013
|
Application #:
|
12776512
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
ENHANCING UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING STI STRUCTURES AFTER THE GROWTH PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2015
|
Application #:
|
12776674
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMATION IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12776742
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
REDUCED SILICON THICKNESS OF N-CHANNEL TRANSISTORS IN SOI CMOS DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2013
|
Application #:
|
12776829
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/10/2011
| | | | |
Title:
|
EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
12776861
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
12776879
|
Filing Dt:
|
05/10/2010
|
Publication #:
|
|
Pub Dt:
|
11/18/2010
| | | | |
Title:
|
SEMICONDUCTOR ELEMENT FORMED IN A CRYSTALLINE SUBSTRATE MATERIAL AND COMPRISING AN EMBEDDED IN SITU DOPED SEMICONDUCTOR MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
12777715
|
Filing Dt:
|
05/11/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
EFFECTIVE CYCLE TIME MANAGEMENT EMPLOYING A MULTI-HORIZON MODEL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12777881
|
Filing Dt:
|
05/11/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
TFET WITH NANOWIRE SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
12778130
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
CIRCUIT DEVICE WITH SIGNAL LINE TRANSITION ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12778315
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
NANOWIRE TUNNEL FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2013
|
Application #:
|
12778319
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
SEMICONDUCTOR STRUCTURES USING REPLACEMENT GATE AND METHODS OF MANUFACTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12778517
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
GENERATION OF MUTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2013
|
Application #:
|
12778526
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
GENERATION OF MULTIPLE DIAMETER NANOWIRE FIELD EFFECT TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/20/2014
|
Application #:
|
12778897
|
Filing Dt:
|
05/12/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
SELF ALIGNED FIN-TYPE PROGRAMMABLE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2014
|
Application #:
|
12779100
|
Filing Dt:
|
05/13/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED SOURCE AND DRAIN REGIONS OF CMOS TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2012
|
Application #:
|
12779608
|
Filing Dt:
|
05/13/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
SINGLE SUPPLY SUB VDD BITLINE PRECHARGE SRAM AND METHOD FOR LEVEL SHIFTING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/07/2011
|
Application #:
|
12780029
|
Filing Dt:
|
05/14/2010
|
Publication #:
|
|
Pub Dt:
|
12/23/2010
| | | | |
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/26/2013
|
Application #:
|
12780193
|
Filing Dt:
|
05/14/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
NON-UNIFORM GATE DIELECTRIC CHARGE FOR PIXEL SENSOR CELLS AND METHODS OF MANUFACTURING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2012
|
Application #:
|
12780962
|
Filing Dt:
|
05/17/2010
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
Title:
|
FORMATION OF RAISED SOURCE/DRAIN STRUCTURES IN NFET WITH EMBEDDED SIGE IN PFET
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2014
|
Application #:
|
12781514
|
Filing Dt:
|
05/17/2010
|
Publication #:
|
|
Pub Dt:
|
11/17/2011
| | | | |
Title:
|
FET Nanopore Sensor
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12781851
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
09/02/2010
| | | | |
Title:
|
REDUCING COUPLING BETWEEN WIRES OF AN ELECTRONIC CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2011
|
Application #:
|
12782320
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
BODY CONTACT STRUCTURES AND METHODS OF MANUFACTURING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12782359
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
METHOD AND SYSTEM TO OPTIMIZE SEMICONDUCTOR PRODUCTS FOR POWER, PERFORMANCE, NOISE, AND COST THROUGH USE OF VARIABLE POWER SUPPLY VOLTAGE COMPRESSION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/14/2011
|
Application #:
|
12782388
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
09/09/2010
| | | | |
Title:
|
PARTIALLY AND FULLY SILICIDED GATE STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12782407
|
Filing Dt:
|
05/18/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
EQUATION BASED RETARGETING OF DESIGN LAYOUTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12783676
|
Filing Dt:
|
05/20/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
GRAPHENE CHANNEL-BASED DEVICES AND METHODS FOR FABRICATION THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
02/25/2014
|
Application #:
|
12783787
|
Filing Dt:
|
05/20/2010
|
Publication #:
|
|
Pub Dt:
|
11/04/2010
| | | | |
Title:
|
ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/17/2015
|
Application #:
|
12783914
|
Filing Dt:
|
05/20/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
SHALLOW TRENCH ISOLATION EXTENSION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2013
|
Application #:
|
12784583
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
11/24/2011
| | | | |
Title:
|
ASYMMETRIC SILICON-ON-INSULATOR (SOI) JUNCTION FIELD EFFECT TRANSISTOR (JFET) AND A METHOD OF FORMING THE ASYMMETRICAL SOI JFET
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2012
|
Application #:
|
12784688
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
12/09/2010
| | | | |
Title:
|
THIN SUBSTRATE FABRICATION USING STRESS-INDUCED SUBSTRATE SPALLING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/22/2011
|
Application #:
|
12784819
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
STRAIN TRANSFORMATION IN BIAXIALLY STRAINED SOI SUBSTRATES FOR PERFORMANCE ENHANCEMENT OF P-CHANNEL AND N-CHANNEL TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2011
|
Application #:
|
12785007
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
ELECTRO-OPTICAL MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2012
|
Application #:
|
12785185
|
Filing Dt:
|
05/21/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
WORK FUNCTION ADJUSTMENT IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY SELECTIVELY REMOVING A BARRIER LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
05/17/2011
|
Application #:
|
12785435
|
Filing Dt:
|
05/22/2010
|
Publication #:
|
|
Pub Dt:
|
09/16/2010
| | | | |
Title:
|
METHOD TO IMPROVE REQUIREMENTS, DESIGN MANUFACTURING, AND TRANSPORTATION IN MASS MANUFACTURING INDUSTRIES THROUGH ANALYSIS OF DEFECT DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
10/09/2012
|
Application #:
|
12785849
|
Filing Dt:
|
05/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
ENHANCED ETCH STOP CAPABILITY DURING PATTERNING OF SILICON NITRIDE INCLUDING LAYER STACKS BY PROVIDING A CHEMICALLY FORMED OXIDE LAYER DURING SEMICONDUCTOR PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/01/2011
|
Application #:
|
12786019
|
Filing Dt:
|
05/24/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS FORMED BASED ON A SACRIFICIAL MATERIAL
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2012
|
Application #:
|
12786572
|
Filing Dt:
|
05/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
COMPUTING RESISTANCE SENSITIVITIES WITH RESPECT TO GEOMETRIC PARAMETERS OF CONDUCTORS WITH ARBITRARY SHAPES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2014
|
Application #:
|
12786956
|
Filing Dt:
|
05/25/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
ELECTRICALLY PROGRAMMABLE FLOATING COMMON GATE CMOS DEVICE AND APPLICATIONS THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
12787167
|
Filing Dt:
|
05/25/2010
|
Publication #:
|
|
Pub Dt:
|
09/16/2010
| | | | |
Title:
|
POWER MANAGEMENT ARCHITECTURE AND METHOD OF MODULATING OSCILLATOR FREQUENCY BASED ON VOLTAGE SUPPLY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12787417
|
Filing Dt:
|
05/26/2010
|
Publication #:
|
|
Pub Dt:
|
09/16/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR TONE INVERTING OF RESIDUAL LAYER TOLERANT IMPRINT LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2012
|
Application #:
|
12787429
|
Filing Dt:
|
05/26/2010
|
Publication #:
|
|
Pub Dt:
|
09/16/2010
| | | | |
Title:
|
METHOD AND SYSTEM FOR TONE INVERTING OF RESIDUAL LAYER TOLERANT IMPRINT LITHOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12787461
|
Filing Dt:
|
05/26/2010
|
Publication #:
|
|
Pub Dt:
|
12/30/2010
| | | | |
Title:
|
UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2012
|
Application #:
|
12788411
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
IMPLEMENTING LOW POWER DATA PREDICTING LOCAL EVALUATION FOR DOUBLE PUMPED ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2011
|
Application #:
|
12788486
|
Filing Dt:
|
05/27/2010
|
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2011
|
Application #:
|
12788521
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
09/16/2010
| | | | |
Title:
|
SEMICONDUCTOR CHIPS WITH CRACK STOP REGIONS FOR REDUCING CRACK PROPAGATION FROM CHIP EDGES/CORNERS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/25/2014
|
Application #:
|
12788839
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
Laser Ablation of Adhesive for Integrated Circuit Fabrication
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2013
|
Application #:
|
12788910
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
Differential Cross-Coupled Power Combiner or Divider
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2013
|
Application #:
|
12788987
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
SELF-ADJUSTING CRITICAL PATH TIMING OF MULTI-CORE VLSI CHIP
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12789013
|
Filing Dt:
|
05/27/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
INTEGRATED CIRCUIT WITH FINFETS AND MIM FIN CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2011
|
Application #:
|
12789505
|
Filing Dt:
|
05/28/2010
|
Publication #:
|
|
Pub Dt:
|
11/25/2010
| | | | |
Title:
|
COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2012
|
Application #:
|
12789839
|
Filing Dt:
|
05/28/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/16/2014
|
Application #:
|
12791372
|
Filing Dt:
|
06/01/2010
|
Publication #:
|
|
Pub Dt:
|
12/01/2011
| | | | |
Title:
|
REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
12791942
|
Filing Dt:
|
06/02/2010
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
FORMATION OF MASKS/RETICLES HAVING DUMMY FEATURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12792242
|
Filing Dt:
|
06/02/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
INTERFACE STRUCTURE FOR CHANNEL MOBILITY IMPROVEMENT IN HIGH-K METAL GATE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
10/11/2011
|
Application #:
|
12792837
|
Filing Dt:
|
06/03/2010
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
NEUTRALIZATION OF TRAPPED CHARGE IN A CHARGE ACCUMULATION LAYER OF A SEMICONDUCTOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2013
|
Application #:
|
12793046
|
Filing Dt:
|
06/03/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
CONTACT RESISTIVITY REDUCTION IN TRANSISTOR DEVICES BY DEEP LEVEL IMPURITY FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/14/2014
|
Application #:
|
12793292
|
Filing Dt:
|
06/03/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
FINFET-COMPATIBLE METAL-INSULATOR-METAL CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2012
|
Application #:
|
12793896
|
Filing Dt:
|
06/04/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
VARIABLE FLOW COMPUTER COOLING SYSTEM FOR A DATA CENTER AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/23/2011
|
Application #:
|
12793905
|
Filing Dt:
|
06/04/2010
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
VARIABLE FLOW COMPUTER COOLING SYSTEM FOR A DATA CENTER AND METHOD OF OPERATION
|
|
|
Patent #:
|
|
Issue Dt:
|
02/28/2012
|
Application #:
|
12794208
|
Filing Dt:
|
06/04/2010
|
Publication #:
|
|
Pub Dt:
|
09/23/2010
| | | | |
Title:
|
METHOD FOR USING COMPOSITIONS CONTAINING FLUOROCARBINOLS IN LITHOGRAPHIC PROCESSES
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2014
|
Application #:
|
12794995
|
Filing Dt:
|
06/07/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
LOW VOLTAGE SIGNALING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/02/2011
|
Application #:
|
12795108
|
Filing Dt:
|
06/07/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
METHODS OF FORMING A HYPER-ABRUPT P-N JUNCTION AND DESIGN STRUCTURES FOR AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2013
|
Application #:
|
12795962
|
Filing Dt:
|
06/08/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2013
|
Application #:
|
12795973
|
Filing Dt:
|
06/08/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
REPLACEMENT GATE MOSFET WITH SELF-ALIGNED DIFFUSION CONTACT
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2013
|
Application #:
|
12796501
|
Filing Dt:
|
06/08/2010
|
Publication #:
|
|
Pub Dt:
|
12/08/2011
| | | | |
Title:
|
DETAILED ROUTABILITY BY CELL PLACEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2012
|
Application #:
|
12797181
|
Filing Dt:
|
06/09/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
MEMORY TESTING SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2013
|
Application #:
|
12797420
|
Filing Dt:
|
06/09/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12813491
|
Filing Dt:
|
06/10/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
DETECTION AND CORRECTION OF DROPPED WRITE ERRORS IN A DATA STORAGE SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12813598
|
Filing Dt:
|
06/11/2010
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12813828
|
Filing Dt:
|
06/11/2010
|
Publication #:
|
|
Pub Dt:
|
03/17/2011
| | | | |
Title:
|
PHASE AND FREQUENCY DETECTOR WITH OUTPUT PROPORTIONAL TO FREQUENCY DIFFERENCE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
12814346
|
Filing Dt:
|
06/11/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12814930
|
Filing Dt:
|
06/14/2010
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12814942
|
Filing Dt:
|
06/14/2010
|
Publication #:
|
|
Pub Dt:
|
12/02/2010
| | | | |
Title:
|
MOSFET STRUCTURE WITH MULTIPLE SELF-ALIGNED SILICIDE CONTACTS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/27/2011
|
Application #:
|
12815129
|
Filing Dt:
|
06/14/2010
|
Publication #:
|
|
Pub Dt:
|
09/30/2010
| | | | |
Title:
|
METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/05/2013
|
Application #:
|
12815845
|
Filing Dt:
|
06/15/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
FINFET DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2012
|
Application #:
|
12815902
|
Filing Dt:
|
06/15/2010
|
Publication #:
|
|
Pub Dt:
|
12/15/2011
| | | | |
Title:
|
FABRICATION OF A VERTICAL HETEROJUNCTION TUNNEL-FET
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2013
|
Application #:
|
12816399
|
Filing Dt:
|
06/16/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2013
|
Application #:
|
12816605
|
Filing Dt:
|
06/16/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
Gate-Last Fabrication of Quarter-Gap MGHK FET
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2013
|
Application #:
|
12816697
|
Filing Dt:
|
06/16/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
FIELD EFFECTS TRANSISTOR WITH ASYMMETRIC ABRUPT JUNCTION IMPLANT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2012
|
Application #:
|
12816825
|
Filing Dt:
|
06/16/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
DIFFERENTIALLY RECESSED CONTACTS FOR MULTI-GATE TRANSISTOR OF SRAM CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/26/2013
|
Application #:
|
12817249
|
Filing Dt:
|
06/17/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2013
|
Application #:
|
12818828
|
Filing Dt:
|
06/18/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
INTERFACE-FREE METAL GATE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/2011
|
Application #:
|
12819228
|
Filing Dt:
|
06/21/2010
|
Publication #:
|
|
Pub Dt:
|
10/14/2010
| | | | |
Title:
|
LATERAL JUNCTION VARACTOR WITH LARGE TUNING RANGE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2013
|
Application #:
|
12819440
|
Filing Dt:
|
06/21/2010
|
Publication #:
|
|
Pub Dt:
|
12/22/2011
| | | | |
Title:
|
SEMICONDUCTOR DEVICES FABRICATED BY DOPED MATERIAL LAYER AS DOPANT SOURCE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2012
|
Application #:
|
12819721
|
Filing Dt:
|
06/21/2010
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
PHASE CHANGE MATERIAL BASED TEMPERATURE SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/15/2011
|
Application #:
|
12819786
|
Filing Dt:
|
06/21/2010
|
Publication #:
|
|
Pub Dt:
|
10/07/2010
| | | | |
Title:
|
CONSTRAINT PROGRAMMING FOR REDUCTION OF SYSTEM TEST-CONFIGURATION-MATRIX COMPLEXITY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2013
|
Application #:
|
12821507
|
Filing Dt:
|
06/23/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
SHORT CHANNEL SEMICONDUCTOR DEVICES WITH REDUCED HALO DIFFUSION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2012
|
Application #:
|
12821526
|
Filing Dt:
|
06/23/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
PHASE LOCKED LOOP WITH STARTUP OSCILLATOR AND PRIMARY OSCILLATOR
|
|
|
Patent #:
|
|
Issue Dt:
|
07/19/2011
|
Application #:
|
12821583
|
Filing Dt:
|
06/23/2010
|
Publication #:
|
|
Pub Dt:
|
12/30/2010
| | | | |
Title:
|
ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING A HARD MASK FOR OFFSET SPACER PATTERNING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2013
|
Application #:
|
12821953
|
Filing Dt:
|
06/23/2010
|
Publication #:
|
|
Pub Dt:
|
12/29/2011
| | | | |
Title:
|
METHOD OF PURIFYING NANOPARTICLES IN A COLLOID
|
|