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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
1
Patent #:
Issue Dt:
04/02/2013
Application #:
13243605
Filing Dt:
09/23/2011
Publication #:
Pub Dt:
03/28/2013
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUIT SYSTEMS INCLUDING HIGH RELIABILITY DIE UNDER-FILL
2
Patent #:
Issue Dt:
07/22/2014
Application #:
13244426
Filing Dt:
09/24/2011
Publication #:
Pub Dt:
03/28/2013
Title:
RETICLE DEFECT CORRECTION BY SECOND EXPOSURE
3
Patent #:
Issue Dt:
05/15/2012
Application #:
13244998
Filing Dt:
09/26/2011
Publication #:
Pub Dt:
01/19/2012
Title:
ON-CHIP EMBEDDED THERMAL ANTENNA FOR CHIP COOLING
4
Patent #:
Issue Dt:
01/28/2014
Application #:
13246037
Filing Dt:
09/27/2011
Publication #:
Pub Dt:
03/28/2013
Title:
PROGRAMMABLE GATE ARRAY AS DRIVERS FOR DATA PORTS OF SPARE LATCHES
5
Patent #:
Issue Dt:
10/16/2012
Application #:
13246175
Filing Dt:
09/27/2011
Publication #:
Pub Dt:
07/05/2012
Title:
ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD
6
Patent #:
Issue Dt:
02/11/2014
Application #:
13246904
Filing Dt:
09/28/2011
Publication #:
Pub Dt:
03/28/2013
Title:
SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING ENHANCED PERFORMANCE AND RELIABILITY
7
Patent #:
Issue Dt:
12/31/2013
Application #:
13247763
Filing Dt:
09/28/2011
Publication #:
Pub Dt:
03/28/2013
Title:
SEMICONDUCTOR DEVICE FABRICATION METHODS WITH ENHANCED CONTROL IN RECESSING PROCESSES
8
Patent #:
Issue Dt:
07/23/2013
Application #:
13248792
Filing Dt:
09/29/2011
Publication #:
Pub Dt:
04/04/2013
Title:
HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE
9
Patent #:
Issue Dt:
02/11/2014
Application #:
13251660
Filing Dt:
10/03/2011
Publication #:
Pub Dt:
04/04/2013
Title:
STRUCTURE AND METHOD TO FORM PASSIVE DEVICES IN ETSOI PROCESS FLOW
10
Patent #:
Issue Dt:
05/07/2013
Application #:
13251757
Filing Dt:
10/03/2011
Publication #:
Pub Dt:
04/04/2013
Title:
SEMICONDUCTOR DEVICES WITH RAISED EXTENSIONS
11
Patent #:
Issue Dt:
08/07/2012
Application #:
13252152
Filing Dt:
10/03/2011
Publication #:
Pub Dt:
01/26/2012
Title:
POLYSILICON PLUG BIPOLAR TRANSISTOR FOR PHASE CHANGE MEMORY
12
Patent #:
Issue Dt:
09/16/2014
Application #:
13252366
Filing Dt:
10/04/2011
Publication #:
Pub Dt:
04/04/2013
Title:
FUSE FOR THREE DIMENSIONAL SOLID-STATE BATTERY
13
Patent #:
Issue Dt:
07/23/2013
Application #:
13252424
Filing Dt:
10/04/2011
Publication #:
Pub Dt:
01/26/2012
Title:
NOVEL REWORKABLE UNDERFILLS FOR CERAMIC MCM C4 PROTECTION
14
Patent #:
Issue Dt:
11/12/2013
Application #:
13252868
Filing Dt:
10/04/2011
Publication #:
Pub Dt:
04/04/2013
Title:
EVALUATING ROUTING CONGESTION BASED ON AVERAGE GLOBAL EDGE CONGESTION HISTOGRAMS
15
Patent #:
Issue Dt:
07/15/2014
Application #:
13253260
Filing Dt:
10/05/2011
Publication #:
Pub Dt:
04/11/2013
Title:
Low Phase Variation CMOS Digital Attenuator
16
Patent #:
Issue Dt:
10/07/2014
Application #:
13253375
Filing Dt:
10/05/2011
Publication #:
Pub Dt:
04/11/2013
Title:
TUCKED ACTIVE REGION WITHOUT DUMMY POLY FOR PERFORMANCE BOOST AND VARIATION REDUCTION
17
Patent #:
Issue Dt:
03/18/2014
Application #:
13267198
Filing Dt:
10/06/2011
Publication #:
Pub Dt:
04/11/2013
Title:
SIDEWALL IMAGE TRANSFER PROCESS WITH MULTIPLE CRITICAL DIMENSIONS
18
Patent #:
Issue Dt:
11/12/2013
Application #:
13267739
Filing Dt:
10/06/2011
Publication #:
Pub Dt:
04/11/2013
Title:
MOSFET INTEGRATED CIRCUIT HAVING DOPED CONDUCTIVE INTERCONNECTS AND METHODS FOR ITS MANUFACTURE
19
Patent #:
Issue Dt:
04/07/2015
Application #:
13269552
Filing Dt:
10/07/2011
Publication #:
Pub Dt:
04/11/2013
Title:
LATERAL ETCH STOP FOR NEMS RELEASE ETCH FOR HIGH DENSITY NEMS/CMOS MONOLITHIC INTEGRATION
20
Patent #:
Issue Dt:
06/02/2015
Application #:
13269830
Filing Dt:
10/10/2011
Publication #:
Pub Dt:
04/11/2013
Title:
DETERMINATION OF SERIES RESISTANCE OF AN ARRAY OF CAPACITIVE ELEMENTS
21
Patent #:
Issue Dt:
11/26/2013
Application #:
13269942
Filing Dt:
10/10/2011
Publication #:
Pub Dt:
04/11/2013
Title:
ASYMMETRIC MEMORY CELLS
22
Patent #:
Issue Dt:
04/22/2014
Application #:
13269955
Filing Dt:
10/10/2011
Publication #:
Pub Dt:
04/11/2013
Title:
EMBEDED DRAM CELL STRUCTURES WITH HIGH CONDUCTANCE ELECTRODES AND METHODS OF MANUFACTURE
23
Patent #:
Issue Dt:
04/28/2015
Application #:
13270047
Filing Dt:
10/10/2011
Publication #:
Pub Dt:
04/11/2013
Title:
BORDERLESS SELF-ALIGNED METAL CONTACT PATTERNING USING PRINTABLE DIELECTRIC MATERIALS
24
Patent #:
Issue Dt:
05/20/2014
Application #:
13270649
Filing Dt:
10/11/2011
Publication #:
Pub Dt:
04/11/2013
Title:
USER-COORDINATED RESOURCE RECOVERY
25
Patent #:
Issue Dt:
07/01/2014
Application #:
13271796
Filing Dt:
10/12/2011
Publication #:
Pub Dt:
04/18/2013
Title:
MULTI-BIT SPIN-MOMENTUM-TRANSFER MAGNETORESISTENCE RANDOM ACCESS MEMORY WITH SINGLE MAGNETIC-TUNNEL-JUNCTION STACK
26
Patent #:
Issue Dt:
10/01/2013
Application #:
13272340
Filing Dt:
10/13/2011
Publication #:
Pub Dt:
04/18/2013
Title:
REDUCING PERFORMANCE VARIATION OF NARROW CHANNEL DEVICES
27
Patent #:
Issue Dt:
01/26/2016
Application #:
13272395
Filing Dt:
10/13/2011
Publication #:
Pub Dt:
07/23/2015
Title:
METHOD, STRUCTURES AND METHOD OF DESIGNING REDUCED DELAMINATION INTEGRATED CIRCUITS
28
Patent #:
Issue Dt:
01/28/2014
Application #:
13272409
Filing Dt:
10/13/2011
Publication #:
Pub Dt:
04/18/2013
Title:
FINFET PARASITIC CAPACITANCE REDUCTION USING AIR GAP
29
Patent #:
Issue Dt:
04/01/2014
Application #:
13272485
Filing Dt:
10/13/2011
Publication #:
Pub Dt:
04/18/2013
Title:
SEMICONDUCTOR TRENCH INDUCTORS AND TRANSFORMERS
30
Patent #:
Issue Dt:
03/18/2014
Application #:
13274389
Filing Dt:
10/17/2011
Publication #:
Pub Dt:
04/18/2013
Title:
ARRAY AND MOAT ISOLATION STRUCTURES AND METHOD OF MANUFACTURE
31
Patent #:
Issue Dt:
06/14/2016
Application #:
13274758
Filing Dt:
10/17/2011
Publication #:
Pub Dt:
04/18/2013
Title:
REPLACEMENT GATE MULTIGATE TRANSISTOR FOR EMBEDDED DRAM
32
Patent #:
Issue Dt:
10/16/2012
Application #:
13275441
Filing Dt:
10/18/2011
Publication #:
Pub Dt:
02/09/2012
Title:
METHOD FOR HIGH DENSITY DATA STORAGE AND IMAGING
33
Patent #:
Issue Dt:
05/14/2013
Application #:
13275766
Filing Dt:
10/18/2011
Publication #:
Pub Dt:
04/18/2013
Title:
METHODS OF FORMING HIGHLY SCALED SEMICONDUCTOR DEVICES USING A DISPOSABLE SPACER TECHNIQUE
34
Patent #:
Issue Dt:
12/23/2014
Application #:
13275936
Filing Dt:
10/18/2011
Publication #:
Pub Dt:
04/18/2013
Title:
PHOTOVOLTAIC DEVICE USING NANO-SPHERES FOR TEXTURED ELECTRODES
35
Patent #:
Issue Dt:
07/08/2014
Application #:
13276395
Filing Dt:
10/19/2011
Publication #:
Pub Dt:
04/25/2013
Title:
FINFET STRUCTURE AND METHOD TO ADJUST THRESHOLD VOLTAGE IN A FINFET STRUCTURE
36
Patent #:
Issue Dt:
07/22/2014
Application #:
13277259
Filing Dt:
10/20/2011
Publication #:
Pub Dt:
04/25/2013
Title:
POST-GATE SHALLOW TRENCH ISOLATION STRUCTURE FORMATION
37
Patent #:
Issue Dt:
02/04/2014
Application #:
13277265
Filing Dt:
10/20/2011
Publication #:
Pub Dt:
02/09/2012
Title:
ON-CHIP MILLIMETER WAVE LANGE COUPLER
38
Patent #:
Issue Dt:
12/03/2013
Application #:
13277767
Filing Dt:
10/20/2011
Publication #:
Pub Dt:
02/21/2013
Title:
METHOD TO REORDER (SHUFFLE) OPTICAL CABLE WAVEGUIDE LAYERS
39
Patent #:
Issue Dt:
04/16/2013
Application #:
13277956
Filing Dt:
10/20/2011
Publication #:
Pub Dt:
04/25/2013
Title:
BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION
40
Patent #:
Issue Dt:
12/18/2012
Application #:
13278010
Filing Dt:
10/20/2011
Publication #:
Pub Dt:
02/16/2012
Title:
METHODS FOR FORMING ISOLATED FIN STRUCTURES ON BULK SEMICONDUCTOR MATERIAL
41
Patent #:
Issue Dt:
10/15/2013
Application #:
13278301
Filing Dt:
10/21/2011
Publication #:
Pub Dt:
04/25/2013
Title:
METHOD FOR CONTROLLING STRUCTURE HEIGHT
42
Patent #:
Issue Dt:
01/14/2014
Application #:
13278552
Filing Dt:
10/21/2011
Publication #:
Pub Dt:
04/25/2013
Title:
CARBON NANOTUBE TRANSISTOR EMPLOYING EMBEDDED ELECTRODES
43
Patent #:
Issue Dt:
09/29/2015
Application #:
13279687
Filing Dt:
10/24/2011
Publication #:
Pub Dt:
04/25/2013
Title:
STACKED POWER SUPPLIES FOR INTEGRATED CIRCUIT DEVICES AND METHODS OF MAKING SAME
44
Patent #:
Issue Dt:
09/24/2013
Application #:
13280146
Filing Dt:
10/24/2011
Publication #:
Pub Dt:
05/03/2012
Title:
CONSTRAINT OPTIMIZATION OF SUB-NET LEVEL ROUTING IN ASIC DESIGN
45
Patent #:
Issue Dt:
01/03/2017
Application #:
13280178
Filing Dt:
10/24/2011
Publication #:
Pub Dt:
02/23/2012
Title:
METHOD, SYSTEM AND APPARATUS FOR AUTOMATED TERMINATION OF A THERAPY FOR AN EPILEPTIC EVENT UPON A DETERMINATION OF EFFECTS OF A THERAPY
46
Patent #:
Issue Dt:
07/15/2014
Application #:
13280666
Filing Dt:
10/25/2011
Publication #:
Pub Dt:
04/25/2013
Title:
METHODOLOGY AND APPARATUS FOR TUNING DRIVING CURRENT OF SEMICONDUCTOR TRANSISTORS
47
Patent #:
Issue Dt:
06/10/2014
Application #:
13280681
Filing Dt:
11/28/2011
Publication #:
Pub Dt:
05/30/2013
Title:
NOBLE GAS IMPLANTATION REGION IN TOP SILICON LAYER OF SEMICONDUCTOR-ON-INSULATOR SUBSTRATE
48
Patent #:
Issue Dt:
07/16/2013
Application #:
13280853
Filing Dt:
10/25/2011
Publication #:
Pub Dt:
05/03/2012
Title:
METHOD AND APPARATUS FOR TRACKING UNCERTAIN SIGNALS
49
Patent #:
Issue Dt:
11/12/2013
Application #:
13280881
Filing Dt:
10/25/2011
Publication #:
Pub Dt:
04/25/2013
Title:
METHODS OF FORMING BUMP STRUCTURES THAT INCLUDE A PROTECTION LAYER
50
Patent #:
Issue Dt:
03/18/2014
Application #:
13281105
Filing Dt:
10/25/2011
Publication #:
Pub Dt:
04/25/2013
Title:
METHODS OF FORMING CONDUCTIVE STRUCTURES IN DIELECTRIC LAYERS ON AN INTEGRATED CIRCUIT DEVICE
51
Patent #:
Issue Dt:
11/05/2013
Application #:
13281236
Filing Dt:
10/25/2011
Publication #:
Pub Dt:
04/25/2013
Title:
REPLACEMENT GATE FABRICATION METHODS
52
Patent #:
Issue Dt:
07/29/2014
Application #:
13281552
Filing Dt:
10/26/2011
Publication #:
Pub Dt:
05/02/2013
Title:
METHODS OF FORMING CONDUCTIVE STRUCTURES USING A SPACER EROSION TECHNIQUE
53
Patent #:
Issue Dt:
07/01/2014
Application #:
13281688
Filing Dt:
10/26/2011
Publication #:
Pub Dt:
05/02/2013
Title:
HIGH SELECTIVITY NITRIDE ETCH PROCESS
54
Patent #:
Issue Dt:
02/18/2014
Application #:
13281715
Filing Dt:
10/26/2011
Publication #:
Pub Dt:
05/02/2013
Title:
HIGH ASPECT RATIO AND REDUCED UNDERCUT TRENCH ETCH PROCESS FOR A SEMICONDUCTOR SUBSTRATE
55
Patent #:
Issue Dt:
11/17/2015
Application #:
13281732
Filing Dt:
10/26/2011
Publication #:
Pub Dt:
05/02/2013
Title:
LOW ENERGY ETCH PROCESS FOR NITROGEN-CONTAINING DIELECTRIC LAYER
56
Patent #:
Issue Dt:
12/23/2014
Application #:
13281749
Filing Dt:
10/26/2011
Publication #:
Pub Dt:
05/02/2013
Title:
HIGH FIDELITY PATTERNING EMPLOYING A FLUOROHYDROCARBON-CONTAINING POLYMER
57
Patent #:
Issue Dt:
10/07/2014
Application #:
13282224
Filing Dt:
10/26/2011
Publication #:
Pub Dt:
02/16/2012
Title:
LOW CAPACITANCE PRECISION RESISTOR
58
Patent #:
Issue Dt:
06/02/2015
Application #:
13282261
Filing Dt:
10/26/2011
Publication #:
Pub Dt:
05/02/2013
Title:
SRAM CELL WITH INDIVIDUAL ELECTRICAL DEVICE THRESHOLD CONTROL
59
Patent #:
Issue Dt:
05/12/2015
Application #:
13282299
Filing Dt:
10/26/2011
Publication #:
Pub Dt:
05/02/2013
Title:
SRAM CELL WITH INDIVIDUAL ELECTRICAL DEVICE THRESHOLD CONTROL
60
Patent #:
Issue Dt:
03/12/2013
Application #:
13283031
Filing Dt:
10/27/2011
Title:
ISOLATION IN CMOSFET DEVICES UTILIZING BURIED AIR BAGS
61
Patent #:
Issue Dt:
06/16/2015
Application #:
13283305
Filing Dt:
10/27/2011
Publication #:
Pub Dt:
05/02/2013
Title:
DETECTION OF UNCHECKED SIGNALS IN CIRCUIT DESIGN VERIFICATION
62
Patent #:
Issue Dt:
11/05/2013
Application #:
13283308
Filing Dt:
10/27/2011
Publication #:
Pub Dt:
05/02/2013
Title:
MOSFET WITH THIN SEMICONDUCTOR CHANNEL AND EMBEDDED STRESSOR WITH ENHANCED JUNCTION ISOLATION
63
Patent #:
Issue Dt:
10/09/2012
Application #:
13283328
Filing Dt:
10/27/2011
Publication #:
Pub Dt:
02/16/2012
Title:
STRUCTURE HAVING SUBSTANTIALLY PARALLEL RESISTOR MATERIAL LENGTHS
64
Patent #:
Issue Dt:
03/25/2014
Application #:
13283370
Filing Dt:
10/27/2011
Publication #:
Pub Dt:
05/02/2013
Title:
CANYON GATE TRANSISTOR AND METHODS FOR ITS FABRICATION
65
Patent #:
Issue Dt:
03/25/2014
Application #:
13283819
Filing Dt:
10/28/2011
Publication #:
Pub Dt:
02/16/2012
Title:
METHODS FOR ENHANCING QUALITY OF PIXEL SENSOR IMAGE FRAMES FOR GLOBAL SHUTTER IMAGING
66
Patent #:
Issue Dt:
04/09/2013
Application #:
13284239
Filing Dt:
10/28/2011
Publication #:
Pub Dt:
05/02/2013
Title:
IMPLEMENTING SCREENING FOR SINGLE FET COMPARE OF PHYSICALLY UNCLONABLE FUNCTION (PUF)
67
Patent #:
Issue Dt:
06/18/2013
Application #:
13284265
Filing Dt:
10/28/2011
Publication #:
Pub Dt:
05/02/2013
Title:
STARTUP AND PROTECTION CIRCUITRY FOR THIN OXIDE OUTPUT STAGE
68
Patent #:
Issue Dt:
06/03/2014
Application #:
13285162
Filing Dt:
10/31/2011
Publication #:
Pub Dt:
05/02/2013
Title:
Recessed Single Crystalline Source and Drain For Semiconductor-On-Insulator Devices
69
Patent #:
Issue Dt:
10/30/2012
Application #:
13285282
Filing Dt:
10/31/2011
Title:
SELECTIVE THRESHOLD VOLTAGE IMPLANTS FOR LONG CHANNEL DEVICES
70
Patent #:
Issue Dt:
04/07/2015
Application #:
13285408
Filing Dt:
10/31/2011
Publication #:
Pub Dt:
05/10/2012
Title:
LASER ASHING OF POLYIMIDE FOR SEMICONDUCTOR MANUFACTURING
71
Patent #:
Issue Dt:
07/15/2014
Application #:
13285443
Filing Dt:
10/31/2011
Publication #:
Pub Dt:
05/02/2013
Title:
FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING
72
Patent #:
Issue Dt:
02/19/2013
Application #:
13285600
Filing Dt:
10/31/2011
Title:
TRANSISTORS HAVING A CHANNEL SEMICONDUCTOR ALLOY FORMED IN AN EARLY PROCESS STAGE BASED ON A HARD MASK
73
Patent #:
Issue Dt:
04/16/2013
Application #:
13286292
Filing Dt:
11/01/2011
Publication #:
Pub Dt:
05/02/2013
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CONTROLLED P-CHANNEL THRESHOLD VOLTAGE
74
Patent #:
Issue Dt:
10/29/2013
Application #:
13286394
Filing Dt:
11/01/2011
Publication #:
Pub Dt:
05/02/2013
Title:
GRAPHENE AND NANOTUBE/NANOWIRE TRANSISTOR WITH A SELF-ALIGNED GATE STRUCTURE ON TRANSPARENT SUBSTRATES AND METHOD OF MAKING SAME
75
Patent #:
Issue Dt:
12/03/2013
Application #:
13287170
Filing Dt:
11/02/2011
Publication #:
Pub Dt:
02/23/2012
Title:
SEA-OF-FINS STRUCTURE ON A SEMICONDUCTOR SUBSTRATE AND METHOD OF FABRICATION
76
Patent #:
Issue Dt:
05/27/2014
Application #:
13287403
Filing Dt:
11/02/2011
Publication #:
Pub Dt:
05/02/2013
Title:
METHODS OF FORMING PFET DEVICES WITH DIFFERENT STRUCTURES AND PERFORMANCE CHARACTERISTICS
77
Patent #:
Issue Dt:
08/05/2014
Application #:
13287466
Filing Dt:
11/02/2011
Publication #:
Pub Dt:
05/02/2013
Title:
METHODS OF EPITAXIALLY FORMING MATERIALS ON TRANSISTOR DEVICES
78
Patent #:
Issue Dt:
08/05/2014
Application #:
13287575
Filing Dt:
11/02/2011
Publication #:
Pub Dt:
05/02/2013
Title:
SEMICONDUCTOR STRUCTURE
79
Patent #:
Issue Dt:
04/16/2013
Application #:
13288269
Filing Dt:
11/03/2011
Publication #:
Pub Dt:
05/09/2013
Title:
SPEED BINNING FOR DYNAMIC AND ADAPTIVE POWER CONTROL
80
Patent #:
Issue Dt:
08/26/2014
Application #:
13288541
Filing Dt:
11/03/2011
Publication #:
Pub Dt:
05/09/2013
Title:
Method and Apparatus for Simulating Gate Capacitance of a Tucked Transistor Device
81
Patent #:
Issue Dt:
04/30/2013
Application #:
13288645
Filing Dt:
11/03/2011
Publication #:
Pub Dt:
05/09/2013
Title:
THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING
82
Patent #:
Issue Dt:
05/14/2013
Application #:
13288686
Filing Dt:
11/03/2011
Publication #:
Pub Dt:
05/17/2012
Title:
CMOS IMAGER PHOTODIODE WITH ENHANCED CAPACITANCE
83
Patent #:
Issue Dt:
02/19/2013
Application #:
13289140
Filing Dt:
11/04/2011
Title:
METHOD FOR PROVIDING A SECURE "GRAY BOX" VIEW PROPRIETARY IP
84
Patent #:
Issue Dt:
10/16/2012
Application #:
13290634
Filing Dt:
11/07/2011
Publication #:
Pub Dt:
03/01/2012
Title:
SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX)
85
Patent #:
Issue Dt:
07/08/2014
Application #:
13290824
Filing Dt:
11/07/2011
Publication #:
Pub Dt:
03/01/2012
Title:
SEMICONDUCTOR PACKAGE STRUCTURES HAVING LIQUID COOLER INTEGRATED WITH FIRST LEVEL CHIP PACKAGE MODULES
86
Patent #:
Issue Dt:
05/28/2013
Application #:
13292585
Filing Dt:
11/09/2011
Publication #:
Pub Dt:
03/08/2012
Title:
INTEGRATED CIRCUIT TRANSFORMER DEVICES FOR ON-CHIP MILLIMETER-WAVE APPLICATIONS
87
Patent #:
Issue Dt:
04/14/2015
Application #:
13292629
Filing Dt:
11/09/2011
Publication #:
Pub Dt:
05/09/2013
Title:
RADIATION HARDENED MEMORY CELL AND DESIGN STRUCTURES
88
Patent #:
Issue Dt:
06/09/2015
Application #:
13292729
Filing Dt:
11/09/2011
Publication #:
Pub Dt:
05/09/2013
Title:
TUNABLE FILTER STRUCTURES AND DESIGN STRUCTURES
89
Patent #:
Issue Dt:
11/25/2014
Application #:
13293210
Filing Dt:
11/10/2011
Publication #:
Pub Dt:
05/16/2013
Title:
GATE STRUCTURES AND METHODS OF MANUFACTURE
90
Patent #:
Issue Dt:
01/13/2015
Application #:
13293672
Filing Dt:
11/10/2011
Publication #:
Pub Dt:
05/16/2013
Title:
HYBRID PHOTORESIST COMPOSITION AND PATTERN FORMING METHOD USING THEREOF
91
Patent #:
Issue Dt:
09/24/2013
Application #:
13294210
Filing Dt:
11/11/2011
Publication #:
Pub Dt:
05/16/2013
Title:
TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS
92
Patent #:
Issue Dt:
07/16/2013
Application #:
13294220
Filing Dt:
11/11/2011
Publication #:
Pub Dt:
05/16/2013
Title:
DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCILLATOR AND PERFORMANCE PATH TESTING
93
Patent #:
Issue Dt:
08/11/2015
Application #:
13294603
Filing Dt:
11/11/2011
Publication #:
Pub Dt:
05/16/2013
Title:
INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE
94
Patent #:
Issue Dt:
10/01/2013
Application #:
13294610
Filing Dt:
11/11/2011
Publication #:
Pub Dt:
05/16/2013
Title:
METHODS OF MANUFACTURING INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM
95
Patent #:
Issue Dt:
01/14/2014
Application #:
13294615
Filing Dt:
11/11/2011
Publication #:
Pub Dt:
05/16/2013
Title:
INTEGRATED SEMICONDUCTOR DEVICES WITH AMORPHOUS SILICON BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE
96
Patent #:
Issue Dt:
12/23/2014
Application #:
13294671
Filing Dt:
11/11/2011
Publication #:
Pub Dt:
05/16/2013
Title:
BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS
97
Patent #:
Issue Dt:
12/30/2014
Application #:
13294697
Filing Dt:
11/11/2011
Publication #:
Pub Dt:
05/16/2013
Title:
PNP BIPOLAR JUNCTION TRANSISTOR FABRICATION USING SELECTIVE EPITAXY
98
Patent #:
Issue Dt:
01/06/2015
Application #:
13294731
Filing Dt:
11/11/2011
Publication #:
Pub Dt:
05/16/2013
Title:
JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY
99
Patent #:
Issue Dt:
10/28/2014
Application #:
13294760
Filing Dt:
11/11/2011
Publication #:
Pub Dt:
05/16/2013
Title:
SCHOTTKY BARRIER DIODES WITH A GUARD RING FORMED BY SELECTIVE EPITAXY
100
Patent #:
Issue Dt:
07/23/2013
Application #:
13295351
Filing Dt:
11/14/2011
Publication #:
Pub Dt:
05/16/2013
Title:
LEAKAGE TOLERANT DELAY LOCKED LOOP CIRCUIT DEVICE
Assignor
1
Exec Dt:
11/27/2018
Assignee
1
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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