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Issue Dt:
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09/16/2014
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13343190
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Filing Dt:
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01/04/2012
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Publication #:
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Pub Dt:
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07/04/2013
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Title:
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Titanium-Nitride Removal
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07/02/2013
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13343472
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Filing Dt:
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01/04/2012
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Publication #:
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Pub Dt:
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07/04/2013
| | | | |
Title:
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CMOS HAVING A SIC/SIGE ALLOY STACK
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Patent #:
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Issue Dt:
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06/17/2014
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13343513
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Filing Dt:
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01/27/2012
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Pub Dt:
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08/01/2013
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Title:
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METHODS FOR FABRICATING MOS DEVICES WITH STRESS MEMORIZATION
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02/03/2015
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13343688
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01/04/2012
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Pub Dt:
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07/04/2013
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Title:
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SOI LATERAL BIPOLAR TRANSISTOR HAVING MULTI-SIDED BASE CONTACT AND METHODS FOR MAKING SAME
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02/11/2014
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13343799
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01/05/2012
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Pub Dt:
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07/11/2013
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Title:
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NANOWIRE FIELD EFFECT TRANSISTORS
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02/12/2013
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13343850
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Filing Dt:
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01/05/2012
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Publication #:
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Pub Dt:
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05/03/2012
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Title:
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WORK FUNCTION ENGINEERING FOR EDRAM MOSFETS
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06/23/2015
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13343938
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Filing Dt:
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01/05/2012
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Publication #:
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Pub Dt:
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07/11/2013
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Title:
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IMPLEMENTING ENHANCED HARDWARE ASSISTED DRAM REPAIR USING A DATA REGISTER FOR DRAM REPAIR SELECTIVELY PROVIDED IN A DRAM MODULE
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04/09/2013
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13344006
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Filing Dt:
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01/05/2012
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Publication #:
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Pub Dt:
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05/10/2012
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Title:
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SOI CMOS CIRCUITS WITH SUBSTRATE BIAS
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07/15/2014
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13344009
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01/05/2012
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Pub Dt:
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07/11/2013
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Title:
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Interlevel Dielectric Stack for Interconnect Structures
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08/04/2015
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13344313
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Filing Dt:
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01/05/2012
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Pub Dt:
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07/11/2013
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Title:
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PROVIDING A FAULT TOLERANT SYSTEM IN A LOOSELY-COUPLED CLUSTER ENVIRONMENT USING APPLICATION CHECKPOINTS AND LOGS
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07/23/2013
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13344352
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01/05/2012
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Pub Dt:
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07/11/2013
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Title:
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Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process
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Issue Dt:
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05/17/2016
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13344517
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01/05/2012
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Pub Dt:
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07/11/2013
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Title:
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NANOWIRE FLOATING GATE TRANSISTOR
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11/25/2014
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13344806
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01/06/2012
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Pub Dt:
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07/11/2013
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Title:
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INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
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02/18/2014
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13344885
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01/06/2012
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Pub Dt:
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07/11/2013
| | | | |
Title:
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INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC
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01/07/2014
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13344955
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01/06/2012
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Pub Dt:
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05/03/2012
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Title:
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FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE
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07/01/2014
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13345120
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Filing Dt:
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01/06/2012
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Pub Dt:
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07/11/2013
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Title:
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THICK ON-CHIP HIGH-PERFORMANCE WIRING STRUCTURES
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02/04/2014
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13345233
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Filing Dt:
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01/06/2012
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Pub Dt:
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07/11/2013
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Title:
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FINFET WITH FULLY SILICIDED GATE
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10/16/2012
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13345252
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01/06/2012
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Pub Dt:
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05/03/2012
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Title:
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FIELD EFFECT TRANSISTOR HAVING NANOSTRUCTURE CHANNEL
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02/25/2014
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13345266
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01/06/2012
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Pub Dt:
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07/11/2013
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Title:
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INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR
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12/02/2014
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13345290
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01/06/2012
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Pub Dt:
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07/11/2013
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Title:
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THERMALLY STABLE HIGH-K TETRAGONAL HFO2 LAYER WITHIN HIGH ASPECT RATIO DEEP TRENCHES
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07/01/2014
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13345388
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01/06/2012
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Pub Dt:
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07/11/2013
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Title:
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SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS
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Issue Dt:
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09/03/2013
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13345457
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01/06/2012
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Pub Dt:
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07/11/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH STRAIN-INDUCING REGIONS AND METHOD THEREOF
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09/10/2013
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13345619
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01/06/2012
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Pub Dt:
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07/11/2013
| | | | |
Title:
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8-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES
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Issue Dt:
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12/31/2013
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13345629
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Filing Dt:
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01/06/2012
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Pub Dt:
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07/11/2013
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Title:
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8-TRANSISTOR SRAM CELL DESIGN WITH INNER PASS-GATE JUNCTION DIODES
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09/03/2013
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13345636
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01/06/2012
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Pub Dt:
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07/11/2013
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Title:
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8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES
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07/23/2013
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13345881
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01/09/2012
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Pub Dt:
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07/11/2013
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Title:
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ISOLATED ZENER DIODE
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Issue Dt:
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11/08/2016
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13345922
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01/09/2012
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Pub Dt:
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07/11/2013
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Title:
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Methods of Making Transistor Devices with Elevated Source/Drain Regions to Accommodate Consumption During Metal Silicide Formation Process
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05/14/2013
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13346008
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Filing Dt:
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01/09/2012
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Title:
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METHOD TO FORM LOW SERIES RESISTANCE TRANSISTOR DEVICES ON SILICON ON INSULATOR LAYER
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04/21/2015
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13346043
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01/09/2012
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Pub Dt:
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07/11/2013
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IN SITU DOPING AND DIFFUSIONLESS ANNEALING OF EMBEDDED STRESSOR REGIONS IN PMOS AND NMOS DEVICES
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03/04/2014
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13346164
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01/09/2012
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Pub Dt:
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07/11/2013
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SEMICONDUCTOR DEVICE WITH AN OVERSIZED LOCAL CONTACT AS A FARADAY SHIELD
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11/19/2013
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13346242
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01/09/2012
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07/11/2013
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OFF-LINE GAIN CALIBRATION IN A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER
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03/19/2013
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13346776
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01/10/2012
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05/03/2012
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METHODS OF FABRICATING PHOTOMASKS FOR IMPROVING DAMASCENE WIRE UNIFORMITY WITHOUT REDUCING PERFORMANCE
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01/15/2013
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13347014
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01/10/2012
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05/03/2012
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THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION
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05/06/2014
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13347571
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01/10/2012
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07/11/2013
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INDUCTOR WITH LAMINATED YOKE
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10/28/2014
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13347851
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01/11/2012
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05/10/2012
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A TRANSISTOR STRUCTURE HAVING AN ELECTRICAL CONTACT STRUCTURE WITH MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER
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01/14/2014
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13348018
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01/11/2012
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Pub Dt:
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07/11/2013
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ELECTRICAL ISOLATION STRUCTURES FOR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR DEVICES
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07/15/2014
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13348101
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01/11/2012
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07/11/2013
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METHOD OF FORMING TRANSISTOR WITH INCREASED GATE WIDTH
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02/03/2015
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13348142
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01/11/2012
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07/11/2013
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SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
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10/15/2013
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13348188
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01/11/2012
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07/11/2013
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RECESSED SOURCE AND DRAIN REGIONS FOR FINFETS
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10/14/2014
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13348256
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01/11/2012
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07/11/2013
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Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique
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10/15/2013
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13348771
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01/12/2012
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07/18/2013
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METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER
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02/18/2014
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13348850
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01/12/2012
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07/18/2013
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INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM
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05/14/2013
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13349158
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01/12/2012
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05/03/2012
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EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE
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05/31/2016
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13349203
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01/12/2012
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05/03/2012
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DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
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04/09/2013
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13349412
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01/12/2012
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METHODS FOR PATTERN MATCHING IN A DOUBLE PATTERNING TECHNOLOGY-COMPLIANT PHYSICAL DESIGN FLOW
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05/21/2013
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13349883
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01/13/2012
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05/10/2012
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FABRICATION OF SEMICONDUCTORS WITH HIGH-K/METAL GATE ELECTRODES
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01/27/2015
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13349942
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01/13/2012
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07/18/2013
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STRAIN ENGINEERING IN THREE-DIMENSIONAL TRANSISTORS BASED ON STRAINED ISOLATION MATERIAL
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12/25/2012
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13350817
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01/16/2012
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05/10/2012
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METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL
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11/04/2014
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13350889
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01/16/2012
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05/10/2012
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LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION
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03/11/2014
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13350891
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01/16/2012
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07/18/2013
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METHODS OF REDUCING GATE LEAKAGE
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08/25/2015
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13350908
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01/16/2012
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07/18/2013
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METHODS OF FORMING A DIELECTRIC CAP LAYER ON A METAL GATE STRUCTURE
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07/15/2014
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13350981
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01/16/2012
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05/10/2012
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ULTRA-COMPACT PLL WITH WIDE TUNING RANGE AND LOW NOISE
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07/23/2013
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13351012
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01/16/2012
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05/17/2012
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TRENCH-GENERATED TRANSISTOR STRUCTURES, DEVICE STRUCTURES, AND DESIGN STRUCTURES
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12/03/2013
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13351101
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01/16/2012
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07/18/2013
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SEMICONDUCTOR DEVICE HAVING CONTACT LAYER PROVIDING ELECTRICAL CONNECTIONS
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06/03/2014
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13351294
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01/17/2012
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07/18/2013
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LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES
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02/26/2013
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13351370
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01/17/2012
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05/10/2012
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METHOD FOR FABRICATING AIR GAP INTERCONNECT STRUCTURES
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06/04/2013
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13351398
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01/17/2012
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05/10/2012
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GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
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05/28/2013
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13351402
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01/17/2012
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Pub Dt:
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05/10/2012
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Title:
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GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
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Patent #:
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Issue Dt:
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11/04/2014
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Application #:
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13352713
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Filing Dt:
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01/18/2012
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Publication #:
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Pub Dt:
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07/18/2013
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Title:
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ANALYZING A PATTERNING PROCESS USING A MODEL OF YIELD
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Patent #:
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Issue Dt:
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06/10/2014
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Application #:
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13352737
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Filing Dt:
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01/18/2012
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Publication #:
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Pub Dt:
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07/19/2012
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Title:
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GRAPHENE DEVICES AND SEMICONDUCTOR FIELD EFFECT TRANSISTORS IN 3D HYBRID INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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08/05/2014
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Application #:
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13352851
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Filing Dt:
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01/18/2012
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Publication #:
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Pub Dt:
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07/18/2013
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Title:
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DIFFUSION BARRIER FOR OPPOSITELY DOPED PORTIONS OF GATE CONDUCTOR
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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13353118
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Filing Dt:
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01/18/2012
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Publication #:
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Pub Dt:
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07/18/2013
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Title:
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SILICON PHOTONIC CHIP OPTICAL COUPLING STRUCTURES
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Patent #:
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Issue Dt:
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12/02/2014
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Application #:
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13353162
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Filing Dt:
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01/18/2012
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Publication #:
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Pub Dt:
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07/18/2013
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Title:
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SILICON PHOTONICS WAFER USING STANDARD SILICON-ON-INSULATOR PROCESSES THROUGH SUBSTRATE REMOVAL OR TRANSFER
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Patent #:
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Issue Dt:
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06/25/2013
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Application #:
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13353383
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Filing Dt:
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01/19/2012
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Title:
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SELECTABLE DYNAMIC/STATIC LATCH WITH EMBEDDED LOGIC
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Patent #:
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Issue Dt:
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07/08/2014
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Application #:
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13353708
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Filing Dt:
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01/19/2012
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Publication #:
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Pub Dt:
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07/25/2013
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Title:
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FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE
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Patent #:
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Issue Dt:
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09/23/2014
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Application #:
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13353879
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Filing Dt:
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01/19/2012
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Publication #:
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Pub Dt:
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07/25/2013
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Title:
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DYNAMIC GRADUATED MEMORY DEVICE PROTECTION IN REDUNDANT ARRAY OF INDEPENDENT MEMORY (RAIM) SYSTEMS
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Patent #:
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Issue Dt:
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07/15/2014
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Application #:
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13353925
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Filing Dt:
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01/19/2012
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM
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Patent #:
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Issue Dt:
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09/29/2015
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Application #:
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13354024
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Filing Dt:
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01/19/2012
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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FINFET SEMICONDUCTOR DEVICES WITH IMPROVED SOURCE/DRAIN RESISTANCE AND METHODS OF MAKING SAME
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Patent #:
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Issue Dt:
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11/17/2015
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Application #:
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13354070
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Filing Dt:
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01/19/2012
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICES WITH COPPER INTERCONNECTS AND METHODS FOR FABRICATING SAME
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Patent #:
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Issue Dt:
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05/19/2015
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Application #:
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13354363
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Filing Dt:
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01/20/2012
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICE WITH A LOW-K SPACER AND METHOD OF FORMING THE SAME
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13354705
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Filing Dt:
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01/20/2012
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
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|
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Patent #:
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Issue Dt:
|
07/16/2013
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Application #:
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13354715
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Filing Dt:
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01/20/2012
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
Title:
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METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13354739
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Filing Dt:
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01/20/2012
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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METHOD OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13354883
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Filing Dt:
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01/20/2012
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Publication #:
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Pub Dt:
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05/24/2012
| | | | |
Title:
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METHOD FOR AUTOMATIC GENERATION OF THROUGHPUT MODELS FOR SEMICONDUCTOR TOOLS
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Patent #:
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Issue Dt:
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11/19/2013
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Application #:
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13355065
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Filing Dt:
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01/20/2012
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
Title:
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METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
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Patent #:
|
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Issue Dt:
|
08/06/2013
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Application #:
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13355099
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Filing Dt:
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01/20/2012
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
10/23/2012
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Application #:
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13355221
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Filing Dt:
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01/20/2012
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Publication #:
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Pub Dt:
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05/24/2012
| | | | |
Title:
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METHOD OF MANUFACTURING A TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS
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Patent #:
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Issue Dt:
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12/30/2014
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Application #:
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13356013
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Filing Dt:
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01/23/2012
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13356090
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Filing Dt:
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01/23/2012
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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METHOD TO FORM SILICIDE CONTACT IN TRENCHES
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|
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Patent #:
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Issue Dt:
|
01/08/2013
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Application #:
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13356681
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Filing Dt:
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01/24/2012
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Title:
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ANALYTIC EXPERIMENTAL ESTIMATOR FOR IMPACT OF VOLTAGE-OVERSHOOT OF VOLTAGE WAVEFORM ON DIELECTRIC FAILURE/BREAKDOWN
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|
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Patent #:
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Issue Dt:
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01/01/2013
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Application #:
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13357656
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Filing Dt:
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01/25/2012
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Publication #:
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Pub Dt:
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05/31/2012
| | | | |
Title:
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N-TYPE CARRIER ENHANCEMENT IN SEMICONDUCTORS
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13358101
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Filing Dt:
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01/25/2012
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Publication #:
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Pub Dt:
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08/02/2012
| | | | |
Title:
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SOPHISTICATED GATE ELECTRODE STRUCTURES FORMED BY CAP LAYER REMOVAL WITH REDUCED LOSS OF EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL
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|
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Patent #:
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Issue Dt:
|
04/16/2013
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Application #:
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13358105
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Filing Dt:
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01/25/2012
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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SEMICONDUCTOR STRUCTURE AND METHOD OF DESIGNING SEMICONDUCTOR STRUCTURE TO AVOID HIGH VOLTAGE INITIATED LATCH-UP IN LOW VOLTAGE SECTORS
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Patent #:
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Issue Dt:
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08/04/2015
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Application #:
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13358172
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Filing Dt:
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01/25/2012
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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METHOD OF MANUFACTURING SWITCHING FILTERS AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13358180
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Filing Dt:
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01/25/2012
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Publication #:
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Pub Dt:
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07/25/2013
| | | | |
Title:
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HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
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Patent #:
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Issue Dt:
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04/02/2013
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Application #:
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13358963
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Filing Dt:
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01/26/2012
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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3D OPTOELECTRONIC PACKAGING
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Patent #:
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Issue Dt:
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12/17/2013
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Application #:
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13359032
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Filing Dt:
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01/26/2012
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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METHOD OF FORMING MIM CAPACITOR STRUCTURE IN FEOL
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Patent #:
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Issue Dt:
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07/09/2013
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Application #:
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13359100
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Filing Dt:
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01/26/2012
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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3D OPTOELECTRONIC PACKAGING
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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13359107
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Filing Dt:
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01/26/2012
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Publication #:
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Pub Dt:
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08/01/2013
| | | | |
Title:
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CELL ARRAY AND DENSITY FEATURES WITH DECOUPLING CAPACITORS
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Patent #:
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Issue Dt:
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01/27/2015
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Application #:
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13359177
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Filing Dt:
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01/26/2012
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE
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Patent #:
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Issue Dt:
|
03/11/2014
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Application #:
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13359197
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Filing Dt:
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01/26/2012
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Publication #:
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Pub Dt:
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08/01/2013
| | | | |
Title:
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Methods of Forming SRAM Devices Using Sidewall Image Transfer Techniques
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Patent #:
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Issue Dt:
|
11/19/2013
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Application #:
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13359454
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Filing Dt:
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01/26/2012
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Publication #:
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Pub Dt:
|
08/01/2013
| | | | |
Title:
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SRAM WITH HYBRID FINFET AND PLANAR TRANSISTORS
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Patent #:
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Issue Dt:
|
07/16/2013
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Application #:
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13359634
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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05/31/2012
| | | | |
Title:
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METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
|
10/07/2014
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Application #:
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13359729
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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08/02/2012
| | | | |
Title:
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ELECTRON BEAM SCULPTING OF TUNNELING JUNCTION FOR NANOPORE DNA SEQUENCING
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Patent #:
|
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Issue Dt:
|
01/27/2015
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Application #:
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13359970
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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05/24/2012
| | | | |
Title:
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METHOD OF CREATING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER HAVING A UNIFORM THICKNESS
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Patent #:
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Issue Dt:
|
10/30/2012
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Application #:
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13360055
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
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05/17/2012
| | | | |
Title:
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PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP
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Patent #:
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Issue Dt:
|
01/28/2014
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Application #:
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13360083
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Filing Dt:
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01/27/2012
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Publication #:
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Pub Dt:
|
08/01/2013
| | | | |
Title:
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CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY
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Patent #:
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Issue Dt:
|
02/05/2013
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Application #:
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13360203
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Filing Dt:
|
01/27/2012
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Publication #:
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Pub Dt:
|
05/17/2012
| | | | |
Title:
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ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
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|
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Patent #:
|
|
Issue Dt:
|
02/05/2013
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Application #:
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13360248
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Filing Dt:
|
01/27/2012
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Publication #:
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Pub Dt:
|
05/24/2012
| | | | |
Title:
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ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
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|
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Patent #:
|
|
Issue Dt:
|
02/05/2013
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Application #:
|
13360270
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Filing Dt:
|
01/27/2012
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Publication #:
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Pub Dt:
|
05/24/2012
| | | | |
Title:
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ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
|
|