skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
1
Patent #:
Issue Dt:
09/16/2014
Application #:
13343190
Filing Dt:
01/04/2012
Publication #:
Pub Dt:
07/04/2013
Title:
Titanium-Nitride Removal
2
Patent #:
Issue Dt:
07/02/2013
Application #:
13343472
Filing Dt:
01/04/2012
Publication #:
Pub Dt:
07/04/2013
Title:
CMOS HAVING A SIC/SIGE ALLOY STACK
3
Patent #:
Issue Dt:
06/17/2014
Application #:
13343513
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
08/01/2013
Title:
METHODS FOR FABRICATING MOS DEVICES WITH STRESS MEMORIZATION
4
Patent #:
Issue Dt:
02/03/2015
Application #:
13343688
Filing Dt:
01/04/2012
Publication #:
Pub Dt:
07/04/2013
Title:
SOI LATERAL BIPOLAR TRANSISTOR HAVING MULTI-SIDED BASE CONTACT AND METHODS FOR MAKING SAME
5
Patent #:
Issue Dt:
02/11/2014
Application #:
13343799
Filing Dt:
01/05/2012
Publication #:
Pub Dt:
07/11/2013
Title:
NANOWIRE FIELD EFFECT TRANSISTORS
6
Patent #:
Issue Dt:
02/12/2013
Application #:
13343850
Filing Dt:
01/05/2012
Publication #:
Pub Dt:
05/03/2012
Title:
WORK FUNCTION ENGINEERING FOR EDRAM MOSFETS
7
Patent #:
Issue Dt:
06/23/2015
Application #:
13343938
Filing Dt:
01/05/2012
Publication #:
Pub Dt:
07/11/2013
Title:
IMPLEMENTING ENHANCED HARDWARE ASSISTED DRAM REPAIR USING A DATA REGISTER FOR DRAM REPAIR SELECTIVELY PROVIDED IN A DRAM MODULE
8
Patent #:
Issue Dt:
04/09/2013
Application #:
13344006
Filing Dt:
01/05/2012
Publication #:
Pub Dt:
05/10/2012
Title:
SOI CMOS CIRCUITS WITH SUBSTRATE BIAS
9
Patent #:
Issue Dt:
07/15/2014
Application #:
13344009
Filing Dt:
01/05/2012
Publication #:
Pub Dt:
07/11/2013
Title:
Interlevel Dielectric Stack for Interconnect Structures
10
Patent #:
Issue Dt:
08/04/2015
Application #:
13344313
Filing Dt:
01/05/2012
Publication #:
Pub Dt:
07/11/2013
Title:
PROVIDING A FAULT TOLERANT SYSTEM IN A LOOSELY-COUPLED CLUSTER ENVIRONMENT USING APPLICATION CHECKPOINTS AND LOGS
11
Patent #:
Issue Dt:
07/23/2013
Application #:
13344352
Filing Dt:
01/05/2012
Publication #:
Pub Dt:
07/11/2013
Title:
Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process
12
Patent #:
Issue Dt:
05/17/2016
Application #:
13344517
Filing Dt:
01/05/2012
Publication #:
Pub Dt:
07/11/2013
Title:
NANOWIRE FLOATING GATE TRANSISTOR
13
Patent #:
Issue Dt:
11/25/2014
Application #:
13344806
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
INTEGRATED CIRCUIT HAVING RAISED SOURCE DRAINS DEVICES WITH REDUCED SILICIDE CONTACT RESISTANCE AND METHODS TO FABRICATE SAME
14
Patent #:
Issue Dt:
02/18/2014
Application #:
13344885
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC
15
Patent #:
Issue Dt:
01/07/2014
Application #:
13344955
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
05/03/2012
Title:
FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE
16
Patent #:
Issue Dt:
07/01/2014
Application #:
13345120
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
THICK ON-CHIP HIGH-PERFORMANCE WIRING STRUCTURES
17
Patent #:
Issue Dt:
02/04/2014
Application #:
13345233
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
FINFET WITH FULLY SILICIDED GATE
18
Patent #:
Issue Dt:
10/16/2012
Application #:
13345252
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
05/03/2012
Title:
FIELD EFFECT TRANSISTOR HAVING NANOSTRUCTURE CHANNEL
19
Patent #:
Issue Dt:
02/25/2014
Application #:
13345266
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR
20
Patent #:
Issue Dt:
12/02/2014
Application #:
13345290
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
THERMALLY STABLE HIGH-K TETRAGONAL HFO2 LAYER WITHIN HIGH ASPECT RATIO DEEP TRENCHES
21
Patent #:
Issue Dt:
07/01/2014
Application #:
13345388
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
SEMICONDUCTOR DEVICES HAVING DIELECTRIC CAPS ON CONTACTS AND RELATED FABRICATION METHODS
22
Patent #:
Issue Dt:
09/03/2013
Application #:
13345457
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
SEMICONDUCTOR DEVICE WITH STRAIN-INDUCING REGIONS AND METHOD THEREOF
23
Patent #:
Issue Dt:
09/10/2013
Application #:
13345619
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
8-TRANSISTOR SRAM CELL DESIGN WITH SCHOTTKY DIODES
24
Patent #:
Issue Dt:
12/31/2013
Application #:
13345629
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
8-TRANSISTOR SRAM CELL DESIGN WITH INNER PASS-GATE JUNCTION DIODES
25
Patent #:
Issue Dt:
09/03/2013
Application #:
13345636
Filing Dt:
01/06/2012
Publication #:
Pub Dt:
07/11/2013
Title:
8-TRANSISTOR SRAM CELL DESIGN WITH OUTER PASS-GATE DIODES
26
Patent #:
Issue Dt:
07/23/2013
Application #:
13345881
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
07/11/2013
Title:
ISOLATED ZENER DIODE
27
Patent #:
Issue Dt:
11/08/2016
Application #:
13345922
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
07/11/2013
Title:
Methods of Making Transistor Devices with Elevated Source/Drain Regions to Accommodate Consumption During Metal Silicide Formation Process
28
Patent #:
Issue Dt:
05/14/2013
Application #:
13346008
Filing Dt:
01/09/2012
Title:
METHOD TO FORM LOW SERIES RESISTANCE TRANSISTOR DEVICES ON SILICON ON INSULATOR LAYER
29
Patent #:
Issue Dt:
04/21/2015
Application #:
13346043
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
07/11/2013
Title:
IN SITU DOPING AND DIFFUSIONLESS ANNEALING OF EMBEDDED STRESSOR REGIONS IN PMOS AND NMOS DEVICES
30
Patent #:
Issue Dt:
03/04/2014
Application #:
13346164
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
07/11/2013
Title:
SEMICONDUCTOR DEVICE WITH AN OVERSIZED LOCAL CONTACT AS A FARADAY SHIELD
31
Patent #:
Issue Dt:
11/19/2013
Application #:
13346242
Filing Dt:
01/09/2012
Publication #:
Pub Dt:
07/11/2013
Title:
OFF-LINE GAIN CALIBRATION IN A TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER
32
Patent #:
Issue Dt:
03/19/2013
Application #:
13346776
Filing Dt:
01/10/2012
Publication #:
Pub Dt:
05/03/2012
Title:
METHODS OF FABRICATING PHOTOMASKS FOR IMPROVING DAMASCENE WIRE UNIFORMITY WITHOUT REDUCING PERFORMANCE
33
Patent #:
Issue Dt:
01/15/2013
Application #:
13347014
Filing Dt:
01/10/2012
Publication #:
Pub Dt:
05/03/2012
Title:
THRESHOLD VOLTAGE ADJUSTMENT THROUGH GATE DIELECTRIC STACK MODIFICATION
34
Patent #:
Issue Dt:
05/06/2014
Application #:
13347571
Filing Dt:
01/10/2012
Publication #:
Pub Dt:
07/11/2013
Title:
INDUCTOR WITH LAMINATED YOKE
35
Patent #:
Issue Dt:
10/28/2014
Application #:
13347851
Filing Dt:
01/11/2012
Publication #:
Pub Dt:
05/10/2012
Title:
A TRANSISTOR STRUCTURE HAVING AN ELECTRICAL CONTACT STRUCTURE WITH MULTIPLE METAL INTERCONNECT LEVELS STAGGERING ONE ANOTHER
36
Patent #:
Issue Dt:
01/14/2014
Application #:
13348018
Filing Dt:
01/11/2012
Publication #:
Pub Dt:
07/11/2013
Title:
ELECTRICAL ISOLATION STRUCTURES FOR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR DEVICES
37
Patent #:
Issue Dt:
07/15/2014
Application #:
13348101
Filing Dt:
01/11/2012
Publication #:
Pub Dt:
07/11/2013
Title:
METHOD OF FORMING TRANSISTOR WITH INCREASED GATE WIDTH
38
Patent #:
Issue Dt:
02/03/2015
Application #:
13348142
Filing Dt:
01/11/2012
Publication #:
Pub Dt:
07/11/2013
Title:
SRAM INTEGRATED CIRCUITS AND METHODS FOR THEIR FABRICATION
39
Patent #:
Issue Dt:
10/15/2013
Application #:
13348188
Filing Dt:
01/11/2012
Publication #:
Pub Dt:
07/11/2013
Title:
RECESSED SOURCE AND DRAIN REGIONS FOR FINFETS
40
Patent #:
Issue Dt:
10/14/2014
Application #:
13348256
Filing Dt:
01/11/2012
Publication #:
Pub Dt:
07/11/2013
Title:
Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique
41
Patent #:
Issue Dt:
10/15/2013
Application #:
13348771
Filing Dt:
01/12/2012
Publication #:
Pub Dt:
07/18/2013
Title:
METHOD FOR FORMING N-SHAPED BOTTOM STRESS LINER
42
Patent #:
Issue Dt:
02/18/2014
Application #:
13348850
Filing Dt:
01/12/2012
Publication #:
Pub Dt:
07/18/2013
Title:
INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM
43
Patent #:
Issue Dt:
05/14/2013
Application #:
13349158
Filing Dt:
01/12/2012
Publication #:
Pub Dt:
05/03/2012
Title:
EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE
44
Patent #:
Issue Dt:
05/31/2016
Application #:
13349203
Filing Dt:
01/12/2012
Publication #:
Pub Dt:
05/03/2012
Title:
DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS
45
Patent #:
Issue Dt:
04/09/2013
Application #:
13349412
Filing Dt:
01/12/2012
Title:
METHODS FOR PATTERN MATCHING IN A DOUBLE PATTERNING TECHNOLOGY-COMPLIANT PHYSICAL DESIGN FLOW
46
Patent #:
Issue Dt:
05/21/2013
Application #:
13349883
Filing Dt:
01/13/2012
Publication #:
Pub Dt:
05/10/2012
Title:
FABRICATION OF SEMICONDUCTORS WITH HIGH-K/METAL GATE ELECTRODES
47
Patent #:
Issue Dt:
01/27/2015
Application #:
13349942
Filing Dt:
01/13/2012
Publication #:
Pub Dt:
07/18/2013
Title:
STRAIN ENGINEERING IN THREE-DIMENSIONAL TRANSISTORS BASED ON STRAINED ISOLATION MATERIAL
48
Patent #:
Issue Dt:
12/25/2012
Application #:
13350817
Filing Dt:
01/16/2012
Publication #:
Pub Dt:
05/10/2012
Title:
METHOD TO REDUCE A VIA AREA IN A PHASE CHANGE MEMORY CELL
49
Patent #:
Issue Dt:
11/04/2014
Application #:
13350889
Filing Dt:
01/16/2012
Publication #:
Pub Dt:
05/10/2012
Title:
LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION
50
Patent #:
Issue Dt:
03/11/2014
Application #:
13350891
Filing Dt:
01/16/2012
Publication #:
Pub Dt:
07/18/2013
Title:
METHODS OF REDUCING GATE LEAKAGE
51
Patent #:
Issue Dt:
08/25/2015
Application #:
13350908
Filing Dt:
01/16/2012
Publication #:
Pub Dt:
07/18/2013
Title:
METHODS OF FORMING A DIELECTRIC CAP LAYER ON A METAL GATE STRUCTURE
52
Patent #:
Issue Dt:
07/15/2014
Application #:
13350981
Filing Dt:
01/16/2012
Publication #:
Pub Dt:
05/10/2012
Title:
ULTRA-COMPACT PLL WITH WIDE TUNING RANGE AND LOW NOISE
53
Patent #:
Issue Dt:
07/23/2013
Application #:
13351012
Filing Dt:
01/16/2012
Publication #:
Pub Dt:
05/17/2012
Title:
TRENCH-GENERATED TRANSISTOR STRUCTURES, DEVICE STRUCTURES, AND DESIGN STRUCTURES
54
Patent #:
Issue Dt:
12/03/2013
Application #:
13351101
Filing Dt:
01/16/2012
Publication #:
Pub Dt:
07/18/2013
Title:
SEMICONDUCTOR DEVICE HAVING CONTACT LAYER PROVIDING ELECTRICAL CONNECTIONS
55
Patent #:
Issue Dt:
06/03/2014
Application #:
13351294
Filing Dt:
01/17/2012
Publication #:
Pub Dt:
07/18/2013
Title:
LOCAL INTERCONNECTS COMPATIBLE WITH REPLACEMENT GATE STRUCTURES
56
Patent #:
Issue Dt:
02/26/2013
Application #:
13351370
Filing Dt:
01/17/2012
Publication #:
Pub Dt:
05/10/2012
Title:
METHOD FOR FABRICATING AIR GAP INTERCONNECT STRUCTURES
57
Patent #:
Issue Dt:
06/04/2013
Application #:
13351398
Filing Dt:
01/17/2012
Publication #:
Pub Dt:
05/10/2012
Title:
GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
58
Patent #:
Issue Dt:
05/28/2013
Application #:
13351402
Filing Dt:
01/17/2012
Publication #:
Pub Dt:
05/10/2012
Title:
GRAPHENE BASED SWITCHING DEVICE HAVING A TUNABLE BANDGAP
59
Patent #:
Issue Dt:
11/04/2014
Application #:
13352713
Filing Dt:
01/18/2012
Publication #:
Pub Dt:
07/18/2013
Title:
ANALYZING A PATTERNING PROCESS USING A MODEL OF YIELD
60
Patent #:
Issue Dt:
06/10/2014
Application #:
13352737
Filing Dt:
01/18/2012
Publication #:
Pub Dt:
07/19/2012
Title:
GRAPHENE DEVICES AND SEMICONDUCTOR FIELD EFFECT TRANSISTORS IN 3D HYBRID INTEGRATED CIRCUITS
61
Patent #:
Issue Dt:
08/05/2014
Application #:
13352851
Filing Dt:
01/18/2012
Publication #:
Pub Dt:
07/18/2013
Title:
DIFFUSION BARRIER FOR OPPOSITELY DOPED PORTIONS OF GATE CONDUCTOR
62
Patent #:
Issue Dt:
10/07/2014
Application #:
13353118
Filing Dt:
01/18/2012
Publication #:
Pub Dt:
07/18/2013
Title:
SILICON PHOTONIC CHIP OPTICAL COUPLING STRUCTURES
63
Patent #:
Issue Dt:
12/02/2014
Application #:
13353162
Filing Dt:
01/18/2012
Publication #:
Pub Dt:
07/18/2013
Title:
SILICON PHOTONICS WAFER USING STANDARD SILICON-ON-INSULATOR PROCESSES THROUGH SUBSTRATE REMOVAL OR TRANSFER
64
Patent #:
Issue Dt:
06/25/2013
Application #:
13353383
Filing Dt:
01/19/2012
Title:
SELECTABLE DYNAMIC/STATIC LATCH WITH EMBEDDED LOGIC
65
Patent #:
Issue Dt:
07/08/2014
Application #:
13353708
Filing Dt:
01/19/2012
Publication #:
Pub Dt:
07/25/2013
Title:
FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE
66
Patent #:
Issue Dt:
09/23/2014
Application #:
13353879
Filing Dt:
01/19/2012
Publication #:
Pub Dt:
07/25/2013
Title:
DYNAMIC GRADUATED MEMORY DEVICE PROTECTION IN REDUNDANT ARRAY OF INDEPENDENT MEMORY (RAIM) SYSTEMS
67
Patent #:
Issue Dt:
07/15/2014
Application #:
13353925
Filing Dt:
01/19/2012
Publication #:
Pub Dt:
07/25/2013
Title:
HIERARCHICAL CHANNEL MARKING IN A MEMORY SYSTEM
68
Patent #:
Issue Dt:
09/29/2015
Application #:
13354024
Filing Dt:
01/19/2012
Publication #:
Pub Dt:
07/25/2013
Title:
FINFET SEMICONDUCTOR DEVICES WITH IMPROVED SOURCE/DRAIN RESISTANCE AND METHODS OF MAKING SAME
69
Patent #:
Issue Dt:
11/17/2015
Application #:
13354070
Filing Dt:
01/19/2012
Publication #:
Pub Dt:
07/25/2013
Title:
SEMICONDUCTOR DEVICES WITH COPPER INTERCONNECTS AND METHODS FOR FABRICATING SAME
70
Patent #:
Issue Dt:
05/19/2015
Application #:
13354363
Filing Dt:
01/20/2012
Publication #:
Pub Dt:
07/25/2013
Title:
SEMICONDUCTOR DEVICE WITH A LOW-K SPACER AND METHOD OF FORMING THE SAME
71
Patent #:
Issue Dt:
06/16/2015
Application #:
13354705
Filing Dt:
01/20/2012
Publication #:
Pub Dt:
07/25/2013
Title:
BACKSIDE INTEGRATION OF RF FILTERS FOR RF FRONT END MODULES AND DESIGN STRUCTURE
72
Patent #:
Issue Dt:
07/16/2013
Application #:
13354715
Filing Dt:
01/20/2012
Publication #:
Pub Dt:
05/10/2012
Title:
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
73
Patent #:
Issue Dt:
01/06/2015
Application #:
13354739
Filing Dt:
01/20/2012
Publication #:
Pub Dt:
07/25/2013
Title:
METHOD OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE
74
Patent #:
Issue Dt:
08/06/2013
Application #:
13354883
Filing Dt:
01/20/2012
Publication #:
Pub Dt:
05/24/2012
Title:
METHOD FOR AUTOMATIC GENERATION OF THROUGHPUT MODELS FOR SEMICONDUCTOR TOOLS
75
Patent #:
Issue Dt:
11/19/2013
Application #:
13355065
Filing Dt:
01/20/2012
Publication #:
Pub Dt:
05/10/2012
Title:
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
76
Patent #:
Issue Dt:
08/06/2013
Application #:
13355099
Filing Dt:
01/20/2012
Publication #:
Pub Dt:
05/17/2012
Title:
METHOD AND DEVICE FOR SELECTIVELY ADDING TIMING MARGIN IN AN INTEGRATED CIRCUIT
77
Patent #:
Issue Dt:
10/23/2012
Application #:
13355221
Filing Dt:
01/20/2012
Publication #:
Pub Dt:
05/24/2012
Title:
METHOD OF MANUFACTURING A TRANSISTOR DEVICE HAVING ASYMMETRIC EMBEDDED STRAIN ELEMENTS
78
Patent #:
Issue Dt:
12/30/2014
Application #:
13356013
Filing Dt:
01/23/2012
Publication #:
Pub Dt:
05/17/2012
Title:
ELECTROMIGRATION RESISTANT VIA-TO-LINE INTERCONNECT
79
Patent #:
Issue Dt:
06/16/2015
Application #:
13356090
Filing Dt:
01/23/2012
Publication #:
Pub Dt:
07/25/2013
Title:
METHOD TO FORM SILICIDE CONTACT IN TRENCHES
80
Patent #:
Issue Dt:
01/08/2013
Application #:
13356681
Filing Dt:
01/24/2012
Title:
ANALYTIC EXPERIMENTAL ESTIMATOR FOR IMPACT OF VOLTAGE-OVERSHOOT OF VOLTAGE WAVEFORM ON DIELECTRIC FAILURE/BREAKDOWN
81
Patent #:
Issue Dt:
01/01/2013
Application #:
13357656
Filing Dt:
01/25/2012
Publication #:
Pub Dt:
05/31/2012
Title:
N-TYPE CARRIER ENHANCEMENT IN SEMICONDUCTORS
82
Patent #:
Issue Dt:
07/01/2014
Application #:
13358101
Filing Dt:
01/25/2012
Publication #:
Pub Dt:
08/02/2012
Title:
SOPHISTICATED GATE ELECTRODE STRUCTURES FORMED BY CAP LAYER REMOVAL WITH REDUCED LOSS OF EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL
83
Patent #:
Issue Dt:
04/16/2013
Application #:
13358105
Filing Dt:
01/25/2012
Publication #:
Pub Dt:
05/17/2012
Title:
SEMICONDUCTOR STRUCTURE AND METHOD OF DESIGNING SEMICONDUCTOR STRUCTURE TO AVOID HIGH VOLTAGE INITIATED LATCH-UP IN LOW VOLTAGE SECTORS
84
Patent #:
Issue Dt:
08/04/2015
Application #:
13358172
Filing Dt:
01/25/2012
Publication #:
Pub Dt:
07/25/2013
Title:
METHOD OF MANUFACTURING SWITCHING FILTERS AND DESIGN STRUCTURES
85
Patent #:
Issue Dt:
06/16/2015
Application #:
13358180
Filing Dt:
01/25/2012
Publication #:
Pub Dt:
07/25/2013
Title:
HETEROJUNCTION BIPOLAR TRANSISTOR WITH REDUCED SUB-COLLECTOR LENGTH, METHOD OF MANUFACTURE AND DESIGN STRUCTURE
86
Patent #:
Issue Dt:
04/02/2013
Application #:
13358963
Filing Dt:
01/26/2012
Publication #:
Pub Dt:
05/17/2012
Title:
3D OPTOELECTRONIC PACKAGING
87
Patent #:
Issue Dt:
12/17/2013
Application #:
13359032
Filing Dt:
01/26/2012
Publication #:
Pub Dt:
05/17/2012
Title:
METHOD OF FORMING MIM CAPACITOR STRUCTURE IN FEOL
88
Patent #:
Issue Dt:
07/09/2013
Application #:
13359100
Filing Dt:
01/26/2012
Publication #:
Pub Dt:
05/17/2012
Title:
3D OPTOELECTRONIC PACKAGING
89
Patent #:
Issue Dt:
05/06/2014
Application #:
13359107
Filing Dt:
01/26/2012
Publication #:
Pub Dt:
08/01/2013
Title:
CELL ARRAY AND DENSITY FEATURES WITH DECOUPLING CAPACITORS
90
Patent #:
Issue Dt:
01/27/2015
Application #:
13359177
Filing Dt:
01/26/2012
Publication #:
Pub Dt:
05/17/2012
Title:
SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE
91
Patent #:
Issue Dt:
03/11/2014
Application #:
13359197
Filing Dt:
01/26/2012
Publication #:
Pub Dt:
08/01/2013
Title:
Methods of Forming SRAM Devices Using Sidewall Image Transfer Techniques
92
Patent #:
Issue Dt:
11/19/2013
Application #:
13359454
Filing Dt:
01/26/2012
Publication #:
Pub Dt:
08/01/2013
Title:
SRAM WITH HYBRID FINFET AND PLANAR TRANSISTORS
93
Patent #:
Issue Dt:
07/16/2013
Application #:
13359634
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
05/31/2012
Title:
METHODS OF FABRICATING PASSIVE ELEMENT WITHOUT PLANARIZING AND RELATED SEMICONDUCTOR DEVICE
94
Patent #:
Issue Dt:
10/07/2014
Application #:
13359729
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
08/02/2012
Title:
ELECTRON BEAM SCULPTING OF TUNNELING JUNCTION FOR NANOPORE DNA SEQUENCING
95
Patent #:
Issue Dt:
01/27/2015
Application #:
13359970
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
05/24/2012
Title:
METHOD OF CREATING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER HAVING A UNIFORM THICKNESS
96
Patent #:
Issue Dt:
10/30/2012
Application #:
13360055
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
05/17/2012
Title:
PRODUCT CHIPS AND DIE WITH A FEATURE PATTERN THAT CONTAINS INFORMATION RELATING TO THE PRODUCT CHIP
97
Patent #:
Issue Dt:
01/28/2014
Application #:
13360083
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
08/01/2013
Title:
CIRCUIT VERIFICATION USING COMPUTATIONAL ALGEBRAIC GEOMETRY
98
Patent #:
Issue Dt:
02/05/2013
Application #:
13360203
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
05/17/2012
Title:
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
99
Patent #:
Issue Dt:
02/05/2013
Application #:
13360248
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
05/24/2012
Title:
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
100
Patent #:
Issue Dt:
02/05/2013
Application #:
13360270
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
05/24/2012
Title:
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
Assignor
1
Exec Dt:
11/27/2018
Assignee
1
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

Search Results as of: 05/08/2024 06:39 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT