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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:049490/0001   Pages: 892
Recorded: 11/29/2018
Conveyance: SECURITY AGREEMENT
1
Patent #:
Issue Dt:
02/05/2013
Application #:
13360277
Filing Dt:
01/27/2012
Publication #:
Pub Dt:
05/24/2012
Title:
ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION
2
Patent #:
Issue Dt:
12/24/2013
Application #:
13361004
Filing Dt:
01/30/2012
Publication #:
Pub Dt:
08/01/2013
Title:
SEMICONDUCTOR SUBSTRATES USING BANDGAP MATERIAL BETWEEN III-V CHANNEL MATERIAL AND INSULATOR LAYER
3
Patent #:
Issue Dt:
03/05/2013
Application #:
13361051
Filing Dt:
01/30/2012
Publication #:
Pub Dt:
05/17/2012
Title:
ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME
4
Patent #:
Issue Dt:
05/21/2013
Application #:
13361057
Filing Dt:
01/30/2012
Publication #:
Pub Dt:
05/31/2012
Title:
SOFT ERROR RATE MITIGATION BY INTERCONNECT STRUCTURE
5
Patent #:
Issue Dt:
08/20/2013
Application #:
13361595
Filing Dt:
01/30/2012
Publication #:
Pub Dt:
08/01/2013
Title:
METHODS FOR QUANTITATIVELY EVALUATING THE QUALITY OF DOUBLE PATTERNING TECHNOLOGY-COMPLIANT LAYOUTS
6
Patent #:
Issue Dt:
01/08/2013
Application #:
13362019
Filing Dt:
01/31/2012
Publication #:
Pub Dt:
05/31/2012
Title:
FIELD EFFECT TRANSISTOR WITH CHANNEL REGION EDGE AND CENTER PORTIONS HAVING DIFFERENT BAND STRUCTURES FOR SUPPRESSED CORNER LEAKAGE
7
Patent #:
Issue Dt:
01/29/2013
Application #:
13362043
Filing Dt:
01/31/2012
Publication #:
Pub Dt:
05/24/2012
Title:
METHOD OF PROGRAMMING ELECTRICAL ANTIFUSE
8
Patent #:
Issue Dt:
09/23/2014
Application #:
13362366
Filing Dt:
01/31/2012
Publication #:
Pub Dt:
08/01/2013
Title:
SUPERCONDUCTING QUANTUM CIRCUIT HAVING A RESONANT CAVITY THERMALIZED WITH METAL COMPONENTS
9
Patent #:
Issue Dt:
07/09/2013
Application #:
13362398
Filing Dt:
01/31/2012
Publication #:
Pub Dt:
08/01/2013
Title:
METHODS OF EPITAXIAL FINFET
10
Patent #:
Issue Dt:
09/01/2015
Application #:
13362635
Filing Dt:
01/31/2012
Publication #:
Pub Dt:
08/01/2013
Title:
BRUSH CLEANING SYSTEM
11
Patent #:
Issue Dt:
03/22/2016
Application #:
13362754
Filing Dt:
01/31/2012
Publication #:
Pub Dt:
08/01/2013
Title:
PROBABLISTIC SUBSURFACE MODELING FOR IMPROVED DRILL CONTROL AND REAL-TIME CORRECTION
12
Patent #:
Issue Dt:
07/08/2014
Application #:
13362763
Filing Dt:
01/31/2012
Publication #:
Pub Dt:
05/24/2012
Title:
PERFORMANCE ENHANCEMENT IN PMOS AND NMOS TRANSISTORS ON THE BASIS OF SILICON/CARBON MATERIAL
13
Patent #:
Issue Dt:
11/05/2013
Application #:
13362862
Filing Dt:
01/31/2012
Publication #:
Pub Dt:
05/24/2012
Title:
LOW TEMPERATURE MELT-PROCESSING OF ORGANIC-INORGANIC HYBRID
14
Patent #:
Issue Dt:
10/22/2013
Application #:
13363465
Filing Dt:
02/01/2012
Publication #:
Pub Dt:
08/02/2012
Title:
FILM FOR PACKAGING PRODUCT, ESPECIALLY AN ENVELOPE
15
Patent #:
Issue Dt:
06/18/2013
Application #:
13363549
Filing Dt:
02/01/2012
Publication #:
Pub Dt:
05/24/2012
Title:
THERMALLY INSULATED PHASE MATERIAL CELLS
16
Patent #:
Issue Dt:
01/01/2013
Application #:
13363944
Filing Dt:
02/01/2012
Publication #:
Pub Dt:
07/26/2012
Title:
RECESSED GATE CHANNEL WITH LOW VT CORNER
17
Patent #:
Issue Dt:
01/29/2013
Application #:
13363995
Filing Dt:
02/01/2012
Publication #:
Pub Dt:
05/24/2012
Title:
TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES
18
Patent #:
Issue Dt:
03/18/2014
Application #:
13364002
Filing Dt:
02/01/2012
Publication #:
Pub Dt:
05/24/2012
Title:
3D INTEGRATED CIRCUITS STRUCTURE
19
Patent #:
Issue Dt:
09/17/2013
Application #:
13364153
Filing Dt:
02/01/2012
Publication #:
Pub Dt:
05/24/2012
Title:
THERMALLY INSULATED PHASE CHANGE MATERIAL MEMORY CELLS
20
Patent #:
Issue Dt:
03/11/2014
Application #:
13364171
Filing Dt:
02/01/2012
Publication #:
Pub Dt:
05/24/2012
Title:
GRID-LINE-FREE CONTACT FOR A PHOTOVOLTAIC CELL
21
Patent #:
Issue Dt:
11/19/2013
Application #:
13364273
Filing Dt:
02/01/2012
Publication #:
Pub Dt:
06/14/2012
Title:
LOCAL BOTTOM GATES FOR GRAPHENE AND CARBON NANOTUBE DEVICES
22
Patent #:
Issue Dt:
11/26/2013
Application #:
13364311
Filing Dt:
02/01/2012
Publication #:
Pub Dt:
08/01/2013
Title:
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
23
Patent #:
Issue Dt:
01/01/2013
Application #:
13364346
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
08/02/2012
Title:
IMPLEMENTING MULTIPLE DIFFERENT TYPES OF DIES FOR MEMORY STACKING
24
Patent #:
Issue Dt:
12/04/2012
Application #:
13364494
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
05/31/2012
Title:
TUNNEL JUNCTION VIA
25
Patent #:
Issue Dt:
07/02/2013
Application #:
13364569
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
05/31/2012
Title:
DESIGN STRUCTURE, STRUCTURE AND METHOD FOR PROVIDING AN ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE
26
Patent #:
Issue Dt:
02/03/2015
Application #:
13364663
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
05/24/2012
Title:
LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE
27
Patent #:
Issue Dt:
11/03/2015
Application #:
13364671
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
08/08/2013
Title:
METHODS OF FORMING METAL NITRIDE MATERIALS
28
Patent #:
Issue Dt:
11/18/2014
Application #:
13364753
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
05/31/2012
Title:
SEMICONDUCTOR DEVICES HAVING TENSILE AND/OR COMPRESSIVE STRESS AND METHODS OF MANUFACTURING
29
Patent #:
Issue Dt:
06/03/2014
Application #:
13364759
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
02/07/2013
Title:
METHOD AND STRUCTURE FOR ULTRA-HIGH DENSITY, HIGH DATA RATE FERROELECTRIC STORAGE DISK TECHNOLOGY USING STABILIZATION BY A SURFACE CONDUCTING LAYER
30
Patent #:
Issue Dt:
08/13/2013
Application #:
13364976
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
08/08/2013
Title:
ALIGNMENT TOLERANT SEMICONDUCTOR CONTACT AND METHOD
31
Patent #:
Issue Dt:
11/12/2013
Application #:
13365030
Filing Dt:
02/02/2012
Publication #:
Pub Dt:
08/08/2013
Title:
INTEGRATED CIRCUIT CONTACT STRUCTURE AND METHOD
32
Patent #:
Issue Dt:
04/16/2013
Application #:
13365505
Filing Dt:
02/03/2012
Publication #:
Pub Dt:
05/31/2012
Title:
SILICON BASED MICROCHANNEL COOLING AND ELECTRICAL PACKAGE
33
Patent #:
Issue Dt:
12/31/2013
Application #:
13365577
Filing Dt:
02/03/2012
Publication #:
Pub Dt:
05/31/2012
Title:
NANOFLUIDIC FIELD EFFECT TRANSISTOR BASED ON SURFACE CHARGE MODULATED NANOCHANNEL
34
Patent #:
Issue Dt:
03/19/2013
Application #:
13365764
Filing Dt:
02/03/2012
Publication #:
Pub Dt:
08/09/2012
Title:
SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL)
35
Patent #:
Issue Dt:
12/17/2013
Application #:
13365961
Filing Dt:
02/03/2012
Publication #:
Pub Dt:
08/23/2012
Title:
ESTIMATING POWER CONSUMPTION OF AN ELECTRONIC CIRCUIT
36
Patent #:
Issue Dt:
01/07/2014
Application #:
13365989
Filing Dt:
02/03/2012
Publication #:
Pub Dt:
08/23/2012
Title:
GATE CONFIGURATION DETERMINATION AND SELECTION FROM STANDARD CELL LIBRARY
37
Patent #:
Issue Dt:
05/07/2013
Application #:
13366804
Filing Dt:
02/06/2012
Publication #:
Pub Dt:
05/31/2012
Title:
WORD-LINE LEVEL SHIFT CIRCUIT
38
Patent #:
Issue Dt:
03/19/2013
Application #:
13367646
Filing Dt:
02/07/2012
Publication #:
Pub Dt:
05/31/2012
Title:
SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON AN SOI SUBSTRATE
39
Patent #:
Issue Dt:
12/02/2014
Application #:
13367895
Filing Dt:
02/07/2012
Publication #:
Pub Dt:
08/08/2013
Title:
INDUCTORS AND WIRING STRUCTURES FABRICATED WITH LIMITED WIRING MATERIAL
40
Patent #:
Issue Dt:
08/11/2015
Application #:
13368750
Filing Dt:
02/08/2012
Publication #:
Pub Dt:
08/08/2013
Title:
Interface Engineering to Optimize Metal-III-V Contacts
41
Patent #:
Issue Dt:
01/28/2014
Application #:
13368901
Filing Dt:
02/08/2012
Publication #:
Pub Dt:
06/07/2012
Title:
Method of Fabricating Self-Aligned Nanotube Field Effect Transistor
42
Patent #:
Issue Dt:
02/25/2014
Application #:
13368918
Filing Dt:
02/08/2012
Publication #:
Pub Dt:
08/08/2013
Title:
IMPLEMENTING LOW POWER WRITE DISABLED LOCAL EVALUATION FOR SRAM
43
Patent #:
Issue Dt:
12/24/2013
Application #:
13369246
Filing Dt:
02/08/2012
Publication #:
Pub Dt:
08/08/2013
Title:
SELF-ALIGNED PROCESS TO FABRICATE A MEMORY CELL ARRAY WITH A SURROUNDING-GATE ACCESS TRANSISTOR
44
Patent #:
Issue Dt:
01/06/2015
Application #:
13369261
Filing Dt:
02/08/2012
Publication #:
Pub Dt:
08/08/2013
Title:
SOI BIPOLAR JUNCTION TRANSISTOR WITH SUBSTRATE BIAS VOLTAGES
45
Patent #:
Issue Dt:
12/25/2012
Application #:
13369273
Filing Dt:
02/08/2012
Publication #:
Pub Dt:
06/07/2012
Title:
SYSTEM TO IMPROVE CORELESS PACKAGE CONNECTIONS
46
Patent #:
Issue Dt:
06/16/2015
Application #:
13369382
Filing Dt:
02/09/2012
Publication #:
Pub Dt:
08/15/2013
Title:
JUNCTION BUTTING ON SOI BY RAISED EPITAXIAL STRUCTURE AND METHOD
47
Patent #:
Issue Dt:
01/15/2013
Application #:
13369482
Filing Dt:
02/09/2012
Title:
METHODS OF CONTROLLING FIN HEIGHT OF FINFET DEVICES BY PERFORMING A DIRECTIONAL DEPOSITION PROCESS
48
Patent #:
Issue Dt:
09/25/2012
Application #:
13369592
Filing Dt:
02/09/2012
Publication #:
Pub Dt:
05/31/2012
Title:
CIRCUIT STRUCTURES AND METHODS WITH BEOL LAYERS CONFIGURED TO BLOCK ELECTROMAGNETIC EDGE INTERFERENCE
49
Patent #:
Issue Dt:
06/16/2015
Application #:
13369655
Filing Dt:
02/09/2012
Publication #:
Pub Dt:
06/07/2012
Title:
SELF-ALIGNED LOWER BOTTOM ELECTRODE
50
Patent #:
Issue Dt:
05/27/2014
Application #:
13369872
Filing Dt:
02/09/2012
Publication #:
Pub Dt:
08/15/2013
Title:
INTEGRATED TRANSFORMERS
51
Patent #:
Issue Dt:
11/19/2013
Application #:
13369938
Filing Dt:
02/09/2012
Publication #:
Pub Dt:
08/15/2013
Title:
METHODS FOR ANALYZING DESIGN RULES
52
Patent #:
Issue Dt:
04/02/2013
Application #:
13370144
Filing Dt:
02/09/2012
Title:
LOW-SWING SIGNALING SCHEME FOR DATA COMMUNICATION
53
Patent #:
Issue Dt:
07/02/2013
Application #:
13370722
Filing Dt:
02/10/2012
Title:
Methods of FinFET Height Control
54
Patent #:
Issue Dt:
01/14/2014
Application #:
13370898
Filing Dt:
02/10/2012
Publication #:
Pub Dt:
06/07/2012
Title:
STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES
55
Patent #:
Issue Dt:
09/16/2014
Application #:
13370944
Filing Dt:
02/10/2012
Publication #:
Pub Dt:
08/23/2012
Title:
COMPLEMENTARY TRANSISTORS COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND EPITAXIALLY FORMED SEMICONDUCTOR MATERIALS IN THE DRAIN AND SOURCE AREAS
56
Patent #:
Issue Dt:
05/13/2014
Application #:
13371049
Filing Dt:
02/10/2012
Publication #:
Pub Dt:
08/23/2012
Title:
SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS AND A REPLACEMENT GATE ELECTRODE STRUCTURE
57
Patent #:
Issue Dt:
10/22/2013
Application #:
13371430
Filing Dt:
02/11/2012
Publication #:
Pub Dt:
08/15/2013
Title:
FORMING METAL PREFORMS AND METAL BALLS
58
Patent #:
Issue Dt:
10/29/2013
Application #:
13371493
Filing Dt:
02/13/2012
Publication #:
Pub Dt:
08/15/2013
Title:
DUAL-METAL SELF-ALIGNED WIRES AND VIAS
59
Patent #:
Issue Dt:
01/13/2015
Application #:
13371585
Filing Dt:
02/13/2012
Publication #:
Pub Dt:
08/15/2013
Title:
Critical Dimension and Pattern Recognition Structures for Devices Manufactured Using Double Patterning Techniques
60
Patent #:
Issue Dt:
01/13/2015
Application #:
13371605
Filing Dt:
02/13/2012
Publication #:
Pub Dt:
08/15/2013
Title:
SELF-ALIGNED EMITTER-BASE REGION
61
Patent #:
Issue Dt:
12/11/2012
Application #:
13371840
Filing Dt:
02/13/2012
Publication #:
Pub Dt:
06/07/2012
Title:
TECHNIQUES FOR FORMING SOLDER BUMP INTERCONNECTS
62
Patent #:
Issue Dt:
04/15/2014
Application #:
13372058
Filing Dt:
02/13/2012
Publication #:
Pub Dt:
06/07/2012
Title:
MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION
63
Patent #:
Issue Dt:
08/26/2014
Application #:
13372085
Filing Dt:
02/13/2012
Publication #:
Pub Dt:
08/15/2013
Title:
DEVICES HAVING BIAS TEMPERATURE INSTABILITY COMPENSATION
64
Patent #:
Issue Dt:
04/15/2014
Application #:
13372466
Filing Dt:
02/13/2012
Publication #:
Pub Dt:
03/28/2013
Title:
HIGH-FIDELITY DEVICE FOR SINGLE-SHOT PULSE CONTRAST MEASUREMENT BASED ON QUASI-PHASE-MATCHING (QPM)
65
Patent #:
Issue Dt:
09/16/2014
Application #:
13372604
Filing Dt:
02/14/2012
Publication #:
Pub Dt:
08/23/2012
Title:
SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS
66
Patent #:
Issue Dt:
08/13/2013
Application #:
13372714
Filing Dt:
02/14/2012
Publication #:
Pub Dt:
06/07/2012
Title:
OMEGA SHAPED NANOWIRE TUNNEL FIELD EFFECT TRANSISTORS
67
Patent #:
Issue Dt:
03/25/2014
Application #:
13372719
Filing Dt:
02/14/2012
Publication #:
Pub Dt:
06/14/2012
Title:
OMEGA SHAPED NANOWIRE FIELD EFFECT TRANSISTORS
68
Patent #:
Issue Dt:
02/18/2014
Application #:
13372837
Filing Dt:
02/14/2012
Publication #:
Pub Dt:
08/23/2012
Title:
FIN-TRANSISTOR FORMED ON A PATTERNED STI REGION BY LATE FIN ETCH
69
Patent #:
Issue Dt:
04/28/2015
Application #:
13372901
Filing Dt:
02/14/2012
Publication #:
Pub Dt:
08/23/2012
Title:
Technique for Reducing Plasma-Induced Etch Damage During the Formation of Vias in Interlayer Dielectrics by Modified RF Power Ramp-Up
70
Patent #:
Issue Dt:
11/15/2016
Application #:
13372974
Filing Dt:
02/14/2012
Publication #:
Pub Dt:
06/07/2012
Title:
SILICON WAFER BASED STRUCTURE FOR HETEROSTRUCTURE SOLAR CELLS
71
Patent #:
Issue Dt:
09/17/2013
Application #:
13396291
Filing Dt:
02/14/2012
Publication #:
Pub Dt:
06/14/2012
Title:
FINFET WITH REDUCED GATE TO FIN OVERLAY SENSITIVITY
72
Patent #:
Issue Dt:
08/27/2013
Application #:
13396998
Filing Dt:
02/15/2012
Publication #:
Pub Dt:
06/07/2012
Title:
Template-Registered DiBlock Copolymer Mask for MRAM Device Formation
73
Patent #:
Issue Dt:
10/16/2012
Application #:
13397004
Filing Dt:
02/15/2012
Publication #:
Pub Dt:
08/09/2012
Title:
ENHANCED ELECTROMIGRATION RESISTANCE IN TSV STRUCTURE AND DESIGN
74
Patent #:
Issue Dt:
03/18/2014
Application #:
13397345
Filing Dt:
02/15/2012
Publication #:
Pub Dt:
08/30/2012
Title:
SOI Semiconductor Device Comprising a Substrate Diode with Reduced Metal Silicide Leakage
75
Patent #:
Issue Dt:
03/11/2014
Application #:
13398070
Filing Dt:
02/16/2012
Publication #:
Pub Dt:
06/14/2012
Title:
METAL CAP WITH ULTRA-LOW k DIELECTRIC MATERIAL FOR CIRCUIT INTERCONNECT APPLICATIONS
76
Patent #:
Issue Dt:
08/11/2015
Application #:
13398151
Filing Dt:
02/16/2012
Publication #:
Pub Dt:
08/22/2013
Title:
MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE
77
Patent #:
Issue Dt:
08/05/2014
Application #:
13398190
Filing Dt:
02/16/2012
Publication #:
Pub Dt:
08/22/2013
Title:
OPTICAL RECEIVER USING INFINITE IMPULSE RESPONSE DECISION FEEDBACK EQUALIZATION
78
Patent #:
Issue Dt:
01/28/2014
Application #:
13398339
Filing Dt:
02/16/2012
Publication #:
Pub Dt:
08/22/2013
Title:
NON-PLANAR MOSFET STRUCTURES WITH ASYMMETRIC RECESSED SOURCE DRAINS AND METHODS FOR MAKING THE SAME
79
Patent #:
Issue Dt:
09/09/2014
Application #:
13398408
Filing Dt:
02/16/2012
Publication #:
Pub Dt:
06/14/2012
Title:
STRUCTURE AND LAYOUT OF A FET PRIME CELL
80
Patent #:
Issue Dt:
05/27/2014
Application #:
13398481
Filing Dt:
02/16/2012
Publication #:
Pub Dt:
06/14/2012
Title:
3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL
81
Patent #:
Issue Dt:
02/12/2013
Application #:
13398490
Filing Dt:
02/16/2012
Title:
SOFT-BOUNDED HIERARCHICAL SYNTHESIS
82
Patent #:
Issue Dt:
01/14/2014
Application #:
13398505
Filing Dt:
02/16/2012
Publication #:
Pub Dt:
06/21/2012
Title:
3D INTEGRATED CIRCUIT DEVICE FABRICATION WITH PRECISELY CONTROLLABLE SUBSTRATE REMOVAL
83
Patent #:
Issue Dt:
10/08/2013
Application #:
13398518
Filing Dt:
02/16/2012
Publication #:
Pub Dt:
06/07/2012
Title:
ELECTRONICALLY SCANNABLE MULTIPLEXING DEVICE
84
Patent #:
Issue Dt:
06/16/2015
Application #:
13398875
Filing Dt:
02/17/2012
Publication #:
Pub Dt:
08/22/2013
Title:
Lateral-Dimension-Reducing Metallic Hard Mask Etch
85
Patent #:
Issue Dt:
03/18/2014
Application #:
13398991
Filing Dt:
02/17/2012
Publication #:
Pub Dt:
08/22/2013
Title:
DRY ETCH POLYSILICON REMOVAL FOR REPLACEMENT GATES
86
Patent #:
Issue Dt:
04/22/2014
Application #:
13399054
Filing Dt:
02/17/2012
Publication #:
Pub Dt:
08/22/2013
Title:
CAPACITIVE LEVEL-SHIFTING CIRCUITS AND METHODS FOR ADDING DC OFFSETS TO OUTPUT OF CURRENT-INTEGRATING AMPLIFIER
87
Patent #:
Issue Dt:
02/24/2015
Application #:
13399266
Filing Dt:
02/17/2012
Publication #:
Pub Dt:
08/22/2013
Title:
METAL FUSE STRUCTURE FOR IMPROVED PROGRAMMING CAPABILITY
88
Patent #:
Issue Dt:
12/04/2012
Application #:
13399612
Filing Dt:
02/17/2012
Publication #:
Pub Dt:
06/14/2012
Title:
EMBEDDED NANOPARTICLE FILMS AND METHOD FOR THEIR FORMATION IN SELECTIVE AREAS ON A SURFACE
89
Patent #:
Issue Dt:
09/24/2013
Application #:
13399674
Filing Dt:
02/17/2012
Publication #:
Pub Dt:
08/22/2013
Title:
METHODS FOR FABRICATING INTEGRATED CIRCUITS
90
Patent #:
Issue Dt:
02/24/2015
Application #:
13399675
Filing Dt:
02/17/2012
Publication #:
Pub Dt:
08/22/2013
Title:
ANALOG SIGNAL CURRENT INTEGRATORS WITH TUNABLE PEAKING FUNCTION
91
Patent #:
Issue Dt:
03/25/2014
Application #:
13399727
Filing Dt:
02/17/2012
Publication #:
Pub Dt:
08/22/2013
Title:
METHODS FOR FABRICATING SEMICONDUCTOR DEVICES WITH ISOLATION REGIONS HAVING UNIFORM STEPHEIGHTS
92
Patent #:
Issue Dt:
02/04/2014
Application #:
13400407
Filing Dt:
02/20/2012
Publication #:
Pub Dt:
08/22/2013
Title:
METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES
93
Patent #:
Issue Dt:
10/08/2013
Application #:
13400445
Filing Dt:
02/20/2012
Publication #:
Pub Dt:
08/22/2013
Title:
METHODS FOR DECOMPOSING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING DECOMPOSED PATTERNS
94
Patent #:
Issue Dt:
07/30/2013
Application #:
13400610
Filing Dt:
02/21/2012
Publication #:
Pub Dt:
08/22/2013
Title:
INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES
95
Patent #:
Issue Dt:
01/07/2014
Application #:
13400900
Filing Dt:
02/21/2012
Publication #:
Pub Dt:
06/28/2012
Title:
REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE
96
Patent #:
Issue Dt:
06/10/2014
Application #:
13400981
Filing Dt:
02/21/2012
Publication #:
Pub Dt:
08/22/2013
Title:
REPLACEMENT GATE APPROACH FOR HIGH-K METAL GATE STACKS BY USING A MULTI-LAYER CONTACT LEVEL
97
Patent #:
Issue Dt:
07/22/2014
Application #:
13401064
Filing Dt:
02/21/2012
Publication #:
Pub Dt:
08/22/2013
Title:
TRANSISTOR HAVING A MONOCRYSTALLINE CENTER SECTION AND A POLYCRYSTALLINE OUTER SECTION, AND NARROW IN-SUBSTRATE COLLECTOR REGION FOR REDUCED BASE-COLLECTOR JUNCTION CAPACITANCE
98
Patent #:
Issue Dt:
07/08/2014
Application #:
13401368
Filing Dt:
02/21/2012
Publication #:
Pub Dt:
08/22/2013
Title:
REFERENCE GENERATOR WITH PROGRAMMABLE M AND B PARAMETERS AND METHODS OF USE
99
Patent #:
Issue Dt:
09/25/2012
Application #:
13401967
Filing Dt:
02/22/2012
Publication #:
Pub Dt:
06/14/2012
Title:
ULTRATHIN SPACER FORMATION FOR CARBON-BASED FET
100
Patent #:
Issue Dt:
12/23/2014
Application #:
13402068
Filing Dt:
02/22/2012
Publication #:
Pub Dt:
08/22/2013
Title:
DUAL HARD MASK LITHOGRAPHY PROCESS
Assignor
1
Exec Dt:
11/27/2018
Assignee
1
1100 NORTH MARKET STREET
WILMINGTON, DELAWARE 19801
Correspondence name and address
CT CORPORATION
4400 EASTON COMMONS WAY
SUITE 125
COLUMBUS, OH 43219

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