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01/13/2015
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13747529
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01/23/2013
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Pub Dt:
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07/24/2014
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Title:
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COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DYNAMIC RANDOM ACCESS MEMORY (DRAM) CELL WITH SENSE AMPLIFIER
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01/26/2016
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13747579
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01/23/2013
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07/24/2014
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Title:
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INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH MULTIPLE EMBEDDED INTERCONNECT CONNECTION TO SAME THROUGH-SEMICONDUCTOR VIA
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03/15/2016
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13747798
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01/23/2013
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05/23/2013
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Title:
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METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS
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06/23/2015
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13747842
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01/23/2013
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12/19/2013
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09/16/2014
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13747907
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01/23/2013
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07/24/2014
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Title:
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METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A VERTICAL NANOWIRE
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02/25/2014
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13748038
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01/23/2013
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05/30/2013
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HYDROGEN BARRIER LINER FOR FERRO-ELECTRIC RANDOM ACCESS MEMORY (FRAM) CHIP
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02/16/2016
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13748048
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01/23/2013
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07/24/2014
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NOTCH FILTER STRUCTURE WITH OPEN STUBS IN SEMICONDUCTOR SUBSTRATE AND DESIGN STRUCTURE
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09/12/2017
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13748159
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01/23/2013
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07/24/2014
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INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME WITH METAL LAYER CONNECTION TO THROUGH-SEMICONDUCTOR VIA
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11/25/2014
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13748197
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01/23/2013
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07/24/2014
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Title:
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SELF-ALIGNED BIOSENSORS WITH ENHANCED SENSITIVITY
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12/16/2014
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13748226
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01/23/2013
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05/30/2013
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Title:
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TEMPERATURE CONTROL DEVICE FOR OPTOELECTRONIC DEVICES
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06/16/2015
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13748662
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01/24/2013
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05/30/2013
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Title:
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STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING
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01/13/2015
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13748821
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01/24/2013
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07/24/2014
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Title:
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IN-SITU THERMOELECTRIC COOLING
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09/30/2014
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13749146
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01/24/2013
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05/30/2013
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Title:
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METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY
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11/25/2014
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13749744
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01/25/2013
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06/06/2013
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Title:
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CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE
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09/16/2014
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13749745
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01/25/2013
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06/06/2013
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Title:
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CHIP IDENTIFICATION FOR ORGANIC LAMINATE PACKAGING AND METHODS OF MANUFACTURE
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09/16/2014
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13749851
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01/25/2013
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12/05/2013
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Title:
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POWER/PERFORMANCE OPTIMIZATION THROUGH TEMPERATURE/VOLTAGE CONTROL
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09/16/2014
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13749925
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01/25/2013
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Pub Dt:
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07/31/2014
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Title:
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POWER/PERFORMANCE OPTIMIZATION THROUGH CONTINUOUSLY VARIABLE TEMPERATURE-BASED VOLTAGE CONTROL
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12/17/2013
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13750497
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01/25/2013
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05/30/2013
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Title:
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CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR
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12/01/2015
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13750751
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01/25/2013
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07/31/2014
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Title:
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INTERPOLATION TECHNIQUES USED FOR TIME ALIGNMENT OF MULTIPLE SIMULATION MODELS
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11/18/2014
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13751238
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01/28/2013
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07/31/2014
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Title:
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METHOD OF FORMING ELECTRONIC FUSE LINE WITH MODIFIED CAP
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12/30/2014
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13751361
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01/28/2013
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06/06/2013
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Title:
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STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS
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06/23/2015
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13751490
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01/28/2013
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07/31/2014
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Title:
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Nanowire Capacitor for Bidirectional Operation
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06/16/2015
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13751799
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01/28/2013
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05/15/2014
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Title:
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SELECTIVE GALLIUM NITRIDE REGROWTH ON (100) SILICON
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05/26/2015
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13752567
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01/29/2013
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Pub Dt:
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06/06/2013
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Title:
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STRUCTURE AND METHOD FOR REPLACEMENT GATE MOSFET WITH SELF-ALIGNED CONTACT USING SACRIFICIAL MANDREL DIELECTRIC
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02/10/2015
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13752737
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01/29/2013
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07/31/2014
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Title:
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ORGANIC MODULE EMI SHIELDING STRUCTURES AND METHODS
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04/05/2016
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13752948
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01/29/2013
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06/06/2013
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Title:
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EFFICIENT DATA EXTRACTION BY A REMOTE APPLICATION
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09/09/2014
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13753269
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01/29/2013
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07/31/2014
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METHODS FOR FABRICATING ELECTRICALLY-ISOLATED FINFET SEMICONDUCTOR DEVICES
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01/13/2015
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13753989
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01/30/2013
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07/31/2014
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Title:
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PROCESS VARIATION SKEW IN AN SRAM COLUMN ARCHITECTURE
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04/07/2015
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13755030
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01/31/2013
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07/31/2014
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Title:
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ELECTRONIC FUSE HAVING AN INSULATION LAYER
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04/29/2014
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13755192
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01/31/2013
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06/06/2013
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BIPOLAR JUNCTION TRANSISTOR WITH A SELF-ALIGNED EMITTER AND BASE
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08/26/2014
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13755246
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01/31/2013
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07/31/2014
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METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING CONFINED EPITAXIAL GROWTH REGIONS
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12/30/2014
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13755374
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01/31/2013
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07/31/2014
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AUTOMATED DESIGN LAYOUT PATTERN CORRECTION BASED ON CONTEXT-AWARE PATTERNS
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09/29/2015
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13755726
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01/31/2013
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06/19/2014
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ANALYSIS OF CHIP-MEAN VARIATION AND INDEPENDENT INTRA-DIE VARIATION FOR CHIP YIELD DETERMINATION
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10/21/2014
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13755807
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01/31/2013
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06/06/2013
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METHODS FOR FORMING SEMICONDUCTOR STRUCTURES USING SELECTIVELY-FORMED SIDEWALL SPACERS
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11/04/2014
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13756689
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02/01/2013
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08/07/2014
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DOUBLE-PATTERN GATE FORMATION PROCESSING WITH CRITICAL DIMENSION CONTROL
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03/25/2014
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13756981
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02/01/2013
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06/06/2013
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METAL-CONTAMINATION-FREE THROUGH-SUBSTRATE VIA STRUCTURE
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09/17/2013
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13757040
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02/01/2013
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06/06/2013
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PARALLEL OPTICAL TRANSCEIVER MODULE
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05/06/2014
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13757069
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02/01/2013
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METHODS OF FORMING FINS FOR A FINFET SEMICONDUCTOR DEVICE USING A MANDREL OXIDATION PROCESS
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05/12/2015
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13757205
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02/01/2013
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Pub Dt:
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08/07/2014
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Title:
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METHODS OF FORMING SILICON/GERMANIUM PROTECTION LAYER ABOVE SOURCE/DRAIN REGIONS OF A TRANSISTOR AND A DEVICE HAVING SUCH A PROTECTION LAYER
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09/02/2014
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13757218
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02/01/2013
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08/07/2014
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PATTERN-BASED REPLACEMENT FOR LAYOUT REGULARIZATION
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03/10/2015
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13757286
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02/01/2013
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08/07/2014
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METHODS FOR OPTICAL PROXIMITY CORRECTION IN THE DESIGN AND FABRICATION OF INTEGRATED CIRCUITS
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09/16/2014
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13757504
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02/01/2013
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08/07/2014
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METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING EMBEDDED ELECTRICAL INTERCONNECTS
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02/17/2015
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13757961
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02/04/2013
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08/07/2014
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TRENCH ISOLATION FOR BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY
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05/06/2014
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13758204
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02/04/2013
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Pub Dt:
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06/13/2013
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BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES
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06/14/2016
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13758225
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02/04/2013
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08/07/2014
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METHODS OF FORMING SUBSTRATES COMPRISED OF DIFFERENT SEMICONDUCTOR MATERIALS AND THE RESULTING DEVICE
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07/15/2014
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13758386
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02/04/2013
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06/06/2013
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SOLDER BUMP CONNECTIONS
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11/04/2014
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13759102
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02/05/2013
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06/13/2013
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Title:
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METHOD FOR COMPENSATING FOR VARIATIONS IN STRUCTURES OF AN INTEGRATED CIRCUIT
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08/20/2013
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13759146
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02/05/2013
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06/13/2013
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METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR
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12/30/2014
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13759156
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02/05/2013
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Pub Dt:
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08/07/2014
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INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH LOWER CONTACT RESISTANCE AND REDUCED PARASITIC CAPACITANCE AND METHODS FOR FABRICATING THE SAME
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02/03/2015
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13759209
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02/05/2013
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08/07/2014
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INTEGRATED CIRCUITS HAVING REPLACEMENT GATE STRUCTURES AND METHODS FOR FABRICATING THE SAME
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11/04/2014
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13759297
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02/05/2013
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08/07/2014
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OPTIMIZED OPTICAL PROXIMITY CORRECTION HANDLING FOR LITHOGRAPHIC FILLS
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06/09/2015
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13759311
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02/05/2013
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08/07/2014
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Wide Bandwidth Resonant Global Clock Distribution
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09/24/2013
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13759641
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02/05/2013
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Pub Dt:
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08/29/2013
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Title:
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PAD-LESS GATE-ALL AROUND SEMICONDUCTOR NANOWIRE FETS ON BULK SEMICONDUCTOR WAFERS
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11/04/2014
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13759649
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02/05/2013
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07/25/2013
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IMAGER MICROLENS STRUCTURE HAVING INTERFACIAL REGION FOR ADHESION OF PROTECTIVE LAYER
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04/22/2014
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13759697
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02/05/2013
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Title:
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VARIABLE RESISTANCE SWITCH FOR WIDE BANDWIDTH RESONANT GLOBAL CLOCK DISTRIBUTION
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04/29/2014
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13760190
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02/06/2013
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06/13/2013
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DATA SECURITY FOR DYNAMIC RANDOM ACCESS MEMORY USING BODY BIAS TO CLEAR DATA AT POWER-UP
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07/21/2015
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13760277
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02/06/2013
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Pub Dt:
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08/07/2014
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Title:
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PLANAR SEMICONDUCTOR GROWTH ON III-V MATERIAL
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Patent #:
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Issue Dt:
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04/15/2014
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Application #:
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13760373
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Filing Dt:
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02/06/2013
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Publication #:
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Pub Dt:
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06/06/2013
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Title:
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SUPERFILLED METAL CONTACT VIAS FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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02/04/2014
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Application #:
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13760391
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Filing Dt:
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02/06/2013
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Publication #:
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Pub Dt:
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06/13/2013
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Title:
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CORROSION SENSORS
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13760488
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Filing Dt:
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02/06/2013
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Publication #:
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Pub Dt:
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08/07/2014
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Title:
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ELECTRONIC FUSE HAVING A DAMAGED REGION
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Patent #:
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Issue Dt:
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12/09/2014
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Application #:
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13760571
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Filing Dt:
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02/06/2013
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Publication #:
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Pub Dt:
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08/07/2014
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Title:
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RETARGETING SEMICONDUCTOR DEVICE SHAPES FOR MULTIPLE PATTERNING PROCESSES
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Patent #:
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Issue Dt:
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11/12/2013
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Application #:
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13761358
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Filing Dt:
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02/07/2013
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Publication #:
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Pub Dt:
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06/13/2013
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Title:
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HIGH FREQUENCY QUADRATURE PLL CIRCUIT AND METHOD
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Patent #:
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Issue Dt:
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11/17/2015
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Application #:
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13761430
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Filing Dt:
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02/07/2013
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Publication #:
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Pub Dt:
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08/07/2014
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Title:
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DIODE STRUCTURE AND METHOD FOR FINFET TECHNOLOGIES
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13761453
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Filing Dt:
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02/07/2013
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Publication #:
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Pub Dt:
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08/07/2014
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Title:
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Diode Structure and Method for Gate All Around Silicon Nanowire Technologies
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Patent #:
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Issue Dt:
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04/14/2015
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Application #:
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13761476
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Filing Dt:
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02/07/2013
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Publication #:
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Pub Dt:
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08/07/2014
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Title:
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DIODE STRUCTURE AND METHOD FOR WIRE-LAST NANOMESH TECHNOLOGIES
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13761610
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Filing Dt:
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02/07/2013
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Title:
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METHODS OF FORMING ISOLATION REGIONS FOR FINFET SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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12/30/2014
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Application #:
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13761686
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Filing Dt:
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02/07/2013
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Publication #:
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Pub Dt:
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08/07/2014
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Title:
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METHODS OF FORMING A TRANSISTOR DEVICE ON A BULK SUBSTRATE AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
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12/01/2015
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Application #:
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13762216
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Filing Dt:
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02/07/2013
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Publication #:
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Pub Dt:
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10/24/2013
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Title:
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COMBINED SOFT DETECTION/SOFT DECODING IN TAPE DRIVE STORAGE CHANNELS
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13762445
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Filing Dt:
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02/08/2013
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Publication #:
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Pub Dt:
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06/13/2013
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Title:
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TRANSISTOR STRUCTURE WITH A SIDEWALL-DEFINED INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION AND METHOD OF FORMING THE TRANSISTOR
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Patent #:
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Issue Dt:
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01/26/2016
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Application #:
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13762450
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Filing Dt:
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02/08/2013
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Publication #:
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Pub Dt:
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08/14/2014
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Title:
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LATERAL EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (LEDMOSFET) WITH TAPERED AIRGAP FIELD PLATES
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13762980
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Filing Dt:
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02/08/2013
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Publication #:
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Pub Dt:
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06/13/2013
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Title:
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FIELD EFFECT TRANSISTORS (FETS) AND METHODS OF MANUFACTURE
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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13763136
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Filing Dt:
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02/08/2013
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Publication #:
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Pub Dt:
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06/20/2013
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Title:
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METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER
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Patent #:
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Issue Dt:
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06/17/2014
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Application #:
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13763312
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Filing Dt:
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02/08/2013
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Publication #:
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Pub Dt:
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08/15/2013
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Title:
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FEED-FORWARD EQUALIZER ARCHITECTURES
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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13763399
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Filing Dt:
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02/08/2013
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Publication #:
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Pub Dt:
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08/14/2014
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Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH IMPROVED SEMICONDUCTOR FIN STRUCTURES
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Patent #:
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Issue Dt:
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02/24/2015
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Application #:
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13763659
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Filing Dt:
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02/09/2013
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Publication #:
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Pub Dt:
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08/15/2013
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Title:
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TIME DOMAIN ANALOG MULTIPLICATION TECHNIQUES FOR ADJUSTING TAP WEIGHTS OF FEED-FORWARD EQUALIZERS
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Patent #:
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Issue Dt:
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07/29/2014
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Application #:
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13764051
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Filing Dt:
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02/11/2013
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Publication #:
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Pub Dt:
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08/14/2014
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Title:
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CHEMICAL AND PHYSICAL TEMPLATES FOR FORMING PATTERNS USING DIRECTED SELF-ASSEMBLY MATERIALS
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Patent #:
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Issue Dt:
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11/04/2014
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Application #:
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13764115
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Filing Dt:
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02/11/2013
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Publication #:
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Pub Dt:
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08/14/2014
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Title:
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METHODS OF FORMING A THREE-DIMENSIONAL SEMICONDUCTOR DEVICE WITH A DUAL STRESS CHANNEL AND THE RESULTING DEVICE
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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13764169
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Filing Dt:
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02/11/2013
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Publication #:
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Pub Dt:
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06/13/2013
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Title:
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NANOWIRE STRESS SENSORS AND STRESS SENSOR INTEGRATED CIRCUITS, DESIGN STRUCTURES FOR A STRESS SENSOR INTEGRATED CIRCUIT, AND RELATED METHODS
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13764355
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Filing Dt:
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02/11/2013
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Publication #:
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Pub Dt:
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07/04/2013
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Title:
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METHODS OF FABRICATING TRENCH GENERATED DEVICE STRUCTURES
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13764839
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Filing Dt:
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02/12/2013
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Publication #:
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Pub Dt:
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08/14/2014
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Title:
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METHODS OF TRIMMING NANOWIRE STRUCTURES
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Patent #:
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Issue Dt:
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04/14/2015
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Application #:
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13764860
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Filing Dt:
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02/12/2013
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Publication #:
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Pub Dt:
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04/24/2014
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Title:
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SRAM GLOBAL PRECHARGE, DISCHARGE, AND SENSE
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Patent #:
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Issue Dt:
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07/05/2016
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Application #:
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13765105
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Filing Dt:
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02/12/2013
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Publication #:
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Pub Dt:
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06/13/2013
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Title:
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DEEP TRENCH DECOUPLING CAPACITOR AND METHODS OF FORMING
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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13765474
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Filing Dt:
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02/12/2013
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Publication #:
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Pub Dt:
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06/20/2013
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Title:
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SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS
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Patent #:
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Issue Dt:
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09/01/2015
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Application #:
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13765723
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Filing Dt:
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02/13/2013
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Publication #:
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Pub Dt:
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08/14/2014
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Title:
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SHALLOW TRENCH ISOLATION INTEGRATION METHODS AND DEVICES FORMED THEREBY
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13765772
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Filing Dt:
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02/13/2013
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Publication #:
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Pub Dt:
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10/03/2013
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Title:
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METHOD OF CHANGING REFLECTANCE OR RESISTANCE OF A REGION IN AN OPTOELECTRONIC MEMORY DEVICE
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13765797
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Filing Dt:
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02/13/2013
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Title:
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METHODS OF FORMING A SEMICONDUCTOR DEVICE WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS
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Patent #:
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Issue Dt:
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03/04/2014
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Application #:
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13765830
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Filing Dt:
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02/13/2013
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Publication #:
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Pub Dt:
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06/13/2013
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Title:
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SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL)
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Patent #:
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Issue Dt:
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10/14/2014
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Application #:
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13766028
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Filing Dt:
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02/13/2013
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Publication #:
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Pub Dt:
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08/14/2014
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Title:
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INTERCONNECT WIRING SWITCHES AND INTEGRATED CIRCUITS INCLUDING THE SAME
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Patent #:
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Issue Dt:
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12/30/2014
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Application #:
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13766141
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Filing Dt:
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02/13/2013
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Publication #:
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Pub Dt:
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08/14/2014
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Title:
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METHOD FOR OFF-GRID ROUTING STRUCTURES UTILIZING SELF ALIGNED DOUBLE PATTERNING (SADP) TECHNOLOGY
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Patent #:
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Issue Dt:
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12/30/2014
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Application #:
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13766228
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Filing Dt:
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02/13/2013
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Publication #:
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Pub Dt:
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08/14/2014
| | | | |
Title:
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EDGE AND STRAP CELL DESIGN FOR SRAM ARRAY
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Patent #:
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Issue Dt:
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12/29/2015
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Application #:
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13766846
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Filing Dt:
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02/14/2013
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Publication #:
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Pub Dt:
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08/14/2014
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Title:
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TEMPERATURE STABILIZATION IN SEMICONDUCTORS USING THE MAGNETOCALORIC EFFECT
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Patent #:
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Issue Dt:
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11/18/2014
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Application #:
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13766898
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Filing Dt:
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02/14/2013
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Publication #:
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Pub Dt:
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08/14/2014
| | | | |
Title:
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METHODS OF FORMING CONDUCTIVE STRUCTURES USING A SACRIFICIAL LINER LAYER
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Patent #:
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Issue Dt:
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09/30/2014
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Application #:
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13766922
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Filing Dt:
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02/14/2013
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Publication #:
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Pub Dt:
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08/14/2014
| | | | |
Title:
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METHODS OF FORMING MULTIPLE N-TYPE SEMICONDUCTOR DEVICES WITH DIFFERENT THRESHOLD VOLTAGES ON A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
|
08/05/2014
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Application #:
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13766952
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Filing Dt:
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02/14/2013
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Publication #:
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Pub Dt:
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06/27/2013
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Title:
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ISOLATION STRUCTURES FOR GLOBAL SHUTTER IMAGER PIXEL, METHODS OF MANUFACTURE AND DESIGN STRUCTURES
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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13767024
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Filing Dt:
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02/14/2013
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Publication #:
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Pub Dt:
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08/14/2014
| | | | |
Title:
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BIOLOGICAL AND CHEMICAL SENSORS
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13767930
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Filing Dt:
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02/15/2013
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Publication #:
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Pub Dt:
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08/21/2014
| | | | |
Title:
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POLYSILICON RESISTOR FORMATION
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Patent #:
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Issue Dt:
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08/12/2014
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Application #:
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13768112
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Filing Dt:
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02/15/2013
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Publication #:
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Pub Dt:
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08/21/2014
| | | | |
Title:
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INTEGRATED CIRCUIT PAD MODELING
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Patent #:
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Issue Dt:
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12/08/2015
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Application #:
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13768275
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Filing Dt:
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02/15/2013
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Publication #:
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Pub Dt:
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08/21/2014
| | | | |
Title:
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CIRCUIT ELEMENT INCLUDING A LAYER OF A STRESS-CREATING MATERIAL PROVIDING A VARIABLE STRESS AND METHOD FOR THE FORMATION THEREOF
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Patent #:
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Issue Dt:
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05/26/2015
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Application #:
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13768759
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Filing Dt:
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02/15/2013
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Publication #:
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Pub Dt:
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06/20/2013
| | | | |
Title:
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CHIP ASSEMBLY WITH A CORELESS SUBSTRATE EMPLOYING A PATTERNED ADHESIVE LAYER
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Patent #:
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Issue Dt:
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12/24/2013
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Application #:
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13769402
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Filing Dt:
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02/18/2013
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Publication #:
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Pub Dt:
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06/20/2013
| | | | |
Title:
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LINER-FREE TUNGSTEN CONTACT
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|