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Patent #:
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05/06/2014
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13769446
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02/18/2013
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Publication #:
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Pub Dt:
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06/20/2013
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Title:
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SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT BARS AND METAL LINES WITH INCREASED VIA LANDING REGIONS
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05/26/2015
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13769494
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02/18/2013
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Pub Dt:
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08/21/2014
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Title:
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INFRARED-BASED METROLOGY FOR DETECTION OF STRESS AND DEFECTS AROUND THROUGH SILICON VIAS
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08/05/2014
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13769500
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Filing Dt:
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02/18/2013
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Publication #:
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Pub Dt:
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08/21/2014
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Title:
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COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY
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05/19/2015
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13769976
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02/19/2013
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Pub Dt:
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06/12/2014
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Title:
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MANAGING ERRORS IN A DRAM BY WEAK CELL ENCODING
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11/29/2016
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13770018
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02/19/2013
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Pub Dt:
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07/11/2013
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Title:
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DEPLOYMENT PATTERN REALIZATION WITH MODELS OF COMPUTING ENVIRONMENTS
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07/08/2014
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13770026
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02/19/2013
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01/23/2014
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Title:
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MULTI-LAYER BARRIER LAYER STACKS FOR INTERCONNECT STRUCTURES
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06/17/2014
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13770229
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Filing Dt:
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02/19/2013
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08/22/2013
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Title:
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Parsing Data Representative of a Hardware Design into Commands of a Hardware Design Environment
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07/08/2014
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13770287
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Filing Dt:
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02/19/2013
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Title:
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CORRECTING FOR OVEREXPOSURE DUE TO OVERLAPPING EXPOSURES IN LITHOGRAPHY
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01/13/2015
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13770493
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02/19/2013
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Pub Dt:
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08/21/2014
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Title:
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SEMICONDUCTOR GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION AND METHOD OF MAKING SAME
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05/26/2015
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13770534
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02/19/2013
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06/20/2013
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Title:
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METHOD AND STRUCTURE FOR FORMING HIGH-K/METAL GATE EXTREMELY THIN SEMICONDUCTOR ON INSULATOR DEVICE
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06/16/2015
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13770552
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02/19/2013
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06/27/2013
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Title:
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REPLACEMENT GATE HAVING WORK FUNCTION AT VALENCE BAND EDGE
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11/22/2016
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13770711
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02/19/2013
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08/21/2014
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Title:
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EFFICIENT VALIDATION OF COHERENCY BETWEEN PROCESSOR CORES AND ACCELERATORS IN COMPUTER SYSTEMS
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07/22/2014
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13771240
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Filing Dt:
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02/20/2013
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Title:
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FINFETS AND FIN ISOLATION STRUCTURES
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03/24/2015
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13771255
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02/20/2013
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05/08/2014
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Title:
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METHOD AND STRUCTURE FOR FORMING A LOCALIZED SOI FINFET
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11/04/2014
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13771294
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02/20/2013
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Pub Dt:
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08/21/2014
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Title:
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METHODS OF INDUCING A DESIRED STRESS IN THE CHANNEL REGION OF A TRANSISTOR BY PERFORMING ION IMPLANTATION/ANNEAL PROCESSES ON THE GATE ELECTRODE
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05/27/2014
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13771478
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02/20/2013
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Title:
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EUV MASK DEFECT RECONSTRUCTION AND COMPENSATION REPAIR
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09/02/2014
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13771668
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02/20/2013
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06/27/2013
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Title:
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ON CHIP INDUCTOR WITH FREQUENCY DEPENDENT INDUCTANCE
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06/16/2015
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13771864
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02/20/2013
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06/27/2013
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Title:
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STRUCTURE AND METHOD FOR INCREASING STRAIN IN A DEVICE
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06/16/2015
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13771929
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02/20/2013
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06/27/2013
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Title:
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FLUIDIC STRUCTURE WITH NANOPORE ARRAY
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10/22/2013
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13772402
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02/21/2013
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Pub Dt:
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06/27/2013
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Title:
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SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS AND METHOD OF FORMING THE STRUCTURE
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10/21/2014
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13772511
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02/21/2013
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08/29/2013
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Title:
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Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION
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02/11/2014
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13772881
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02/21/2013
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Pub Dt:
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06/27/2013
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Title:
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JUNCTION FIELD EFFECT TRANSISTOR WITH AN EPITAXIALLY GROWN GATE STRUCTURE
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01/06/2015
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13772954
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02/21/2013
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07/04/2013
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Title:
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TRENCH SILICIDE CONTACT WITH LOW INTERFACE RESISTANCE
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05/26/2015
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13772993
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02/21/2013
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06/27/2013
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Title:
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DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE
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09/16/2014
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13773397
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02/21/2013
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08/21/2014
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Title:
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INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING METAL GATE ELECTRODES
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11/11/2014
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13773854
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02/22/2013
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08/28/2014
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Title:
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SETTING SWITCH SIZE AND TRANSITION PATTERN IN A RESONANT CLOCK DISTRIBUTION SYSTEM
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01/14/2014
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13773881
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02/22/2013
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Pub Dt:
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12/19/2013
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METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION
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01/13/2015
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13774069
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02/22/2013
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06/27/2013
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Title:
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STRUCTURE, METHOD AND SYSTEM FOR COMPLEMENTARY STRAIN FILL FOR INTEGRATED CIRCUIT CHIPS
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03/31/2015
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13774205
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02/22/2013
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Pub Dt:
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07/04/2013
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Title:
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DESIGN STRUCTURE, STRUCTURE AND METHOD OF LATCH-UP IMMUNITY FOR HIGH AND LOW VOLTAGE INTEGRATED CIRCUITS
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11/25/2014
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13774373
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02/22/2013
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08/28/2014
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Title:
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ELECTRICAL FUSES AND METHODS OF MAKING ELECTRICAL FUSES
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03/04/2014
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13774822
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02/22/2013
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Title:
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METHODS FOR DIRECTED SELF-ASSEMBLY PROCESS/PROXIMITY CORRECTION
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06/02/2015
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13775281
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02/25/2013
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08/28/2014
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Title:
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PHASE CHANGE MEMORY MANAGEMENT
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05/27/2014
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13775369
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02/25/2013
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07/04/2013
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Title:
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FIELD EFFECT TRANSISTOR DEVICE AND FABRICATION
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10/23/2018
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13775416
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02/25/2013
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Pub Dt:
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08/28/2014
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Title:
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METHOD OF FORMING A HIGH QUALITY INTERFACIAL LAYER FOR A SEMICONDUCTOR DEVICE BY PERFORMING A LOW TEMPERATURE ALD PROCESS
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12/02/2014
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13775430
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02/25/2013
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07/11/2013
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SCALING OF METAL GATE WITH ALUMINUM CONTAINING METAL LAYER FOR THRESHOLD VOLTAGE SHIFT
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05/06/2014
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13775570
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02/25/2013
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07/11/2013
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METHODS AND SYSTEMS INVOLVING ELECTRICALLY REPROGRAMMABLE FUSES
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02/17/2015
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13775917
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02/25/2013
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08/28/2014
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U-SHAPED SEMICONDUCTOR STRUCTURE
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02/18/2014
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13775958
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02/25/2013
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07/04/2013
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C-RICH CARBON BORON NITRIDE DIELECTRIC FILMS FOR USE IN ELECTRONIC DEVICES
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08/19/2014
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13775968
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02/25/2013
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07/04/2013
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Title:
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III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER
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12/01/2015
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13775988
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02/25/2013
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11/21/2013
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MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES
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12/09/2014
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13776324
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02/25/2013
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08/28/2014
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SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION
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09/27/2016
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13776902
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02/26/2013
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08/28/2014
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CHARACTERIZATION OF INTERFACE RESISTANCE IN A MULTI-LAYER CONDUCTIVE STRUCTURE
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06/16/2015
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13776911
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02/26/2013
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01/23/2014
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SOURCE/DRAIN-TO-SOURCE/DRAIN RECESSED STRAP AND METHODS OF MANUFACTURE OF SAME
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07/28/2015
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13777353
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02/26/2013
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07/04/2013
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EPITAXIAL EXTENSION CMOS TRANSISTOR
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02/11/2014
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13777402
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02/26/2013
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07/04/2013
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METHOD FOR GROWING CONFORMAL EPI LAYERS AND STRUCTURE THEREOF
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12/16/2014
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13777493
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02/26/2013
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07/04/2013
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ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME
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09/23/2014
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13777506
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02/26/2013
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04/03/2014
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POWER MANAGEMENT DOMINO SRAM BIT LINE DISCHARGE CIRCUIT
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11/18/2014
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13778314
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02/27/2013
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08/28/2014
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STRESS MEMORIZATION IN RMG FINFETS
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12/02/2014
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13778321
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02/27/2013
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08/28/2014
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INTERDIGITATED CAPACITORS WITH A ZERO QUADRATIC VOLTAGE COEFFICIENT OF CAPACITANCE OR ZERO LINEAR TEMPERATURE COEFFICIENT OF CAPACITANCE
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12/09/2014
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13778322
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02/27/2013
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08/28/2014
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METHODS INVOLVING PATTERN MATCHING TO IDENTIFY AND RESOLVE POTENTIAL NON-DOUBLE-PATTERNING-COMPLIANT PATTERNS IN DOUBLE PATTERNING APPLICATIONS
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04/05/2016
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13778419
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02/27/2013
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07/04/2013
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STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES
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02/03/2015
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13778479
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02/27/2013
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08/28/2014
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BI-DIRECTIONAL SILICON CONTROLLED RECTIFIER STRUCTURE
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01/13/2015
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13778558
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02/27/2013
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08/28/2014
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INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CAPPING LAYERS BETWEEN METAL CONTACTS AND INTERCONNECTS
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01/20/2015
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13779036
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02/27/2013
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08/28/2014
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INFORMATION ENCODING USING WIREBONDS
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07/21/2015
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13780205
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02/28/2013
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06/12/2014
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DRAM ERROR DETECTION, EVALUATION, AND CORRECTION
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04/28/2015
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13780449
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02/28/2013
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07/18/2013
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DEPOSITION CHAMBER CLEANING METHOD INCLUDING STRESSED CLEANING LAYER
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02/25/2014
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13780454
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02/28/2013
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07/11/2013
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SINGLE-JUNCTION PHOTOVOLTAIC CELL
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07/28/2015
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13780762
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02/28/2013
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07/11/2013
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Title:
|
FIELD EFFECT TRANSISTOR HAVING AN ASYMMETRIC GATE ELECTRODE
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Patent #:
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Issue Dt:
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03/03/2015
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Application #:
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13780877
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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REPLACEMENT GATE MOSFET WITH A HIGH PERFORMANCE GATE ELECTRODE
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13780887
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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01/02/2014
| | | | |
Title:
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INTEGRATION OF A TITANIA LAYER IN AN ANTI-REFLECTIVE COATING
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Patent #:
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Issue Dt:
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12/15/2015
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Application #:
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13780912
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Filing Dt:
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02/28/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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SELF-ALIGNED CONTACT FOR REPLACEMENT GATE DEVICES
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Patent #:
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Issue Dt:
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11/18/2014
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Application #:
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13781874
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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METHODS OF FORMING ASYMMETRIC SPACERS ON VARIOUS STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS
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Patent #:
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Issue Dt:
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10/28/2014
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Application #:
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13781907
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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METAL GATE STRUCTURE FOR SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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06/16/2015
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Application #:
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13781921
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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METHODS OF FORMING NON-CONTINUOUS CONDUCTIVE LAYERS FOR CONDUCTIVE STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT
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Patent #:
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Issue Dt:
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08/19/2014
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Application #:
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13782094
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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BIPOLAR DEVICE HAVING A MONOCRYSTALLINE SEMICONDUCTOR INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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13782106
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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REPLACEMENT METAL GATE WITH MULITIPLE TITANIUM NITRIDE LATERS
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Patent #:
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Issue Dt:
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06/30/2015
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Application #:
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13782364
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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SELECTIVELY LOWERING RESISTANCE OF A CONSTANTLY USED PORTION OF MOTOR WINDINGS IN DISK DRIVE
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Patent #:
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Issue Dt:
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03/31/2015
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Application #:
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13782452
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/05/2013
| | | | |
Title:
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SELECTIVELY LOWERING RESISTANCE OF A CONSTANTLY USED PORTION OF MOTOR WINDINGS IN AN ELECTRIC MOTOR
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|
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Patent #:
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Issue Dt:
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05/05/2015
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Application #:
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13782467
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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07/11/2013
| | | | |
Title:
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DYNAMIC RECONFIGURATION-SWITCHING OF WINDINGS IN AN ELECTRIC MOTOR USED AS A GENERATOR IN AN ELECTRIC VEHICLE
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|
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Patent #:
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Issue Dt:
|
03/24/2015
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Application #:
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13782537
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
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09/04/2014
| | | | |
Title:
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SEGMENTED GUARD RING STRUCTURES WITH ELECTRICALLY INSULATED GAP STRUCTURES AND DESIGN STRUCTURES THEREOF
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|
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Patent #:
|
|
Issue Dt:
|
06/16/2015
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Application #:
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13782561
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Filing Dt:
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03/01/2013
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Publication #:
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|
Pub Dt:
|
09/04/2014
| | | | |
Title:
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THERMALLY-OPTIMIZED METAL FILL FOR STACKED CHIP SYSTEMS
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|
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Patent #:
|
|
Issue Dt:
|
01/06/2015
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Application #:
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13782678
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Filing Dt:
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03/01/2013
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Publication #:
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Pub Dt:
|
07/11/2013
| | | | |
Title:
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SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER
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|
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Patent #:
|
|
Issue Dt:
|
05/27/2014
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Application #:
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13782826
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Filing Dt:
|
03/01/2013
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Title:
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METHODS OF MODIFYING A PHYSICAL DESIGN OF AN ELECTRICAL CIRCUIT USED IN THE MANUFACTURE OF A SEMICONDUCTOR DEVICE
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|
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Patent #:
|
|
Issue Dt:
|
02/18/2014
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Application #:
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13783388
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Filing Dt:
|
03/03/2013
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Title:
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SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES
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|
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Patent #:
|
|
Issue Dt:
|
04/01/2014
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Application #:
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13783438
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Filing Dt:
|
03/04/2013
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Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
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DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS
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|
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Patent #:
|
|
Issue Dt:
|
04/21/2015
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Application #:
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13783517
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Filing Dt:
|
03/04/2013
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Publication #:
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|
Pub Dt:
|
09/04/2014
| | | | |
Title:
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CHANNEL SIGE REMOVAL FROM PFET SOURCE/DRAIN REGION FOR IMPROVED SILICIDE FORMATION IN HKMG TECHNOLOGIES WITHOUT EMBEDDED SIGE
|
|
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Patent #:
|
|
Issue Dt:
|
12/31/2013
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Application #:
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13783526
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Filing Dt:
|
03/04/2013
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Publication #:
|
|
Pub Dt:
|
07/11/2013
| | | | |
Title:
|
FIELD EFFECT TRANSISTOR DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
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Application #:
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13783562
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Filing Dt:
|
03/04/2013
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Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
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DEFECT REMOVAL PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/16/2015
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Application #:
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13783705
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Filing Dt:
|
03/04/2013
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Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
PLANAR QUBITS HAVING INCREASED COHERENCE TIMES
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|
|
Patent #:
|
|
Issue Dt:
|
08/26/2014
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Application #:
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13783715
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Filing Dt:
|
03/04/2013
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Publication #:
|
|
Pub Dt:
|
09/04/2014
| | | | |
Title:
|
METHODS OF FORMING STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2015
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Application #:
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13783729
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Filing Dt:
|
03/04/2013
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Publication #:
|
|
Pub Dt:
|
07/03/2014
| | | | |
Title:
|
HYBRID LATCH AND FUSE SCHEME FOR MEMORY REPAIR
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|
|
Patent #:
|
|
Issue Dt:
|
02/03/2015
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Application #:
|
13784220
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Filing Dt:
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03/04/2013
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Publication #:
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|
Pub Dt:
|
09/04/2014
| | | | |
Title:
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CONTACT POWER RAIL
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
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Application #:
|
13785109
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Filing Dt:
|
03/05/2013
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Title:
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TEST COVERAGE OF INTEGRATED CIRCUITS WITH MASKING PATTERN SELECTION
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|
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Patent #:
|
|
Issue Dt:
|
01/27/2015
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Application #:
|
13785403
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Filing Dt:
|
03/05/2013
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Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
03/18/2014
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Application #:
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13785438
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Filing Dt:
|
03/05/2013
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Publication #:
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|
Pub Dt:
|
07/18/2013
| | | | |
Title:
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TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS
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|
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Patent #:
|
|
Issue Dt:
|
02/03/2015
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Application #:
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13785468
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Filing Dt:
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03/05/2013
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Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT ELEMENTS AND THE RESULTING DEVICES
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|
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Patent #:
|
|
Issue Dt:
|
02/10/2015
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Application #:
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13785480
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Filing Dt:
|
03/05/2013
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Publication #:
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Pub Dt:
|
07/25/2013
| | | | |
Title:
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SEMICONDUCTOR DEVICES HAVING ENCAPSULATED STRESSOR REGIONS AND RELATED FABRICATION METHODS
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|
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Patent #:
|
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Issue Dt:
|
09/02/2014
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Application #:
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13785602
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Filing Dt:
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03/05/2013
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Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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MEMORY STATE SENSING BASED ON CELL CAPACITANCE
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|
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Patent #:
|
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Issue Dt:
|
09/02/2014
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Application #:
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13785816
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Filing Dt:
|
03/05/2013
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Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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FRONT SIDE WAFER ID PROCESSING
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|
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Patent #:
|
|
Issue Dt:
|
03/17/2015
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Application #:
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13786627
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Filing Dt:
|
03/06/2013
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Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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BARRIER LAYER CONFORMALITY IN COPPER INTERCONNECTS
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|
|
Patent #:
|
|
Issue Dt:
|
10/25/2016
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Application #:
|
13787090
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Filing Dt:
|
03/06/2013
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Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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MULTILAYER PATTERN TRANSFER FOR CHEMICAL GUIDES
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|
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Patent #:
|
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Issue Dt:
|
12/17/2013
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Application #:
|
13787384
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Filing Dt:
|
03/06/2013
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Title:
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METHODS OF SELECTIVELY FORMING RUTHENIUM LINER LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
01/27/2015
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Application #:
|
13787521
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Filing Dt:
|
03/06/2013
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Publication #:
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Pub Dt:
|
09/11/2014
| | | | |
Title:
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METHODS FOR FABRICATING INTEGRATED CIRCUITS UTILIZING SILICON NITRIDE LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
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Application #:
|
13788406
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Filing Dt:
|
03/07/2013
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Publication #:
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Pub Dt:
|
07/18/2013
| | | | |
Title:
|
High Density Memory Cells Using Lateral Epitaxy
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|
|
Patent #:
|
|
Issue Dt:
|
10/27/2015
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Application #:
|
13788450
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Filing Dt:
|
03/07/2013
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Publication #:
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|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
APPARATUS AND METHOD FOR CONTROLLED ACCESS TO PRESSURIZED FLUID LINES AND TO EXHAUSTED LINES
|
|
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Patent #:
|
|
Issue Dt:
|
06/09/2015
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Application #:
|
13788719
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Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2015
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Application #:
|
13788744
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Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
12/19/2013
| | | | |
Title:
|
BITLINE DELETION
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/2014
|
Application #:
|
13788980
|
Filing Dt:
|
03/07/2013
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Publication #:
|
|
Pub Dt:
|
07/18/2013
| | | | |
Title:
|
HIGH CAPACITANCE TRENCH CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/2014
|
Application #:
|
13789018
|
Filing Dt:
|
03/07/2013
|
Publication #:
|
|
Pub Dt:
|
08/01/2013
| | | | |
Title:
|
REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT
|
|
|
Patent #:
|
|
Issue Dt:
|
11/11/2014
|
Application #:
|
13789792
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Filing Dt:
|
03/08/2013
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Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
Title:
|
Self-aligned Contacts For Replacement Metal Gate Transistors
|
|