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Reel/Frame:	049490/0001			Pages:	892
		Recorded:	11/29/2018
Conveyance:	SECURITY AGREEMENT

Total properties: 13706
Page 98 of 138
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Patent #:	9298081	Issue Dt:	03/29/2016	Application #:	13790727	Filing Dt:	03/08/2013
Publication #:	US20140254018	Pub Dt:	09/11/2014
Title:	SCATTERING ENHANCED THIN ABSORBER FOR EUV RETICLE AND A METHOD OF MAKING

Patent #:	9035462	Issue Dt:	05/19/2015	Application #:	13791502	Filing Dt:	03/08/2013
Publication #:	US20130207272	Pub Dt:	08/15/2013
Title:	AIRGAP-CONTAINING INTERCONNECT STRUCTURE WITH PATTERNABLE LOW-K MATERIAL AND METHOD OF FABRICATING

Patent #:	9059134	Issue Dt:	06/16/2015	Application #:	13791520	Filing Dt:	03/08/2013
Publication #:	US20130189834	Pub Dt:	07/25/2013
Title:	SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW

Patent #:	8890255	Issue Dt:	11/18/2014	Application #:	13791545	Filing Dt:	03/08/2013
Publication #:	US20130187234	Pub Dt:	07/25/2013
Title:	STRUCTURE AND METHOD FOR STRESS LATCHING IN NON-PLANAR SEMICONDUCTOR DEVICES

Patent #:	9224655	Issue Dt:	12/29/2015	Application #:	13792540	Filing Dt:	03/11/2013
Publication #:	US20140256135	Pub Dt:	09/11/2014
Title:	METHODS OF REMOVING GATE CAP LAYERS IN CMOS APPLICATIONS

Patent #:	9412859	Issue Dt:	08/09/2016	Application #:	13792730	Filing Dt:	03/11/2013
Publication #:	US20140252429	Pub Dt:	09/11/2014
Title:	CONTACT GEOMETRY HAVING A GATE SILICON LENGTH DECOUPLED FROM A TRANSISTOR LENGTH

Patent #:	8769335	Issue Dt:	07/01/2014	Application #:	13792933	Filing Dt:	03/11/2013
Publication #:	US20130191682	Pub Dt:	07/25/2013
Title:	HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM

Patent #:	8966423	Issue Dt:	02/24/2015	Application #:	13792946	Filing Dt:	03/11/2013
Publication #:	US20140258960	Pub Dt:	09/11/2014
Title:	INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESIGN LAYOUTS

Patent #:	9006045	Issue Dt:	04/14/2015	Application #:	13792950	Filing Dt:	03/11/2013
Publication #:	US20140252481	Pub Dt:	09/11/2014
Title:	TRANSISTOR INCLUDING A GATE ELECTRODE EXTENDING ALL AROUND ONE OR MORE CHANNEL REGIONS

Patent #:	8815741	Issue Dt:	08/26/2014	Application #:	13793082	Filing Dt:	03/11/2013
Publication #:	US20140256137	Pub Dt:	09/11/2014
Title:	METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING AN IMPLANTATION OF IONS INTO A LAYER OF SPACER MATERIAL

Patent #:	8963211	Issue Dt:	02/24/2015	Application #:	13793185	Filing Dt:	03/11/2013
Publication #:	US20130187243	Pub Dt:	07/25/2013
Title:	METHOD, STRUCTURE AND DESIGN STRUCTURE FOR CUSTOMIZING HISTORY EFFECTS OF SOI CIRCUITS

Patent #:	8775858	Issue Dt:	07/08/2014	Application #:	13793363	Filing Dt:	03/11/2013
Publication #:	US20130191683	Pub Dt:	07/25/2013
Title:	HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM

Patent #:	9349842	Issue Dt:	05/24/2016	Application #:	13793645	Filing Dt:	03/11/2013
Publication #:	US20130270619	Pub Dt:	10/17/2013
Title:	METHODS OF FORMING SEMICONDUCTOR DEVICES COMPRISING FERROELECTRIC ELEMENTS AND FAST HIGH-K METAL GATE TRANSISTORS

Patent #:	9006064	Issue Dt:	04/14/2015	Application #:	13793804	Filing Dt:	03/11/2013
Publication #:	US20140252503	Pub Dt:	09/11/2014
Title:	MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC

Patent #:	8827547	Issue Dt:	09/09/2014	Application #:	13795030	Filing Dt:	03/12/2013
Publication #:	US20130191096	Pub Dt:	07/25/2013
Title:	FLUID DISTRIBUTION METHOD FACILITATING COOLING OF ELECTRONICS RACK(S) AND SIMULATING HEATED AIRFLOW EXHAUST OF ELECTRONICS RACK(S)

Patent #:	8751985	Issue Dt:	06/10/2014	Application #:	13795198	Filing Dt:	03/12/2013
Title:	HIERARCHICAL LAYOUT VERSUS SCHEMATIC (LVS) COMPARISON WITH EXTRANEOUS DEVICE ELIMINATION

Patent #:	8959462	Issue Dt:	02/17/2015	Application #:	13795513	Filing Dt:	03/12/2013
Publication #:	US20130263063	Pub Dt:	10/03/2013
Title:	MASK DESIGN METHOD, PROGRAM, AND MASK DESIGN SYSTEM

Patent #:	8741780	Issue Dt:	06/03/2014	Application #:	13796154	Filing Dt:	03/12/2013
Publication #:	US20130189826	Pub Dt:	07/25/2013
Title:	REDUCED CORNER LEAKAGE IN SOI STRUCTURE AND METHOD

Patent #:	8832626	Issue Dt:	09/09/2014	Application #:	13796259	Filing Dt:	03/12/2013
Publication #:	US20130191801	Pub Dt:	07/25/2013
Title:	DISTRIBUTING SPARE LATCH CIRCUITS IN INTEGRATED CIRCUIT DESIGNS

Patent #:	8900959	Issue Dt:	12/02/2014	Application #:	13796278	Filing Dt:	03/12/2013
Publication #:	US20140264276	Pub Dt:	09/18/2014
Title:	NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH PAD REGIONS

Patent #:	8778768	Issue Dt:	07/15/2014	Application #:	13796418	Filing Dt:	03/12/2013
Title:	NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH EPITIXIALLY GROWN SOURCE AND DRAIN

Patent #:	9269710	Issue Dt:	02/23/2016	Application #:	13796674	Filing Dt:	03/12/2013
Publication #:	US20130207201	Pub Dt:	08/15/2013
Title:	SEMICONDUCTOR DEVICES HAVING STRESSOR REGIONS AND RELATED FABRICATION METHODS

Patent #:	8841711	Issue Dt:	09/23/2014	Application #:	13797001	Filing Dt:	03/12/2013
Publication #:	US20140264479	Pub Dt:	09/18/2014
Title:	METHODS OF INCREASING SPACE FOR CONTACT ELEMENTS BY USING A SACRIFICIAL LINER AND THE RESULTING DEVICE

Patent #:	8936986	Issue Dt:	01/20/2015	Application #:	13797117	Filing Dt:	03/12/2013
Publication #:	US20140273429	Pub Dt:	09/18/2014
Title:	METHODS OF FORMING FINFET DEVICES WITH A SHARED GATE STRUCTURE

Patent #:	9117842	Issue Dt:	08/25/2015	Application #:	13798429	Filing Dt:	03/13/2013
Publication #:	US20140273369	Pub Dt:	09/18/2014
Title:	METHODS OF FORMING CONTACTS TO SOURCE/DRAIN REGIONS OF FINFET DEVICES

Patent #:	9087742	Issue Dt:	07/21/2015	Application #:	13798446	Filing Dt:	03/13/2013
Publication #:	US20130187253	Pub Dt:	07/25/2013
Title:	HIGH DENSITY MULTI-ELECTRODE ARRAY

Patent #:	9055701	Issue Dt:	06/09/2015	Application #:	13798449	Filing Dt:	03/13/2013
Publication #:	US20130205588	Pub Dt:	08/15/2013
Title:	Method and System for Improving Alignment Precision of Parts in MEMS

Patent #:	8927361	Issue Dt:	01/06/2015	Application #:	13798573	Filing Dt:	03/13/2013
Publication #:	US20130196476	Pub Dt:	08/01/2013
Title:	HIGH THRESHOLD VOLTAGE NMOS TRANSISTORS FOR LOW POWER IC TECHNOLOGY

Patent #:	8853019	Issue Dt:	10/07/2014	Application #:	13798616	Filing Dt:	03/13/2013
Publication #:	US20140273423	Pub Dt:	09/18/2014
Title:	METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A NANOWIRE CHANNEL STRUCTURE BY PERFORMING AN ANNEAL PROCESS

Patent #:	8969207	Issue Dt:	03/03/2015	Application #:	13798690	Filing Dt:	03/13/2013
Publication #:	US20140273473	Pub Dt:	09/18/2014
Title:	METHODS OF FORMING A MASKING LAYER FOR PATTERNING UNDERLYING STRUCTURES

Patent #:	8809827	Issue Dt:	08/19/2014	Application #:	13799148	Filing Dt:	03/13/2013
Title:	THERMALLY ASSISTED MRAM WITH MULTILAYER STRAP AND TOP CONTACT FOR LOW THERMAL CONDUCTIVITY

Patent #:	9075934	Issue Dt:	07/07/2015	Application #:	13799165	Filing Dt:	03/13/2013
Publication #:	US20130198697	Pub Dt:	08/01/2013
Title:	RETICLE DEFECT CORRECTION BY SECOND EXPOSURE

Patent #:	9219013	Issue Dt:	12/22/2015	Application #:	13799239	Filing Dt:	03/13/2013
Publication #:	US20140273370	Pub Dt:	09/18/2014
Title:	TECHNIQUE FOR MANUFACTURING SEMICONDUCTOR DEVICES COMPRISING TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES

Patent #:	8895444	Issue Dt:	11/25/2014	Application #:	13799508	Filing Dt:	03/13/2013
Publication #:	US20140273455	Pub Dt:	09/18/2014
Title:	HARD MASK REMOVAL DURING FINFET FORMATION

Patent #:	8962483	Issue Dt:	02/24/2015	Application #:	13799539	Filing Dt:	03/13/2013
Publication #:	US20140273474	Pub Dt:	09/18/2014
Title:	INTERCONNECTION DESIGNS USING SIDEWALL IMAGE TRANSFER (SIT)

Patent #:	8951877	Issue Dt:	02/10/2015	Application #:	13799741	Filing Dt:	03/13/2013
Publication #:	US20140264347	Pub Dt:	09/18/2014
Title:	TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES BASED ON AN AMORPHIZATION PROCESS AND A HEAT TREATMENT

Patent #:	8846464	Issue Dt:	09/30/2014	Application #:	13799814	Filing Dt:	03/13/2013
Publication #:	US20140273389	Pub Dt:	09/18/2014
Title:	SEMICONDUCTOR DEVICE HAVING CONTROLLED FINAL METAL CRITICAL DIMENSION

Patent #:	9219128	Issue Dt:	12/22/2015	Application #:	13800091	Filing Dt:	03/13/2013
Publication #:	US20140264341	Pub Dt:	09/18/2014
Title:	METHODS OF FABRICATING BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE

Patent #:	8835889	Issue Dt:	09/16/2014	Application #:	13800966	Filing Dt:	03/13/2013
Publication #:	US20140264664	Pub Dt:	09/18/2014
Title:	PARALLEL SHUNT PATHS IN THERMALLY ASSISTED MAGNETIC MEMORY CELLS

Patent #:	8918745	Issue Dt:	12/23/2014	Application #:	13803048	Filing Dt:	03/14/2013
Publication #:	US20140282301	Pub Dt:	09/18/2014
Title:	STITCH INSERTION FOR REDUCING COLOR DENSITY DIFFERENCES IN DOUBLE PATTERNING TECHNOLOGY (DPT)

Patent #:	8932932	Issue Dt:	01/13/2015	Application #:	13803281	Filing Dt:	03/14/2013
Publication #:	US20130203234	Pub Dt:	08/08/2013
Title:	HIGHLY SCALABLE TRENCH CAPACITOR

Patent #:	9015642	Issue Dt:	04/21/2015	Application #:	13803293	Filing Dt:	03/14/2013
Publication #:	US20140282296	Pub Dt:	09/18/2014
Title:	HYBRID METHOD FOR PERFORMING FULL FIELD OPTICAL PROXIMITY CORRECTION FOR FINFET MANDREL LAYER

Patent #:	8865561	Issue Dt:	10/21/2014	Application #:	13803856	Filing Dt:	03/14/2013
Publication #:	US20140273418	Pub Dt:	09/18/2014
Title:	BACK-GATED SUBSTRATE AND SEMICONDUCTOR DEVICE, AND RELATED METHOD OF FABRICATION

Patent #:	9455154	Issue Dt:	09/27/2016	Application #:	13804112	Filing Dt:	03/14/2013
Publication #:	US20140273475	Pub Dt:	09/18/2014
Title:	METHODS FOR FABRICATING GUIDE PATTERNS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SUCH GUIDE PATTERNS

Patent #:	9080948	Issue Dt:	07/14/2015	Application #:	13826316	Filing Dt:	03/14/2013
Publication #:	US20140264015	Pub Dt:	09/18/2014
Title:	DYNAMIC PEAK TRACKING IN X-RAY PHOTOELECTRON SPECTROSCOPY MEASUREMENT TOOL

Patent #:	9251306	Issue Dt:	02/02/2016	Application #:	13826631	Filing Dt:	03/14/2013
Publication #:	US20130205272	Pub Dt:	08/08/2013
Title:	ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-DIRECTED PLACER

Patent #:	8546956	Issue Dt:	10/01/2013	Application #:	13826830	Filing Dt:	03/14/2013
Publication #:	US20130200520	Pub Dt:	08/08/2013
Title:	THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT WITH ENHANCED COPPER-TO-COPPER BONDING

Patent #:	8658488	Issue Dt:	02/25/2014	Application #:	13826874	Filing Dt:	03/14/2013
Publication #:	US20130203246	Pub Dt:	08/08/2013
Title:	METHOD FOR FORMING SEMICONDUCTOR CHIP WITH GRAPHENE BASED DEVICES IN AN INTERCONNECT STRUCTURE OF THE CHIP

Patent #:	9202863	Issue Dt:	12/01/2015	Application #:	13826936	Filing Dt:	03/14/2013
Publication #:	US20130193551	Pub Dt:	08/01/2013
Title:	STRUCTURE WITH SELF ALIGNED RESIST LAYER ON AN INTERCONNECT SURFACE AND METHOD OF MAKING SAME

Patent #:	8826214	Issue Dt:	09/02/2014	Application #:	13827690	Filing Dt:	03/14/2013
Publication #:	US20130198702	Pub Dt:	08/01/2013
Title:	IMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT

Patent #:	8969170	Issue Dt:	03/03/2015	Application #:	13827786	Filing Dt:	03/14/2013
Publication #:	US20140273396	Pub Dt:	09/18/2014
Title:	METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A METAL-INSULATOR-METAL CAPACITOR

Patent #:	8796093	Issue Dt:	08/05/2014	Application #:	13828276	Filing Dt:	03/14/2013
Title:	DOPING OF FINFET STRUCTURES

Patent #:	9070625	Issue Dt:	06/30/2015	Application #:	13828650	Filing Dt:	03/14/2013
Publication #:	US20130203231	Pub Dt:	08/08/2013
Title:	SELECTIVE ETCH CHEMISTRY FOR GATE ELECTRODE MATERIALS

Patent #:	9064786	Issue Dt:	06/23/2015	Application #:	13828936	Filing Dt:	03/14/2013
Publication #:	US20140264752	Pub Dt:	09/18/2014
Title:	DUAL THREE-DIMENSIONAL (3D) RESISTOR AND METHODS OF FORMING

Patent #:	9012270	Issue Dt:	04/21/2015	Application #:	13832442	Filing Dt:	03/15/2013
Publication #:	US20140264461	Pub Dt:	09/18/2014
Title:	METAL LAYER ENABLING DIRECTED SELF-ASSEMBLY SEMICONDUCTOR LAYOUT DESIGNS

Patent #:	8722508	Issue Dt:	05/13/2014	Application #:	13832929	Filing Dt:	03/15/2013
Publication #:	US20130214384	Pub Dt:	08/22/2013
Title:	LOW HARMONIC RF SWITCH IN SOI

Patent #:	8956789	Issue Dt:	02/17/2015	Application #:	13832994	Filing Dt:	03/15/2013
Publication #:	US20140273306	Pub Dt:	09/18/2014
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING MULTI-PATTERNING OF MASKS FOR EXTREME ULTRAVIOLET LITHOGRAPHY

Patent #:	8856698	Issue Dt:	10/07/2014	Application #:	13833104	Filing Dt:	03/15/2013
Publication #:	US20140282307	Pub Dt:	09/18/2014
Title:	METHOD AND APPARATUS FOR PROVIDING METRIC RELATING TWO OR MORE PROCESS PARAMETERS TO YIELD

Patent #:	9196829	Issue Dt:	11/24/2015	Application #:	13833139	Filing Dt:	03/15/2013
Publication #:	US20130200321	Pub Dt:	08/08/2013
Title:	POST-FABRICATION SELF-ALIGNED INITIALIZATION OF INTEGRATED DEVICES

Patent #:	9460934	Issue Dt:	10/04/2016	Application #:	13833317	Filing Dt:	03/15/2013
Publication #:	US20140273501	Pub Dt:	09/18/2014
Title:	WET STRIP PROCESS FOR AN ANTIREFLECTIVE COATING LAYER

Patent #:	8962417	Issue Dt:	02/24/2015	Application #:	13833656	Filing Dt:	03/15/2013
Publication #:	US20140273381	Pub Dt:	09/18/2014
Title:	METHOD AND STRUCTURE FOR PFET JUNCTION PROFILE WITH SIGE CHANNEL

Patent #:	8799846	Issue Dt:	08/05/2014	Application #:	13833713	Filing Dt:	03/15/2013
Title:	FACILITATING THE DESIGN OF A CLOCK GRID IN AN INTEGRATED CIRCUIT

Patent #:	9041107	Issue Dt:	05/26/2015	Application #:	13833735	Filing Dt:	03/15/2013
Publication #:	US20130200458	Pub Dt:	08/08/2013
Title:	DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE

Patent #:	9087587	Issue Dt:	07/21/2015	Application #:	13834019	Filing Dt:	03/15/2013
Publication #:	US20140269060	Pub Dt:	09/18/2014
Title:	INTEGRATED CIRCUITS AND METHODS FOR OPERATING INTEGRATED CIRCUITS WITH NON-VOLATILE MEMORY

Patent #:	8957524	Issue Dt:	02/17/2015	Application #:	13834058	Filing Dt:	03/15/2013
Publication #:	US20140264890	Pub Dt:	09/18/2014
Title:	NOVEL PILLAR STRUCTURE FOR USE IN PACKAGING INTEGRATED CIRCUIT PRODUCTS AND METHODS OF MAKING SUCH A PILLAR STRUCTURE

Patent #:	8753940	Issue Dt:	06/17/2014	Application #:	13834410	Filing Dt:	03/15/2013
Title:	METHODS OF FORMING ISOLATION STRUCTURES AND FINS ON A FINFET SEMICONDUCTOR DEVICE

Patent #:	9275890	Issue Dt:	03/01/2016	Application #:	13834608	Filing Dt:	03/15/2013
Publication #:	US20140264631	Pub Dt:	09/18/2014
Title:	METHODS OF FORMING ALIGNMENT MARKS AND OVERLAY MARKS ON INTEGRATED CIRCUIT PRODUCTS EMPLOYING FINFET DEVICES AND THE RESULTING ALIGNMENT/OVERLAY MARK

Patent #:	8871649	Issue Dt:	10/28/2014	Application #:	13834946	Filing Dt:	03/15/2013
Publication #:	US20140273443	Pub Dt:	09/18/2014
Title:	METHODS OF FORMING TRENCH/HOLE TYPE FEATURES IN A LAYER OF MATERIAL OF AN INTEGRATED CIRCUIT PRODUCT

Patent #:	9360163	Issue Dt:	06/07/2016	Application #:	13835166	Filing Dt:	03/15/2013
Publication #:	US20140263357	Pub Dt:	09/18/2014
Title:	PASSIVE COMPRESSED GAS STORAGE CONTAINER TEMPERATURE STABILIZER

Patent #:	9257352	Issue Dt:	02/09/2016	Application #:	13835358	Filing Dt:	03/15/2013
Publication #:	US20140266292	Pub Dt:	09/18/2014
Title:	SEMICONDUCTOR TEST WAFER AND METHODS FOR USE THEREOF

Patent #:	9263517	Issue Dt:	02/16/2016	Application #:	13835463	Filing Dt:	03/15/2013
Publication #:	US20130200486	Pub Dt:	08/08/2013
Title:	EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER

Patent #:	9419126	Issue Dt:	08/16/2016	Application #:	13835944	Filing Dt:	03/15/2013
Publication #:	US20140264613	Pub Dt:	09/18/2014
Title:	INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ACTIVE AREA PROTECTION

Patent #:	8904324	Issue Dt:	12/02/2014	Application #:	13836057	Filing Dt:	03/15/2013
Publication #:	US20140282323	Pub Dt:	09/18/2014
Title:	PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN

Patent #:	8793627	Issue Dt:	07/29/2014	Application #:	13837624	Filing Dt:	03/15/2013
Title:	VIA NON-STANDARD LIMITING PARAMETERS

Patent #:	8966418	Issue Dt:	02/24/2015	Application #:	13837763	Filing Dt:	03/15/2013
Publication #:	US20140282330	Pub Dt:	09/18/2014
Title:	PRIORITY BASED LAYOUT VERSUS SCHEMATIC (LVS)

Patent #:	8753953	Issue Dt:	06/17/2014	Application #:	13837810	Filing Dt:	03/15/2013
Title:	SELF ALIGNED CAPACITOR FABRICATION

Patent #:	8843869	Issue Dt:	09/23/2014	Application #:	13838378	Filing Dt:	03/15/2013
Publication #:	US20140282345	Pub Dt:	09/18/2014
Title:	VIA INSERTION IN INTEGRATED CIRCUIT (IC) DESIGNS

Patent #:	8796854	Issue Dt:	08/05/2014	Application #:	13838956	Filing Dt:	03/15/2013
Publication #:	US20130221529	Pub Dt:	08/29/2013
Title:	HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT

Patent #:	8754526	Issue Dt:	06/17/2014	Application #:	13839020	Filing Dt:	03/15/2013
Publication #:	US20130228925	Pub Dt:	09/05/2013
Title:	HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT

Patent #:	9064924	Issue Dt:	06/23/2015	Application #:	13839100	Filing Dt:	03/15/2013
Publication #:	US20130313551	Pub Dt:	11/28/2013
Title:	HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS

Patent #:	8980737	Issue Dt:	03/17/2015	Application #:	13839161	Filing Dt:	03/15/2013
Publication #:	US20130316520	Pub Dt:	11/28/2013
Title:	METHODS OF FORMING CONTACT REGIONS USING SACRIFICIAL LAYERS

Patent #:	9093548	Issue Dt:	07/28/2015	Application #:	13839213	Filing Dt:	03/15/2013
Publication #:	US20130328110	Pub Dt:	12/12/2013
Title:	THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR

Patent #:	8889529	Issue Dt:	11/18/2014	Application #:	13839275	Filing Dt:	03/15/2013
Publication #:	US20130313552	Pub Dt:	11/28/2013
Title:	HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS

Patent #:	8906802	Issue Dt:	12/09/2014	Application #:	13839284	Filing Dt:	03/15/2013
Publication #:	US20140273469	Pub Dt:	09/18/2014
Title:	METHODS OF FORMING TRENCH/VIA FEATURES IN AN UNDERLYING STRUCTURE USING A PROCESS THAT INCLUDES A MASKING LAYER FORMED BY A DIRECTED SELF-ASSEMBLY PROCESS

Patent #:	8871582	Issue Dt:	10/28/2014	Application #:	13839626	Filing Dt:	03/15/2013
Publication #:	US20140264486	Pub Dt:	09/18/2014
Title:	METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE

Patent #:	8906754	Issue Dt:	12/09/2014	Application #:	13839802	Filing Dt:	03/15/2013
Publication #:	US20140264487	Pub Dt:	09/18/2014
Title:	METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE

Patent #:	9231046	Issue Dt:	01/05/2016	Application #:	13840132	Filing Dt:	03/15/2013
Publication #:	US20140264741	Pub Dt:	09/18/2014
Title:	CAPACITOR USING BARRIER LAYER METALLURGY

Patent #:	8906768	Issue Dt:	12/09/2014	Application #:	13840692	Filing Dt:	03/15/2013
Publication #:	US20140264489	Pub Dt:	09/18/2014
Title:	WRAP AROUND STRESSOR FORMATION

Patent #:	8911920	Issue Dt:	12/16/2014	Application #:	13840790	Filing Dt:	03/15/2013
Publication #:	US20140272677	Pub Dt:	09/18/2014
Title:	METHODS FOR FABRICATING EUV MASKS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS USING SUCH EUV MASKS

Patent #:	8853101	Issue Dt:	10/07/2014	Application #:	13841694	Filing Dt:	03/15/2013
Publication #:	US20140273511	Pub Dt:	09/18/2014
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING FORMATION OF CHEMICAL GUIDE PATTERNS FOR DIRECTED SELF-ASSEMBLY LITHOGRAPHY

Patent #:	8892237	Issue Dt:	11/18/2014	Application #:	13841919	Filing Dt:	03/15/2013
Publication #:	US20140273299	Pub Dt:	09/18/2014
Title:	SYSTEMS AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES USING DIFFERENT METROLOGY TOOLS

Patent #:	9082876	Issue Dt:	07/14/2015	Application #:	13842103	Filing Dt:	03/15/2013
Publication #:	US20140273367	Pub Dt:	09/18/2014
Title:	INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH GATE ELECTRODE STRUCTURE PROTECTION

Patent #:	8809176	Issue Dt:	08/19/2014	Application #:	13842217	Filing Dt:	03/15/2013
Publication #:	US20130217219	Pub Dt:	08/22/2013
Title:	REPLACEMENT GATE WITH REDUCED GATE LEAKAGE CURRENT

Patent #:	8658456	Issue Dt:	02/25/2014	Application #:	13842564	Filing Dt:	03/15/2013
Publication #:	US20130224896	Pub Dt:	08/29/2013
Title:	MICRO-ELECTRO-MECHANICAL SYSTEM TILTABLE LENS

Patent #:	9059213	Issue Dt:	06/16/2015	Application #:	13845506	Filing Dt:	03/18/2013
Publication #:	US20130230949	Pub Dt:	09/05/2013
Title:	EMBEDDED DRAM FOR EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR

Patent #:	9293520	Issue Dt:	03/22/2016	Application #:	13845560	Filing Dt:	03/18/2013
Publication #:	US20130214382	Pub Dt:	08/22/2013
Title:	METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE

Patent #:	8841944	Issue Dt:	09/23/2014	Application #:	13846044	Filing Dt:	03/18/2013
Publication #:	US20140266329	Pub Dt:	09/18/2014
Title:	FREQUENCY QUADRUPLERS AT MILLIMETER-WAVE FREQUENCIES

Patent #:	8875978	Issue Dt:	11/04/2014	Application #:	13846158	Filing Dt:	03/18/2013
Publication #:	US20140262113	Pub Dt:	09/18/2014
Title:	FORMING CONSTANT DIAMETER SPHERICAL METAL BALLS

Patent #:	8687445	Issue Dt:	04/01/2014	Application #:	13846229	Filing Dt:	03/18/2013
Publication #:	US20130223172	Pub Dt:	08/29/2013
Title:	SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD

100

Patent #:	8927381	Issue Dt:	01/06/2015	Application #:	13847695	Filing Dt:	03/20/2013
Publication #:	US20140284758	Pub Dt:	09/25/2014
Title:	SELF-ALIGNED BIPOLAR JUNCTION TRANSISTORS

Assignor

GLOBALFOUNDRIES INC.

Exec Dt:

11/27/2018

Assignee

WILMINGTON TRUST, NATIONAL ASSOCIATION

1100 NORTH MARKET STREET

WILMINGTON, DELAWARE 19801

Correspondence name and address
	CT CORPORATION
	4400 EASTON COMMONS WAY
	SUITE 125
	COLUMBUS, OH 43219

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