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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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10908594
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Filing Dt:
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05/18/2005
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Publication #:
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Pub Dt:
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11/23/2006
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Title:
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POD SWAPPING INTERNAL TO TOOL RUN TIME
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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11160428
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Filing Dt:
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06/23/2005
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Publication #:
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Pub Dt:
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12/28/2006
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Title:
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CURRENT-ALIGNED AUTO-GENERATED NON-EQUIAXIAL HOLE SHAPE FOR WIRING
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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11161936
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Filing Dt:
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08/23/2005
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Publication #:
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Pub Dt:
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03/08/2007
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Title:
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SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR HAVING INTERSTITIAL TRAPPING LAYER IN BASE REGION
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Patent #:
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Issue Dt:
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06/17/2014
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Application #:
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11468403
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Filing Dt:
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08/30/2006
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Publication #:
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Pub Dt:
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05/29/2008
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Title:
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SEMICONDUCTOR STRUCTURE HAVING UNDERCUT-GATE-OXIDE GATE STACK ENCLOSED BY PROTECTIVE BARRIER MATERIAL
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Patent #:
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Issue Dt:
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04/23/2013
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Application #:
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11531793
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Filing Dt:
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09/14/2006
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Publication #:
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Pub Dt:
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07/05/2007
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Title:
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METHOD OF REDUCING CONTAMINATION BY PROVIDING AN ETCH STOP LAYER AT THE SUBSTRATE EDGE
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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11550450
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Filing Dt:
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10/18/2006
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Publication #:
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Pub Dt:
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04/24/2008
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Title:
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ELECTRICALLY PROGRAMMABLE RESISTOR
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Patent #:
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Issue Dt:
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08/07/2012
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Application #:
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11623031
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Filing Dt:
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01/12/2007
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Publication #:
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Pub Dt:
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07/17/2008
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Title:
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METHOD OF FORMING SEMICONDUCTOR DEVICE
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Patent #:
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Issue Dt:
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12/25/2012
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Application #:
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11767796
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Filing Dt:
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06/25/2007
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Publication #:
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Pub Dt:
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12/25/2008
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Title:
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SEGREGATING WAFER CARRIER TYPES IN SEMICONDUCTOR STORAGE DEVICES
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Patent #:
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Issue Dt:
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01/24/2012
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Application #:
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11773631
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Filing Dt:
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07/05/2007
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Publication #:
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Pub Dt:
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01/31/2008
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Title:
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METHOD OF ENHANCING LITHOGRAPHY CAPABILITIES DURING GATE FORMATION IN SEMICONDUCTORS HAVING A PRONOUNCED SURFACE TOPOGRAPHY
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Patent #:
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Issue Dt:
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04/17/2012
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Application #:
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11775619
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Filing Dt:
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07/10/2007
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Publication #:
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Pub Dt:
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01/17/2008
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Title:
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STRAINED MOS DEVICE AND METHODS FOR ITS FABRICATION
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Patent #:
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Issue Dt:
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07/28/2015
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Application #:
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11789157
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Filing Dt:
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04/23/2007
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Publication #:
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Pub Dt:
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10/23/2008
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Title:
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Method for semiconductor wafer fabrication utilizing a cleaning substrate
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Patent #:
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Issue Dt:
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05/08/2012
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Application #:
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11830090
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Filing Dt:
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07/30/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Title:
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SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS
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Patent #:
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Issue Dt:
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06/18/2013
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11833283
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08/03/2007
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Publication #:
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Pub Dt:
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11/22/2007
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Title:
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POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY
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Patent #:
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05/22/2012
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11870551
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10/11/2007
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04/16/2009
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Title:
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STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES
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Issue Dt:
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10/30/2012
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11875227
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10/19/2007
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04/23/2009
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Title:
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SELECTIVE ETCHING BATH METHODS
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Patent #:
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Issue Dt:
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11/22/2011
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11953445
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12/10/2007
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06/11/2009
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Title:
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METHOD TO INCREASE EFFECTIVE MOSFET WIDTH
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Patent #:
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03/20/2012
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11954557
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Filing Dt:
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12/12/2007
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Pub Dt:
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06/18/2009
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Title:
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FUSE AND PAD STRESS RELIEF
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Patent #:
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Issue Dt:
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11/08/2011
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11955491
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12/13/2007
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Publication #:
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Pub Dt:
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06/18/2009
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Title:
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PFET WITH TAILORED DIELECTRIC AND RELATED METHODS AND INTEGRATED CIRCUIT
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Patent #:
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05/01/2012
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11968771
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01/03/2008
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Publication #:
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Pub Dt:
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07/09/2009
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Title:
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METHODS OF FORMING TUBULAR OBJECTS
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Patent #:
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01/31/2012
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11970693
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01/08/2008
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Publication #:
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Pub Dt:
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07/09/2009
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Title:
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METHOD AND STRUCTURE TO CONTROL THERMAL GRADIENTS IN SEMICONDUCTOR WAFERS DURING RAPID THERMAL PROCESSING
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Patent #:
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04/17/2012
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12013627
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01/14/2008
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07/16/2009
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Title:
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METHODS FOR FORMING A COMPOSITE PATTERN INCLUDING PRINTED RESOLUTION ASSIST FEATURES
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01/17/2012
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12013846
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01/14/2008
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07/16/2009
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Title:
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METHOD AND APPARATUS FOR FABRICATING A HIGH-PERFORMANCE BAND-EDGE COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE
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03/26/2013
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12035518
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02/22/2008
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02/05/2009
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Title:
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SEMICONDUCTOR DEVICE HAVING A GRAIN ORIENTATION LAYER
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01/31/2012
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12044245
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03/07/2008
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09/18/2008
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Title:
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CHEMICAL OXIDE REMOVAL OF PLASMA DAMAGED SICOH LOW K DIELECTRICS
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05/22/2012
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12062618
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04/04/2008
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08/07/2008
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Title:
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DEVICE COMPONENT FORMING METHOD WITH A TRIM STEP PRIOR TO SIDEWALL IMAGE TRANSFER (SIT) PROCESSING
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05/22/2012
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12103110
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04/15/2008
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08/14/2008
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Title:
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APPARATUS FOR APPLYING A LAYER TO A HYDROPHOBIC SURFACE
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02/21/2012
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12107889
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04/23/2008
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09/11/2008
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Title:
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METHOD FOR PRODUCING SELF-ALIGNED MASK, ARTICLES PRODUCED BY SAME AND COMPOSITION FOR SAME
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07/03/2012
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12111276
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04/29/2008
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10/29/2009
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SLURRYLESS MECHANICAL PLANARIZATION FOR SUBSTRATE RECLAMATION
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02/28/2012
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05/15/2008
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10/09/2008
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01/31/2012
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06/02/2008
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06/04/2009
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METHOD AND A SEMICONDUCTOR DEVICE COMPRISING A PROTECTION LAYER FOR REDUCING STRESS RELAXATION IN A DUAL STRESS LINER APPROACH
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01/24/2012
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12136885
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06/11/2008
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11/06/2008
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03/20/2012
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12140479
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06/17/2008
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10/09/2008
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03/06/2012
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12142896
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06/20/2008
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12/24/2009
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METHOD OF FORMING A METAL SILICIDE LAYER, DEVICES INCORPORATING METAL SILICIDE LAYERS AND DESIGN STRUCTURES FOR THE DEVICES
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01/10/2012
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12145025
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06/24/2008
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12/24/2009
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METHOD FOR OPTIMIZING THE ROUTING OF WAFERS/LOTS BASED ON YIELD
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06/12/2012
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07/10/2008
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11/20/2008
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ADDITION OF BALLAST HYDROCARBON GAS TO DOPED POLYSILICON ETCH MASKED BY RESIST
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02/28/2012
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07/22/2008
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01/28/2010
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MULTIPLE EXPOSURE AND SINGLE ETCH INTEGRATION METHOD
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02/04/2014
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12182212
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07/30/2008
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11/20/2008
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SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT
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04/28/2015
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08/04/2008
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02/04/2010
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10/29/2013
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08/05/2008
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11/20/2008
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07/24/2012
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08/06/2008
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02/11/2010
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04/17/2012
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09/10/2008
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03/11/2010
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11/01/2011
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09/25/2008
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03/25/2010
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02/05/2013
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10/09/2008
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04/16/2009
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04/17/2012
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01/29/2009
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07/29/2010
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10/23/2012
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02/18/2009
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08/19/2010
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01/10/2012
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02/27/2009
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12/03/2009
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09/25/2012
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03/13/2009
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09/16/2010
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02/05/2013
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03/16/2009
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09/16/2010
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01/17/2012
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03/27/2009
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09/30/2010
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09/10/2013
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04/22/2009
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11/26/2009
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CURVILINEAR WIRING STRUCTURE TO REDUCE AREAS OF HIGH FIELD DENSITY IN AN INTEGRATED CIRCUIT
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02/28/2012
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05/20/2009
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11/25/2010
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GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE
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10/20/2015
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05/28/2009
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12/02/2010
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01/29/2013
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12480232
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06/08/2009
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12/09/2010
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Title:
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METHODS FOR FABRICATING SEMICONDUCTOR DEVICES
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10/30/2012
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12483588
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06/12/2009
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12/16/2010
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Title:
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INTERCONNECT STRUCTURE FABRICATED WITHOUT DRY PLASMA ETCH PROCESSING
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12/18/2012
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12483891
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06/12/2009
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12/16/2010
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Title:
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FLEXIBLE JOB PREPARATION AND CONTROL
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12/06/2011
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12494015
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06/29/2009
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12/30/2010
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Title:
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12/25/2012
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12509885
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07/27/2009
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01/27/2011
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Title:
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05/08/2012
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12535183
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08/04/2009
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02/10/2011
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Title:
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STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC
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12/25/2012
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12538114
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08/08/2009
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12/03/2009
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Title:
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INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES
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01/01/2013
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12539235
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08/11/2009
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12/31/2009
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Title:
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03/20/2012
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12539930
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08/12/2009
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02/17/2011
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Title:
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METHOD FOR FORMING TRENCHES HAVING DIFFERENT WIDTHS AND THE SAME DEPTH
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01/03/2012
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12541484
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08/14/2009
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02/17/2011
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Title:
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FABRICATING ESD DEVICES USING MOSFET AND LDMOS
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11/08/2011
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12541933
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08/15/2009
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02/17/2011
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Title:
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04/24/2012
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12546235
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08/24/2009
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02/24/2011
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Title:
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MULTIPLE PATTERNING USING IMPROVED PATTERNABLE LOW-K DIELECTRIC MATERIALS
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03/20/2012
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12548005
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08/26/2009
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03/03/2011
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Title:
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09/04/2012
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12548298
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08/26/2009
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03/03/2011
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Title:
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NANOPILLAR DECOUPLING CAPACITOR
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05/08/2012
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12551804
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09/01/2009
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03/03/2011
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Title:
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ASYMMETRIC EMBEDDED SILICON GERMANIUM FIELD EFFECT TRANSISTOR
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03/13/2012
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12555981
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09/09/2009
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03/10/2011
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Title:
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ARRANGING THROUGH SILICON VIAS IN IC LAYOUT
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12/04/2012
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12557934
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09/11/2009
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03/17/2011
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Title:
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STRUCTURE AND METHOD TO MINIMIZE REGROWTH AND WORK FUNCTION SHIFT IN HIGH-K GATE STACKS
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03/20/2012
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12559996
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09/15/2009
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03/17/2011
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Title:
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ASYMMETRIC FINFET DEVICE WITH IMPROVED PARASITIC RESISTANCE AND CAPACITANCE
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07/31/2012
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12562222
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09/18/2009
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03/24/2011
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DOUBLE PATTERNING PROCESS FOR INTEGRATED CIRCUIT DEVICE MANUFACTURING
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03/13/2012
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12569077
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09/29/2009
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01/21/2010
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Title:
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METHODS FOR FORMING DENSE DIELECTRIC LAYER OVER POROUS DIELECTRICS
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07/31/2012
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12570415
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09/30/2009
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03/31/2011
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Title:
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METHOD OF GENERATING UNIFORMLY ALIGNED WELL AND ISOLATION REGIONS IN A SUBSTRATE AND RESULTING STRUCTURE
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10/02/2012
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12577628
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10/12/2009
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04/14/2011
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METHODS FOR PROTECTING FILM LAYERS WHILE REMOVING HARDMASKS DURING FABRICATION OF SEMICONDUCTOR DEVICES
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12/13/2011
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12603353
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10/21/2009
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02/25/2010
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Title:
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SEMICONDUCTOR DEVICE AND METHODS FOR FABRICATING SAME
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07/31/2012
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12608377
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10/29/2009
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05/05/2011
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Title:
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INTERCONNECT STRUCTURE HAVING A VIA WITH A VIA GOUGING FEATURE AND DIELECTRIC LINER SIDEWALLS FOR BEOL INTEGRATION
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10/16/2012
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12610679
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11/02/2009
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05/05/2011
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METHOD FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
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10/30/2012
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11/02/2009
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05/05/2011
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ALKALINE RINSE AGENTS FOR USE IN LITHOGRAPHIC PATTERNING
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01/01/2013
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12614952
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11/09/2009
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05/12/2011
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ANGLE ION IMPLANT TO RE-SHAPE SIDEWALL IMAGE TRANSFER PATTERNS
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01/31/2012
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12621216
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11/18/2009
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05/19/2011
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DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE
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02/05/2013
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12622111
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11/19/2009
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05/19/2011
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02/28/2012
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12622733
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11/20/2009
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05/26/2011
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INTEGRATED CIRCUIT INCLUDING FINFET RF SWITCH ANGLED RELATIVE TO PLANAR MOSFET AND RELATED DESIGN STRUCTURE
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08/07/2012
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12625590
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11/25/2009
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05/26/2011
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PASSIVATION LAYER SURFACE TOPOGRAPHY MODIFICATIONS FOR IMPROVED INTEGRITY IN PACKAGED ASSEMBLIES
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11/27/2012
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12/01/2009
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06/02/2011
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ENHANCING MOSFET PERFORMANCE BY OPTIMIZING STRESS PROPERTIES
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06/05/2012
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12630091
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12/03/2009
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06/09/2011
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INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT
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03/27/2012
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12640192
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12/17/2009
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04/15/2010
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LATERAL TRENCH FETS (FIELD EFFECT TRANSISTORS)
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08/14/2012
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12647796
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12/28/2009
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06/30/2011
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STRUCTURE AND METHOD TO CREATE STRESS TRENCH
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12/11/2012
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12647888
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12/28/2009
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06/30/2011
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EFUSE ENABLEMENT WITH THIN POLYSILICON OR AMORPHOUS-SILICON GATE-STACK FOR HKMG CMOS
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10/30/2012
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12652275
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01/05/2010
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06/10/2010
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MOSFET WITH MULTIPLE FULLY SILICIDED GATE AND METHOD FOR MAKING THE SAME
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05/21/2013
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12683602
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01/07/2010
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07/07/2011
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ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME
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04/09/2013
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12683857
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01/07/2010
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07/07/2011
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SELECTIVE COPPER ENCAPSULATION LAYER DEPOSITION
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09/11/2012
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01/08/2010
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07/14/2011
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Title:
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STRUCTURE FOR USE IN FABRICATION OF PIN HETEROJUNCTION TFET
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01/01/2013
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12691192
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01/21/2010
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08/05/2010
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WORK FUNCTION ADJUSTMENT IN A HIGH-K GATE ELECTRODE STRUCTURE AFTER TRANSISTOR FABRICATION BY USING LANTHANUM
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02/19/2013
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12693030
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01/25/2010
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08/05/2010
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METHOD OF FORMING A METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE BY USING A HARD MASK FOR DEFINING THE VIA SIZE
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12/04/2012
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12698191
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02/02/2010
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08/04/2011
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FIELD EFFECT TRANSISTOR (FET) AND METHOD OF FORMING THE FET WITHOUT DAMAGING THE WAFER SURFACE
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02/19/2013
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12698448
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02/02/2010
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08/12/2010
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CUT FIRST METHODOLOGY FOR DOUBLE EXPOSURE DOUBLE ETCH INTEGRATION
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02/14/2012
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12706676
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02/16/2010
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06/10/2010
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OVERHEAD TRANSPORT SERVICE VEHICLE AND METHOD
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07/17/2012
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12707150
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02/17/2010
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08/18/2011
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01/15/2013
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12708213
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02/18/2010
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08/18/2011
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FINNED SEMICONDUCTOR DEVICE WITH OXYGEN DIFFUSION BARRIER REGIONS, AND RELATED FABRICATION METHODS
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06/11/2013
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12709966
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02/22/2010
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09/02/2010
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TRANSISTOR COMPRISING AN EMBEDDED SEMICONDUCTOR ALLOY IN DRAIN AND SOURCE REGIONS EXTENDING UNDER THE GATE ELECTRODE
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