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Patent #:
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Issue Dt:
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03/20/2012
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Application #:
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12715781
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Filing Dt:
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03/02/2010
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Publication #:
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Pub Dt:
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09/23/2010
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Title:
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METHOD AND STRUCTURE FOR GATE HEIGHT SCALING WITH HIGH-K/METAL GATE TECHNOLOGY
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Patent #:
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Issue Dt:
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05/28/2013
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Application #:
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12719934
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Filing Dt:
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03/09/2010
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Publication #:
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Pub Dt:
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09/15/2011
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Title:
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MOSFETS WITH REDUCED CONTACT RESISTANCE
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Patent #:
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Issue Dt:
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11/27/2012
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Application #:
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12721608
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Filing Dt:
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03/11/2010
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Publication #:
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Pub Dt:
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09/15/2011
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Title:
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HIGH-K DIELECTRIC GATE STRUCTURES RESISTANT TO OXIDE GROWTH AT THE DIELECTRIC/SILICON SUBSTRATE INTERFACE AND METHODS OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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11/08/2011
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Application #:
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12731802
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Filing Dt:
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03/25/2010
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Publication #:
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Pub Dt:
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09/29/2011
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Title:
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DIE LEVEL INTEGRATED INTERCONNECT DECAL MANUFACTURING METHOD AND APPARATUS
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Patent #:
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Issue Dt:
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02/19/2013
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Application #:
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12748992
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Filing Dt:
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03/29/2010
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Publication #:
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Pub Dt:
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09/30/2010
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Title:
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MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY AN OFFSET SPACER USED TO DETERMINE AN OFFSET OF A STRAIN-INDUCING SEMICONDUCTOR ALLOY
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Patent #:
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Issue Dt:
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12/04/2012
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Application #:
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12749805
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Filing Dt:
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03/30/2010
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Publication #:
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Pub Dt:
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09/30/2010
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Title:
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TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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12755752
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Filing Dt:
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04/07/2010
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Publication #:
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Pub Dt:
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10/13/2011
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Title:
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SELF-ALIGNED CONTACTS
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Patent #:
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Issue Dt:
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01/08/2013
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Application #:
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12755983
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Filing Dt:
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04/07/2010
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Publication #:
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Pub Dt:
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10/13/2011
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Title:
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INTEGRATED CIRCUITS HAVING BACKSIDE TEST STRUCTURES AND METHODS FOR THE FABRICATION THEREOF
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Patent #:
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Issue Dt:
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11/27/2012
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Application #:
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12760287
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Filing Dt:
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04/14/2010
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Publication #:
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Pub Dt:
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10/20/2011
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Title:
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TUNNEL FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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10/16/2012
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Application #:
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12763284
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Filing Dt:
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04/20/2010
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Publication #:
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Pub Dt:
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10/20/2011
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Title:
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INTEGRATED CIRCUIT WITH REPLACEMENT METAL GATES AND DUAL DIELECTRICS
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Patent #:
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Issue Dt:
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01/10/2012
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Application #:
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12763596
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Filing Dt:
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04/20/2010
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Publication #:
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Pub Dt:
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08/12/2010
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Title:
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LOCK AND KEY THROUGH-VIA METHOD FOR WAFER LEVEL 3D INTEGRATION AND STRUCTURES PRODUCED
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Patent #:
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Issue Dt:
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01/22/2013
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Application #:
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12773219
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Filing Dt:
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05/04/2010
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Publication #:
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Pub Dt:
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11/10/2011
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Title:
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DUAL DAMASCENE-LIKE SUBTRACTIVE METAL ETCH SCHEME
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Patent #:
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Issue Dt:
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08/14/2012
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Application #:
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12776885
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Filing Dt:
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05/10/2010
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Publication #:
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Pub Dt:
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11/10/2011
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Title:
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METHOD FOR AIR GAP INTERCONNECT INTEGRATION USING PHOTO-PATTERNABLE LOW K MATERIAL
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Patent #:
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Issue Dt:
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12/11/2012
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Application #:
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12783702
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Filing Dt:
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05/20/2010
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Publication #:
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Pub Dt:
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11/24/2011
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Title:
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FOREIGN MATERIAL CONTAMINATION DETECTION
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Patent #:
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Issue Dt:
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03/19/2013
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Application #:
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12786829
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Filing Dt:
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05/25/2010
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Publication #:
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Pub Dt:
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12/02/2010
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Title:
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ESTABLISHING A HYDROPHOBIC SURFACE OF SENSITIVE LOW-K DIELECTRICS OF MICROSTRUCTURE DEVICES BY IN SITU PLASMA TREATMENT
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Patent #:
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Issue Dt:
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02/12/2013
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Application #:
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12788912
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Filing Dt:
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05/27/2010
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Publication #:
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Pub Dt:
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12/01/2011
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Title:
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INTERCONNECT STRUCTURE WITH AN OXYGEN-DOPED SIC ANTIREFLECTIVE COATING AND METHOD OF FABRICATION
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Patent #:
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Issue Dt:
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02/26/2013
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Application #:
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12789699
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Filing Dt:
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05/28/2010
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Publication #:
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Pub Dt:
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12/01/2011
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Title:
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THIN CHANNEL DEVICE AND FABRICATION METHOD WITH A REVERSE EMBEDDED STRESSOR
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Patent #:
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Issue Dt:
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01/31/2012
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Application #:
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12795681
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Filing Dt:
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06/08/2010
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Publication #:
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Pub Dt:
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12/16/2010
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Title:
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LOCAL METALLIZATION AND USE THEREOF IN SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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12/18/2012
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Application #:
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12814162
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Filing Dt:
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06/11/2010
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Publication #:
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Pub Dt:
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12/15/2011
| | | | |
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Title:
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INTERCONNECT STRUCTURE AND METHOD OF FABRICATING
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Patent #:
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Issue Dt:
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10/23/2012
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Application #:
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12819634
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Filing Dt:
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06/21/2010
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Publication #:
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Pub Dt:
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12/22/2011
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Title:
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METHOD AND STRUCTURE OF FORMING SILICIDE AND DIFFUSION BARRIER LAYER WITH DIRECT DEPOSITED FILM ON SILICON
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Patent #:
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Issue Dt:
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02/26/2013
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Application #:
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12823438
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Filing Dt:
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06/25/2010
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Publication #:
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Pub Dt:
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12/30/2010
| | | | |
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Title:
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CONTACT OPTIMIZATION FOR ENHANCING STRESS TRANSFER IN CLOSELY SPACED TRANSISTORS
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Patent #:
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Issue Dt:
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10/09/2012
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Application #:
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12824614
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Filing Dt:
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06/28/2010
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Publication #:
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Pub Dt:
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12/30/2010
| | | | |
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Title:
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ENHANCING SELECTIVITY DURING FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY A WET OXIDATION PROCESS
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Patent #:
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Issue Dt:
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01/15/2013
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Application #:
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12839697
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Filing Dt:
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07/20/2010
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Publication #:
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Pub Dt:
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01/26/2012
| | | | |
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Title:
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METHODS TO FORM SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURES
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Patent #:
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Issue Dt:
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01/29/2013
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Application #:
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12843350
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Filing Dt:
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07/26/2010
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Publication #:
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Pub Dt:
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01/26/2012
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Title:
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SELF-ALIGNED SILICIDATION FOR REPLACEMENT GATE PROCESS
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Patent #:
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Issue Dt:
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08/14/2012
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Application #:
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12845065
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Filing Dt:
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07/28/2010
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Publication #:
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Pub Dt:
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02/02/2012
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Title:
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INTEGRATED CIRCUIT STRUCTURE INCORPORATING A CONDUCTOR LAYER WITH BOTH TOP SURFACE AND SIDEWALL PASSIVATION AND A METHOD OF FORMING THE INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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12848494
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Filing Dt:
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08/02/2010
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Publication #:
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Pub Dt:
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02/02/2012
| | | | |
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Title:
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RAISED SOURCE/DRAIN FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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07/31/2012
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Application #:
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12851206
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Filing Dt:
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08/05/2010
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Publication #:
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Pub Dt:
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02/09/2012
| | | | |
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Title:
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SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURE FORMED BY PITCH SPLITTING
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Patent #:
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Issue Dt:
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11/13/2012
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Application #:
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12855273
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Filing Dt:
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08/12/2010
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Publication #:
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Pub Dt:
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02/16/2012
| | | | |
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Title:
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METHOD FOR INTEGRATING MULTIPLE THRESHOLD VOLTAGE DEVICES FOR CMOS
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Patent #:
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Issue Dt:
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01/15/2013
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Application #:
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12855738
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Filing Dt:
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08/13/2010
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Publication #:
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Pub Dt:
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02/16/2012
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Title:
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CMOS TRANSISTORS WITH STRESSED HIGH MOBILITY CHANNELS
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Patent #:
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Issue Dt:
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10/16/2012
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Application #:
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12857864
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Filing Dt:
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08/17/2010
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Publication #:
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Pub Dt:
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02/23/2012
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Title:
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SER TESTING FOR AN IC CHIP USING HOT UNDERFILL
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Patent #:
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Issue Dt:
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12/18/2012
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Application #:
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12858727
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Filing Dt:
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08/18/2010
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Publication #:
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Pub Dt:
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03/03/2011
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Title:
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BURIED ETCH STOP LAYER IN TRENCH ISOLATION STRUCTURES FOR SUPERIOR SURFACE PLANARITY IN DENSELY PACKED SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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12869341
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Filing Dt:
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08/26/2010
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Publication #:
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Pub Dt:
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03/01/2012
| | | | |
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Title:
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METHOD OF FABRICATING A SEMICONDUCTOR DEVICE USING COMPRESSIVE MATERIAL WITH A REPLACEMENT GATE TECHNIQUE
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Patent #:
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Issue Dt:
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01/29/2013
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Application #:
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12876480
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Filing Dt:
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09/07/2010
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Publication #:
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Pub Dt:
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03/08/2012
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Title:
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HIGH PERFORMANCE LOW POWER BULK FET DEVICE AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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07/10/2012
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Application #:
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12880478
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Filing Dt:
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09/13/2010
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Publication #:
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Pub Dt:
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12/30/2010
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Title:
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PROCESS TO FABRICATE A METAL HIGH-K TRANSISTOR HAVING FIRST AND SECOND SILICON SIDEWALLS FOR REDUCED PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
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09/11/2012
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Application #:
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12881152
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Filing Dt:
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09/13/2010
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Publication #:
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Pub Dt:
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03/15/2012
| | | | |
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Title:
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ASYMMETRIC FINFET DEVICES
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Patent #:
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Issue Dt:
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01/14/2014
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Application #:
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12885592
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Filing Dt:
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09/20/2010
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Publication #:
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Pub Dt:
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03/22/2012
| | | | |
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Title:
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Replacement Metal Gate Structures for Effective Work Function Control
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Patent #:
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|
Issue Dt:
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06/11/2013
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Application #:
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12892465
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Filing Dt:
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09/28/2010
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Publication #:
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Pub Dt:
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03/29/2012
| | | | |
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Title:
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USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES
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Patent #:
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Issue Dt:
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02/05/2013
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Application #:
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12895116
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Filing Dt:
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09/30/2010
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Publication #:
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Pub Dt:
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05/05/2011
| | | | |
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Title:
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METHOD FOR FORMING SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES
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Patent #:
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Issue Dt:
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04/02/2013
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Application #:
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12900085
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Filing Dt:
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10/07/2010
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Publication #:
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Pub Dt:
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04/12/2012
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Title:
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METHOD AND APPARATUS FOR ROUTING DISPATCHING AND ROUTING RETICLES
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Patent #:
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Issue Dt:
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07/24/2012
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Application #:
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12900095
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Filing Dt:
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10/07/2010
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Publication #:
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Pub Dt:
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04/12/2012
| | | | |
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Title:
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METHOD OF FORMING ENHANCED CAPACITANCE TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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09/04/2012
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Application #:
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12900578
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Filing Dt:
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10/08/2010
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Publication #:
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Pub Dt:
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06/02/2011
| | | | |
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Title:
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PERFORMANCE ENHANCEMENT IN TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY REDUCING A WIDTH OF OFFSET SPACERS
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Patent #:
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Issue Dt:
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03/26/2013
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Application #:
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12902776
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Filing Dt:
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10/12/2010
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Publication #:
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Pub Dt:
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04/12/2012
| | | | |
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Title:
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DEVICES WITH GATE-TO-GATE ISOLATION STRUCTURES AND METHODS OF MANUFACTURE
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Patent #:
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|
Issue Dt:
|
01/15/2013
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Application #:
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12905575
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Filing Dt:
|
10/15/2010
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Publication #:
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Pub Dt:
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04/19/2012
| | | | |
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Title:
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INTEGRATED PLANAR AND MULTIPLE GATE FETS
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Patent #:
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Issue Dt:
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12/11/2012
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Application #:
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12905655
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Filing Dt:
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10/15/2010
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Publication #:
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Pub Dt:
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06/02/2011
| | | | |
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Title:
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CAP REMOVAL IN A HIGH-K METAL GATE ELECTRODE STRUCTURE BY USING A SACRIFICIAL FILL MATERIAL
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|
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Patent #:
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Issue Dt:
|
06/11/2013
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Application #:
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12908306
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Filing Dt:
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10/20/2010
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Publication #:
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Pub Dt:
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04/26/2012
| | | | |
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Title:
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LOCALIZED IMPLANT INTO ACTIVE REGION FOR ENHANCED STRESS
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Patent #:
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Issue Dt:
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01/08/2013
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Application #:
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12909149
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Filing Dt:
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10/21/2010
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Publication #:
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Pub Dt:
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06/30/2011
| | | | |
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Title:
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ENHANCED CONFINEMENT OF HIGH-K METAL GATE ELECTRODE STRUCTURES BY REDUCING MATERIAL EROSION OF A DIELECTRIC CAP LAYER UPON FORMING A STRAIN-INDUCING SEMICONDUCTOR ALLOY
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Patent #:
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Issue Dt:
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10/30/2012
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Application #:
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12912940
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Filing Dt:
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10/27/2010
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Publication #:
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Pub Dt:
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05/03/2012
| | | | |
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Title:
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GERMANIUM-CONTAINING RELEASE LAYER FOR TRANSFER OF A SILICON LAYER TO A SUBSTRATE
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12916681
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Filing Dt:
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11/01/2010
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Publication #:
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Pub Dt:
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02/24/2011
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Title:
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REDUCING THE CREATION OF CHARGE TRAPS AT GATE DIELECTRICS IN MOS TRANSISTORS BY PERFORMING A HYDROGEN TREATMENT
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Patent #:
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Issue Dt:
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04/23/2013
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Application #:
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12938457
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Filing Dt:
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11/03/2010
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Publication #:
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Pub Dt:
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05/03/2012
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Title:
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METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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12939424
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Filing Dt:
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11/04/2010
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Publication #:
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Pub Dt:
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09/01/2011
| | | | |
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Title:
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METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE COMPRISING ROUNDED INTERCONNECTS FORMED BY HARD MASK ROUNDING
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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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12940115
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Filing Dt:
|
11/05/2010
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Publication #:
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Pub Dt:
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05/10/2012
| | | | |
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Title:
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STRAINED SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING STRAINED SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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02/21/2012
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Application #:
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12941184
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11/08/2010
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Title:
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Issue Dt:
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03/12/2013
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12941375
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11/08/2010
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Publication #:
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Pub Dt:
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05/10/2012
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Title:
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Issue Dt:
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04/16/2013
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12942097
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11/09/2010
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05/10/2012
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Title:
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04/16/2013
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12942378
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11/09/2010
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Pub Dt:
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10/06/2011
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Title:
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04/02/2013
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12944174
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11/11/2010
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05/17/2012
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Title:
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06/19/2012
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12947150
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11/16/2010
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05/17/2012
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Title:
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02/19/2013
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12951575
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11/22/2010
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05/24/2012
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Title:
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10/30/2012
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12954155
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11/24/2010
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05/24/2012
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Title:
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03/13/2012
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12959943
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12/03/2010
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Title:
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12/16/2014
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12/14/2010
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06/14/2012
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Title:
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05/22/2012
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12973373
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12/20/2010
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06/04/2013
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01/14/2011
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07/19/2012
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11/20/2012
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01/20/2011
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07/28/2011
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10/02/2012
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01/24/2011
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07/26/2012
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Title:
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12/02/2014
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13013067
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01/25/2011
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07/26/2012
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Title:
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05/01/2012
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01/25/2011
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05/19/2011
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02/12/2013
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01/25/2011
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07/26/2012
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02/21/2012
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01/26/2011
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02/19/2013
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01/27/2011
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08/02/2012
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07/31/2012
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01/28/2011
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05/26/2011
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05/22/2012
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02/02/2011
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05/26/2011
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02/19/2013
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13020369
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02/03/2011
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08/09/2012
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03/05/2013
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02/11/2011
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08/16/2012
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12/04/2012
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02/25/2011
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02/02/2012
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10/23/2012
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02/25/2011
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08/30/2012
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07/31/2012
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03/11/2011
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06/30/2011
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01/08/2013
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03/25/2011
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09/27/2012
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11/06/2012
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03/28/2011
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10/04/2012
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11/18/2014
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04/15/2011
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10/18/2012
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07/10/2012
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04/26/2011
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08/18/2011
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01/29/2013
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05/05/2011
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09/08/2011
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11/22/2012
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12/27/2011
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09/15/2011
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12/13/2012
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04/16/2013
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06/21/2011
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12/27/2012
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07/11/2011
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09/25/2012
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11/10/2011
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06/18/2013
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01/31/2013
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11/04/2014
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07/31/2011
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01/31/2013
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06/02/2015
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09/12/2011
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08/27/2013
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