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Patent #:
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Issue Dt:
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05/21/2013
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Application #:
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13343819
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Filing Dt:
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01/05/2012
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Title:
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INTEGRATED CIRCUIT HAVING BACK GATING, IMPROVED ISOLATION AND REDUCED WELL RESISTANCE AND METHOD TO FABRICATE SAME
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Patent #:
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Issue Dt:
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10/14/2014
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Application #:
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13345439
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Filing Dt:
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01/06/2012
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Publication #:
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Pub Dt:
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07/11/2013
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Title:
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LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13351041
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Filing Dt:
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01/16/2012
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Publication #:
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Pub Dt:
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05/10/2012
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Title:
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DIFFUSION SIDEWALL FOR A SEMICONDUCTOR STRUCTURE
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Patent #:
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Issue Dt:
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03/05/2013
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Application #:
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13353013
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Filing Dt:
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01/18/2012
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Publication #:
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Pub Dt:
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05/17/2012
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Title:
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GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE
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Patent #:
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Issue Dt:
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10/23/2012
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Application #:
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13354371
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Filing Dt:
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01/20/2012
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Publication #:
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Pub Dt:
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05/10/2012
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Title:
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METHOD OF FABRICATING DAMASCENE STRUCTURES
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Patent #:
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Issue Dt:
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07/02/2013
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Application #:
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13357757
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Filing Dt:
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01/25/2012
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Publication #:
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Pub Dt:
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05/24/2012
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Title:
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SEMICONDUCTOR TRANSISTORS HAVING REDUCED DISTANCES BETWEEN GATE ELECTRODE REGIONS
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Patent #:
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Issue Dt:
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07/24/2012
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Application #:
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13364564
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Filing Dt:
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02/02/2012
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Publication #:
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Pub Dt:
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05/24/2012
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Title:
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METHOD AND STRUCTURE FOR GATE HEIGHT SCALING WITH HIGH-K/METAL GATE TECHNOLOGY
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Patent #:
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Issue Dt:
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04/16/2013
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Application #:
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13405443
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Filing Dt:
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02/27/2012
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Publication #:
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Pub Dt:
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06/21/2012
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Title:
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STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13406664
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Filing Dt:
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02/28/2012
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Publication #:
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Pub Dt:
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06/21/2012
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Title:
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INTEGRATED CIRCUIT AND A METHOD USING INTEGRATED PROCESS STEPS TO FORM DEEP TRENCH ISOLATION STRUCTURES AND DEEP TRENCH CAPACITOR STRUCTURES FOR THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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08/20/2013
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Application #:
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13409693
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Filing Dt:
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03/01/2012
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Publication #:
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Pub Dt:
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07/05/2012
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Title:
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STRUCTURE AND METHOD TO IMPROVE THRESHOLD VOLTAGE OF MOSFETS INCLUDING A HIGH K DIELECTRIC
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Patent #:
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Issue Dt:
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06/23/2015
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Application #:
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13418476
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Filing Dt:
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03/13/2012
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Publication #:
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Pub Dt:
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09/19/2013
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Title:
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BREAKDOWN VOLTAGE MULTIPLYING INTEGRATION SCHEME
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Patent #:
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Issue Dt:
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01/14/2014
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Application #:
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13420730
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Filing Dt:
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03/15/2012
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Publication #:
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Pub Dt:
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07/05/2012
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Title:
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ASYMMETRIC FET INCLUDING SLOPED THRESHOLD VOLTAGE ADJUSTING MATERIAL LAYER AND METHOD OF FABRICATING SAME
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Patent #:
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Issue Dt:
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12/03/2013
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Application #:
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13420763
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Filing Dt:
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03/15/2012
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Publication #:
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Pub Dt:
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07/05/2012
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Title:
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FIELD EFFECT TRANSISTOR (FET) AND METHOD OF FORMING THE FET WITHOUT DAMAGING THE WAFER SURFACE
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Patent #:
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Issue Dt:
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02/17/2015
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Application #:
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13431343
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Filing Dt:
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03/27/2012
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Publication #:
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Pub Dt:
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10/03/2013
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Title:
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BOTTOM-UP PLATING OF THROUGH-SUBSTRATE VIAS
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Patent #:
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Issue Dt:
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08/06/2013
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Application #:
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13432395
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Filing Dt:
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03/28/2012
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Publication #:
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Pub Dt:
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07/26/2012
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Title:
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METAL HIGH-K TRANSISTOR HAVING SILICON SIDEWALLS FOR REDUCED PARASITIC CAPACITANCE
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Patent #:
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Issue Dt:
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07/23/2013
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Application #:
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13434883
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Filing Dt:
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03/30/2012
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Publication #:
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Pub Dt:
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07/26/2012
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Title:
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ENHANCED CAPACITANCE TRENCH CAPACITOR
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Patent #:
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Issue Dt:
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07/14/2015
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Application #:
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13434934
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Filing Dt:
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03/30/2012
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Publication #:
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Pub Dt:
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07/26/2012
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Title:
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METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION
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Patent #:
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Issue Dt:
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11/04/2014
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Application #:
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13435056
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Filing Dt:
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03/30/2012
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Publication #:
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Pub Dt:
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10/03/2013
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Title:
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SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13444343
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Filing Dt:
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04/11/2012
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Publication #:
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Pub Dt:
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10/17/2013
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Title:
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SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE
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Patent #:
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Issue Dt:
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02/03/2015
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Application #:
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13451054
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Filing Dt:
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04/19/2012
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Publication #:
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Pub Dt:
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10/24/2013
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Title:
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Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric
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Patent #:
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Issue Dt:
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01/20/2015
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Application #:
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13454635
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Filing Dt:
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04/24/2012
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Publication #:
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Pub Dt:
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08/16/2012
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Title:
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INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT
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Patent #:
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Issue Dt:
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08/05/2014
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Application #:
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13454723
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Filing Dt:
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04/24/2012
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Publication #:
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Pub Dt:
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08/16/2012
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Title:
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SELF-ALIGNED PERMANENT ON-CHIP INTERCONNECT STRUCTURE FORMED BY PITCH SPLITTING
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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13457529
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Filing Dt:
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04/27/2012
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Publication #:
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Pub Dt:
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10/31/2013
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Title:
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FINFET WITH ENHANCED EMBEDDED STRESSOR
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Patent #:
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Issue Dt:
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07/22/2014
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Application #:
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13468223
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Filing Dt:
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05/10/2012
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Publication #:
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Pub Dt:
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09/13/2012
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Title:
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PASSIVATION LAYER SURFACE TOPOGRAPHY MODIFICATIONS FOR IMPROVED INTEGRITY IN PACKAGED ASSEMBLIES
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Patent #:
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Issue Dt:
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09/16/2014
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Application #:
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13468232
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Filing Dt:
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05/10/2012
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Publication #:
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Pub Dt:
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09/13/2012
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Title:
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METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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13468576
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Filing Dt:
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05/10/2012
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Publication #:
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Pub Dt:
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11/14/2013
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Title:
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PRINTED TRANSISTOR AND FABRICATION METHOD
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Patent #:
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Issue Dt:
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12/02/2014
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Application #:
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13470393
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Filing Dt:
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05/14/2012
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Publication #:
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Pub Dt:
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09/06/2012
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Title:
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Asymmetric FinFET devices
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Patent #:
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Issue Dt:
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08/27/2013
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Application #:
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13471684
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Filing Dt:
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05/15/2012
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Publication #:
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Pub Dt:
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09/06/2012
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Title:
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DOPANT MARKER FOR PRECISE RECESS CONTROL
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Patent #:
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Issue Dt:
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02/17/2015
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Application #:
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13472747
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Filing Dt:
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05/16/2012
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Publication #:
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Pub Dt:
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11/21/2013
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Title:
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Epitaxial Semiconductor Resistor With Semiconductor Structures On Same Substrate
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Patent #:
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Issue Dt:
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05/26/2015
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Application #:
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13478154
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Filing Dt:
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05/23/2012
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Publication #:
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Pub Dt:
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11/28/2013
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Title:
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STRUCTURE AND METHOD TO MODULATE THRESHOLD VOLTAGE FOR HIGH-K METAL GATE FIELD EFFECT TRANSISTORS (FETS)
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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13488109
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Filing Dt:
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06/04/2012
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Publication #:
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Pub Dt:
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09/20/2012
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Title:
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METHODS FOR FORMING BARRIER REGIONS WITHIN REGIONS OF INSULATING MATERIAL RESULTING IN OUTGASSING PATHS FROM THE INSULATING MATERIAL AND RELATED DEVICES
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Patent #:
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Issue Dt:
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06/02/2015
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Application #:
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13488678
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Filing Dt:
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06/05/2012
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Publication #:
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Pub Dt:
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12/05/2013
| | | | |
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Title:
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METHOD FOR SHAPING A LAMINATE SUBSTRATE
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Patent #:
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Issue Dt:
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09/08/2015
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Application #:
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13488685
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Filing Dt:
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06/05/2012
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Publication #:
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Pub Dt:
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12/05/2013
| | | | |
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Title:
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METHOD FOR SHAPING A LAMINATE SUBSTRATE
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Patent #:
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Issue Dt:
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08/12/2014
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Application #:
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13490542
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Filing Dt:
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06/07/2012
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Publication #:
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Pub Dt:
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12/12/2013
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Title:
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DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME
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Patent #:
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Issue Dt:
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08/04/2015
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Application #:
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13490740
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Filing Dt:
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06/07/2012
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Publication #:
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Pub Dt:
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12/12/2013
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Title:
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METHOD OF MANUFACTURING SCALED EQUIVALENT OXIDE THICKNESS GATE STACKS IN SEMICONDUCTOR DEVICES AND RELATED DESIGN STRUCTURE
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Patent #:
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Issue Dt:
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07/07/2015
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Application #:
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13528257
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Filing Dt:
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06/20/2012
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Publication #:
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Pub Dt:
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12/26/2013
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Title:
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SEMICONDUCTOR DEVICE FABRICATION METHODS
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Patent #:
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Issue Dt:
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03/25/2014
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Application #:
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13530549
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Filing Dt:
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06/22/2012
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Publication #:
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Pub Dt:
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10/11/2012
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Title:
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NANOPILLAR DECOUPLING CAPACITOR
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Patent #:
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Issue Dt:
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12/23/2014
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Application #:
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13534407
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Filing Dt:
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06/27/2012
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Publication #:
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Pub Dt:
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01/02/2014
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Title:
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SEMICONDUCTOR DEVICE WITH EPITAXIAL SOURCE/DRAIN FACETTING PROVIDED AT THE GATE EDGE
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Patent #:
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Issue Dt:
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01/27/2015
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Application #:
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13541979
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Filing Dt:
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07/05/2012
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Publication #:
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Pub Dt:
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01/09/2014
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Title:
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INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME HAVING A REPLACEMENT GATE STRUCTURE
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13553264
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Filing Dt:
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07/19/2012
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Publication #:
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Pub Dt:
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11/08/2012
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Title:
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HOMOGENEOUS POROUS LOW DIELECTRIC CONSTANT MATERIALS
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Patent #:
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Issue Dt:
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07/01/2014
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Application #:
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13558518
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Filing Dt:
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07/26/2012
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Publication #:
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Pub Dt:
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11/15/2012
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Title:
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TUNNEL FIELD EFFECT TRANSISTOR
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Patent #:
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Issue Dt:
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05/06/2014
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Application #:
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13571521
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Filing Dt:
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08/10/2012
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Publication #:
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Pub Dt:
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12/06/2012
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Title:
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FABRICATION OF DEVICES HAVING DIFFERENT INTERFACIAL OXIDE THICKNESS VIA LATERAL OXIDATION
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Patent #:
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Issue Dt:
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10/07/2014
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Application #:
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13610641
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Filing Dt:
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09/11/2012
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Publication #:
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Pub Dt:
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01/03/2013
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Title:
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SILICON GERMANIUM (SIGE) HETEROJUNCTION BIPOLAR TRANSISTOR (HBT)
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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13611387
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Filing Dt:
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09/12/2012
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Publication #:
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Pub Dt:
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10/10/2013
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Title:
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DEVICE AND METHOD FOR FORMING SHARP EXTENSION REGION WITH CONTROLLABLE JUNCTION DEPTH AND LATERAL OVERLAP
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Patent #:
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Issue Dt:
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12/23/2014
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Application #:
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13613890
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Filing Dt:
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09/13/2012
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Publication #:
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Pub Dt:
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01/10/2013
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Title:
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INTERCONNECT STRUCTURE AND METHOD OF FABRICATING
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Patent #:
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Issue Dt:
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08/11/2015
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Application #:
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13614062
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Filing Dt:
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09/13/2012
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Publication #:
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Pub Dt:
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03/13/2014
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Title:
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METHOD OF REPLACEMENT SOURCE/DRAIN FOR 3D CMOS TRANSISTORS
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Patent #:
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Issue Dt:
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12/24/2013
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Application #:
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13614072
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Filing Dt:
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09/13/2012
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Publication #:
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Pub Dt:
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01/10/2013
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Title:
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VERTICAL NPNP STRUCTURE IN A TRIPLE WELL CMOS PROCESS
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Patent #:
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Issue Dt:
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01/13/2015
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Application #:
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13616322
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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01/17/2013
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Title:
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GERMANIUM-CONTAINING RELEASE LAYER FOR TRANSFER OF A SILICON LAYER TO A SUBSTRATE
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Patent #:
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Issue Dt:
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01/07/2014
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Application #:
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13617866
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Filing Dt:
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09/14/2012
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Publication #:
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Pub Dt:
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07/11/2013
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Title:
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METHOD FOR FABRICATING SILICON-ON-INSULATOR TRANSISTOR WITH SELF-ALIGNED BORDERLESS SOURCE/DRAIN CONTACTS
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Patent #:
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Issue Dt:
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12/23/2014
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Application #:
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13623132
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Filing Dt:
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09/20/2012
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Publication #:
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Pub Dt:
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03/20/2014
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Title:
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Electronic Fuse Vias in Interconnect Structures
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Patent #:
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Issue Dt:
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07/14/2015
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Application #:
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13623276
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Filing Dt:
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09/20/2012
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Publication #:
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Pub Dt:
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03/20/2014
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Title:
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METHOD AND STRUCTURE FOR FINFET WITH FINELY CONTROLLED DEVICE WIDTH
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Patent #:
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Issue Dt:
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01/06/2015
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Application #:
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13627179
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Filing Dt:
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09/26/2012
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Publication #:
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Pub Dt:
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03/27/2014
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Title:
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METHOD TO BRIDGE EXTRINSIC AND INTRINSIC BASE BY SELECTIVE EPITAXY IN BICMOS TECHNOLOGY
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Patent #:
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Issue Dt:
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07/21/2015
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Application #:
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13633973
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Filing Dt:
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10/03/2012
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Publication #:
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04/03/2014
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TRANSISTOR FORMATION USING COLD WELDING
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08/18/2015
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13646120
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10/05/2012
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04/10/2014
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01/27/2015
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10/25/2012
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04/03/2014
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02/03/2015
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10/30/2012
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05/01/2014
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06/24/2014
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13667312
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11/02/2012
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03/07/2013
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SEGREGATING WAFER CARRIER TYPES IN SEMICONDUCTOR STORAGE DEVICES
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01/06/2015
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11/28/2012
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05/29/2014
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02/18/2014
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11/30/2012
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01/16/2014
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07/15/2014
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12/03/2012
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04/18/2013
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07/28/2015
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12/13/2012
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06/19/2014
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METHODS OF FORMING A SIDEWALL SPACER HAVING A GENERALLY TRIANGULAR SHAPE AND A SEMICONDUCTOR DEVICE HAVING SUCH A SPACER
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06/03/2014
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12/18/2012
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05/23/2013
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01/28/2014
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12/21/2012
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05/23/2013
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08/04/2015
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12/28/2012
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07/03/2014
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10/06/2015
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01/02/2013
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06/06/2013
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08/11/2015
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01/07/2013
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07/10/2014
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03/17/2015
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01/09/2013
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07/10/2014
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09/16/2014
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01/24/2013
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05/30/2013
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11/11/2014
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01/30/2013
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07/31/2014
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06/17/2014
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02/01/2013
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10/14/2014
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02/01/2013
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08/07/2014
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10/27/2015
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02/15/2013
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08/21/2014
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07/15/2014
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13772401
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02/21/2013
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06/27/2013
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06/03/2014
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02/25/2013
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07/04/2013
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07/21/2015
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02/26/2013
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08/28/2014
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06/16/2015
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03/04/2013
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09/04/2014
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07/21/2015
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13785934
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03/05/2013
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09/11/2014
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07/28/2015
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03/08/2013
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09/11/2014
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12/09/2014
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13826628
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03/14/2013
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09/18/2014
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01/06/2015
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13847662
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03/20/2013
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08/22/2013
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03/03/2015
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04/09/2013
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09/05/2013
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09/22/2015
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04/10/2013
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10/16/2014
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03/31/2015
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13868412
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04/23/2013
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10/23/2014
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09/29/2015
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05/16/2013
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11/20/2014
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11/04/2014
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05/17/2013
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11/20/2014
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07/21/2015
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05/22/2013
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11/27/2014
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07/21/2015
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05/23/2013
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11/27/2014
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BULK SEMICONDUCTOR FINS WITH SELF-ALIGNED SHALLOW TRENCH ISOLATION STRUCTURES
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06/23/2015
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13905442
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05/30/2013
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12/04/2014
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SUBSTRATE BONDING WITH DIFFUSION BARRIER STRUCTURES
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03/24/2015
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06/03/2013
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10/10/2013
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07/21/2015
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06/24/2013
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11/27/2014
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08/04/2015
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07/02/2013
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01/08/2015
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Semiconductor Device with Distinct Multiple-Patterned Conductive Tracks on a Same Level
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10/27/2015
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07/22/2013
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01/22/2015
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ALIGNMENT OF INTEGRATED CIRCUIT CHIP STACK
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07/28/2015
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07/24/2013
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01/29/2015
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09/15/2015
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07/26/2013
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01/29/2015
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07/28/2015
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07/29/2013
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01/29/2015
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06/16/2015
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08/06/2013
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02/12/2015
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07/07/2015
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08/27/2013
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03/05/2015
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08/11/2015
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09/04/2013
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03/05/2015
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11/04/2014
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09/06/2013
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11/27/2014
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10/13/2015
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09/09/2013
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03/12/2015
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