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Patent Assignment Details

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Reel/Frame:	049612/0211			Pages:	20
		Recorded:	06/27/2019
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 329
Page 4 of 4
Pages: 1 2 3 4

Patent #:	9105517	Issue Dt:	08/11/2015	Application #:	14025119	Filing Dt:	09/12/2013
Publication #:	US20150069421	Pub Dt:	03/12/2015
Title:	WAFER TO WAFER ALIGNMENT BY LED/LSD DEVICES

Patent #:	9159633	Issue Dt:	10/13/2015	Application #:	14026172	Filing Dt:	09/13/2013
Publication #:	US20150076498	Pub Dt:	03/19/2015
Title:	TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS

Patent #:	9093560	Issue Dt:	07/28/2015	Application #:	14032740	Filing Dt:	09/20/2013
Publication #:	US20150084131	Pub Dt:	03/26/2015
Title:	GATE HEIGHT UNIFORMITY IN SEMICONDUCTOR DEVICES

Patent #:	9111756	Issue Dt:	08/18/2015	Application #:	14033789	Filing Dt:	09/23/2013
Publication #:	US20150084183	Pub Dt:	03/26/2015
Title:	INTEGRATED CIRCUITS WITH PROTECTED RESISTORS AND METHODS FOR FABRICATING THE SAME

Patent #:	9147696	Issue Dt:	09/29/2015	Application #:	14043243	Filing Dt:	10/01/2013
Publication #:	US20150091094	Pub Dt:	04/02/2015
Title:	DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION

Patent #:	9093326	Issue Dt:	07/28/2015	Application #:	14058341	Filing Dt:	10/21/2013
Publication #:	US20150108572	Pub Dt:	04/23/2015
Title:	Electrically Isolated SiGe FIN Formation By Local Oxidation

Patent #:	9105677	Issue Dt:	08/11/2015	Application #:	14059531	Filing Dt:	10/22/2013
Publication #:	US20150108548	Pub Dt:	04/23/2015
Title:	BASE PROFILE OF SELF-ALIGNED BIPOLAR TRANSISTORS FOR POWER AMPLIFIER APPLICATIONS

Patent #:	9136131	Issue Dt:	09/15/2015	Application #:	14071044	Filing Dt:	11/04/2013
Publication #:	US20150123216	Pub Dt:	05/07/2015
Title:	COMMON FILL OF GATE AND SOURCE AND DRAIN CONTACTS

Patent #:	9146090	Issue Dt:	09/29/2015	Application #:	14079847	Filing Dt:	11/14/2013
Publication #:	US20150128436	Pub Dt:	05/14/2015
Title:	NOZZLE ALIGNMENT TOOL FOR A FLUID DISPENSING APPARATUS

Patent #:	9093424	Issue Dt:	07/28/2015	Application #:	14132002	Filing Dt:	12/18/2013
Publication #:	US20150171178	Pub Dt:	06/18/2015
Title:	DUAL SILICIDE INTEGRATION WITH LASER ANNEALING

Patent #:	9093387	Issue Dt:	07/28/2015	Application #:	14149898	Filing Dt:	01/08/2014
Publication #:	US20150194320	Pub Dt:	07/09/2015
Title:	METALLIC MASK PATTERNING PROCESS FOR MINIMIZING COLLATERAL ETCH OF AN UNDERLAYER

Patent #:	9123827	Issue Dt:	09/01/2015	Application #:	14153502	Filing Dt:	01/13/2014
Publication #:	US20150200142	Pub Dt:	07/16/2015
Title:	METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH FULLY SILICIDED GATE ELECTRODE STRUCTURES

Patent #:	9123825	Issue Dt:	09/01/2015	Application #:	14153521	Filing Dt:	01/13/2014
Publication #:	US20150200140	Pub Dt:	07/16/2015
Title:	METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS USING LASER INTERFERENCE LITHOGRAPHY TECHNIQUES

Patent #:	9087879	Issue Dt:	07/21/2015	Application #:	14268606	Filing Dt:	05/02/2014
Publication #:	US20150011023	Pub Dt:	01/08/2015
Title:	METHOD OF MAKING SEMICONDUCTOR DEVICE WITH DISTINCT MULTIPLE-PATTERNED CONDUCTIVE TRACKS ON A SAME LEVEL

Patent #:	9076645	Issue Dt:	07/07/2015	Application #:	14272554	Filing Dt:	05/08/2014
Title:	METHOD OF FABRICATING AN INTERLAYER STRUCTURE OF INCREASED ELASTICITY MODULUS

Patent #:	9129843	Issue Dt:	09/08/2015	Application #:	14302880	Filing Dt:	06/12/2014
Title:	INTEGRATED INDUCTOR

Patent #:	9099315	Issue Dt:	08/04/2015	Application #:	14321845	Filing Dt:	07/02/2014
Publication #:	US20150021777	Pub Dt:	01/22/2015
Title:	MOUNTING STRUCTURE AND MOUNTING STRUCTURE MANUFACTURING METHOD

Patent #:	9087880	Issue Dt:	07/21/2015	Application #:	14328760	Filing Dt:	07/11/2014
Publication #:	US20150035153	Pub Dt:	02/05/2015
Title:	REMOVING METAL FILLS IN A WIRING LAYER

Patent #:	9159630	Issue Dt:	10/13/2015	Application #:	14330063	Filing Dt:	07/14/2014
Title:	FIN FIELD-EFFECT TRANSISTOR (FINFET) DEVICE FORMED USING A SINGLE SPACER, DOUBLE HARDMASK SCHEME

Patent #:	9087859	Issue Dt:	07/21/2015	Application #:	14457273	Filing Dt:	08/12/2014
Publication #:	US20140357037	Pub Dt:	12/04/2014
Title:	FINFET WITH ENHANCED EMBEDDED STRESSOR

Patent #:	9142560	Issue Dt:	09/22/2015	Application #:	14461737	Filing Dt:	08/18/2014
Publication #:	US20140353764	Pub Dt:	12/04/2014
Title:	LAYOUT TO MINIMIZE FET VARIATION IN SMALL DIMENSION PHOTOLITHOGRAPHY

Patent #:	9093401	Issue Dt:	07/28/2015	Application #:	14473266	Filing Dt:	08/29/2014
Publication #:	US20140370705	Pub Dt:	12/18/2014
Title:	ACHIEVING GREATER PLANARITY BETWEEN UPPER SURFACES OF A LAYER AND A CONDUCTIVE STRUCTURE RESIDING THEREIN

Patent #:	9099468	Issue Dt:	08/04/2015	Application #:	14494833	Filing Dt:	09/24/2014
Publication #:	US20150041951	Pub Dt:	02/12/2015
Title:	ELECTRONIC FUSE VIAS IN INTERCONNECT STRUCTURES

Patent #:	9087733	Issue Dt:	07/21/2015	Application #:	14575677	Filing Dt:	12/18/2014
Publication #:	US20150102417	Pub Dt:	04/16/2015
Title:	DOUBLE TRENCH WELL FORMATION IN SRAM CELLS

Patent #:	9087916	Issue Dt:	07/21/2015	Application #:	14594745	Filing Dt:	01/12/2015
Publication #:	US20150126004	Pub Dt:	05/07/2015
Title:	Method for Keyhole Repair in Replacement Metal Gate Integration Through the Use of a Printable Dielectric

Assignor

Exec Dt:

11/26/2018

Assignee

303 TERRY FOX DRIVE

SUITE 300

OTTAWA, CANADA K2K 3J1

Correspondence name and address
	ALSEPHINA INNOVATIONS INC.
	1891 ROBERTSON ROAD
	SUITE 100
	OTTAWA, K2H 5B7 CANADA

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