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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	049669/0775			Pages:	9
		Recorded:	07/02/2019
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 77

Patent #:	7109099	Issue Dt:	09/19/2006	Application #:	10688047	Filing Dt:	10/17/2003
Publication #:	US20050085055	Pub Dt:	04/21/2005
Title:	END OF RANGE (EOR) SECONDARY DEFECT ENGINEERING USING SUBSTITUTIONAL CARBON DOPING

Patent #:	7067362	Issue Dt:	06/27/2006	Application #:	10689923	Filing Dt:	10/17/2003
Publication #:	US20050085056	Pub Dt:	04/21/2005
Title:	INTEGRATED CIRCUIT WITH PROTECTED IMPLANTATION PROFILES AND METHOD FOR THE FORMATION THEREOF

Patent #:	6967156	Issue Dt:	11/22/2005	Application #:	10690998	Filing Dt:	10/22/2003
Publication #:	US20050090095	Pub Dt:	04/28/2005
Title:	METHOD TO FABRICATE ALIGNED DUAL DAMASCENE OPENINGS

Patent #:	7291550	Issue Dt:	11/06/2007	Application #:	10778293	Filing Dt:	02/13/2004
Publication #:	US20050181588	Pub Dt:	08/18/2005
Title:	METHOD TO FORM A CONTACT HOLE

Patent #:	7352064	Issue Dt:	04/01/2008	Application #:	10904323	Filing Dt:	11/04/2004
Publication #:	US20060094230	Pub Dt:	05/04/2006
Title:	MULTIPLE LAYER RESIST SCHEME IMPLEMENTING ETCH RECIPE PARTICULAR TO EACH LAYER

Patent #:	7268048	Issue Dt:	09/11/2007	Application #:	10913214	Filing Dt:	08/06/2004
Publication #:	US20060030095	Pub Dt:	02/09/2006
Title:	METHODS FOR ELIMINATION OF ARSENIC BASED DEFECTS IN SEMICONDUCTOR DEVICES WITH ISOLATION REGIONS

Patent #:	7271110	Issue Dt:	09/18/2007	Application #:	11029835	Filing Dt:	01/05/2005
Publication #:	US20060148270	Pub Dt:	07/06/2006
Title:	HIGH DENSITY PLASMA AND BIAS RF POWER PROCESS TO MAKE STABLE FSG WITH LESS FREE F AND SIN WITH LESS H TO ENHANCE THE FSG/SIN INTEGRATION RELIABILITY

Patent #:	7332422	Issue Dt:	02/19/2008	Application #:	11029881	Filing Dt:	01/05/2005
Publication #:	US20060148255	Pub Dt:	07/06/2006
Title:	METHOD FOR CUO REDUCTION BY USING TWO STEP NITROGEN OXYGEN AND REDUCING PLASMA TREATMENT

Patent #:	7297640	Issue Dt:	11/20/2007	Application #:	11034952	Filing Dt:	01/13/2005
Publication #:	US20060154491	Pub Dt:	07/13/2006
Title:	METHOD FOR REDUCING ARGON DIFFUSION FROM HIGH DENSITY PLASMA FILMS

Patent #:	7256112	Issue Dt:	08/14/2007	Application #:	11039429	Filing Dt:	01/20/2005
Publication #:	US20060160343	Pub Dt:	07/20/2006
Title:	LASER ACTIVATION OF IMPLANTED CONTACT PLUG FOR MEMORY BITLINE FABRICATION

Patent #:	7256084	Issue Dt:	08/14/2007	Application #:	11122667	Filing Dt:	05/04/2005
Publication #:	US20060252194	Pub Dt:	11/09/2006
Title:	COMPOSITE STRESS SPACER

Patent #:	7253097	Issue Dt:	08/07/2007	Application #:	11160624	Filing Dt:	06/30/2005
Publication #:	US20070001303	Pub Dt:	01/04/2007
Title:	INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS

Patent #:	7381646	Issue Dt:	06/03/2008	Application #:	11161722	Filing Dt:	08/15/2005
Publication #:	US20070037394	Pub Dt:	02/15/2007
Title:	A METHOD FOR USING A CU BEOL PROCESS TO FABRICATE AN INTEGRATED CIRCUIT (IC) ORIGINALLY HAVING AN AL DESIGN

Patent #:	7442618	Issue Dt:	10/28/2008	Application #:	11182682	Filing Dt:	07/16/2005
Publication #:	US20070020861	Pub Dt:	01/25/2007
Title:	METHOD TO ENGINEER ETCH PROFILES IN SI SUBSTRATE FOR ADVANCED SEMICONDUCTOR DEVICES

Patent #:	7524755	Issue Dt:	04/28/2009	Application #:	11358934	Filing Dt:	02/22/2006
Publication #:	US20070197023	Pub Dt:	08/23/2007
Title:	ENTIRE ENCAPSULATION OF CU INTERCONNECTS USING SELF-ALIGNED CUSIN FILM

Patent #:	7442619	Issue Dt:	10/28/2008	Application #:	11383965	Filing Dt:	05/18/2006
Publication #:	US20070267753	Pub Dt:	11/22/2007
Title:	METHOD OF FORMING SUBSTANTIALLY L-SHAPED SILICIDE CONTACT FOR A SEMICONDUCTOR DEVICE

Patent #:	7501683	Issue Dt:	03/10/2009	Application #:	11421047	Filing Dt:	05/30/2006
Publication #:	US20060220110	Pub Dt:	10/05/2006
Title:	INTEGRATED CIRCUIT WITH PROTECTED IMPLANTATION PROFILES AND METHOD FOR THE FORMATION THEREOF

Patent #:	7400018	Issue Dt:	07/15/2008	Application #:	11462846	Filing Dt:	08/07/2006
Publication #:	US20060270168	Pub Dt:	11/30/2006
Title:	END OF RANGE (EOR) SECONDARY DEFECT ENGINEERING USING CHEMICAL VAPOR DEPOSITION (CVD) SUBSTITUTIONAL CARBON DOPING

Patent #:	8105955	Issue Dt:	01/31/2012	Application #:	11464664	Filing Dt:	08/15/2006
Publication #:	US20080121926	Pub Dt:	05/29/2008
Title:	INTEGRATED CIRCUIT SYSTEM WITH CARBON AND NON-CARBON SILICON

Patent #:	8455350	Issue Dt:	06/04/2013	Application #:	11465793	Filing Dt:	08/18/2006
Publication #:	US20080042236	Pub Dt:	02/21/2008
Title:	INTEGRATED CIRCUIT SYSTEM EMPLOYING GATE SHIELD AND/OR GROUND SHIELD

Patent #:	7410874	Issue Dt:	08/12/2008	Application #:	11481213	Filing Dt:	07/05/2006
Publication #:	US20080124872	Pub Dt:	05/29/2008
Title:	METHOD OF INTEGRATING TRIPLE GATE OXIDE THICKNESS

Patent #:	8177993	Issue Dt:	05/15/2012	Application #:	11556696	Filing Dt:	11/05/2006
Publication #:	US20080105653	Pub Dt:	05/08/2008
Title:	APPARATUS AND METHODS FOR CLEANING AND DRYING OF WAFERS

Patent #:	8053327	Issue Dt:	11/08/2011	Application #:	11614961	Filing Dt:	12/21/2006
Publication #:	US20080150074	Pub Dt:	06/26/2008
Title:	METHOD OF MANUFACTURE OF AN INTEGRATED CIRCUIT SYSTEM WITH SELF-ALIGNED ISOLATION STRUCTURES

Patent #:	8394724	Issue Dt:	03/12/2013	Application #:	11843629	Filing Dt:	08/22/2007
Publication #:	US20080054477	Pub Dt:	03/06/2008
Title:	PROCESSING WITH REDUCED LINE END SHORTENING RATIO

Patent #:	8324011	Issue Dt:	12/04/2012	Application #:	11853156	Filing Dt:	09/11/2007
Publication #:	US20090068825	Pub Dt:	03/12/2009
Title:	IMPLEMENTATION OF TEMPERATURE-DEPENDENT PHASE SWITCH LAYER FOR IMPROVED TEMPERATURE UNIFORMITY DURING ANNEALING

Patent #:	8354347	Issue Dt:	01/15/2013	Application #:	11953881	Filing Dt:	12/11/2007
Publication #:	US20090146296	Pub Dt:	06/11/2009
Title:	METHOD OF FORMING HIGH-K DIELECTRIC STOP LAYER FOR CONTACT HOLE OPENING

Patent #:	8003311	Issue Dt:	08/23/2011	Application #:	11972809	Filing Dt:	01/11/2008
Publication #:	US20090181551	Pub Dt:	07/16/2009
Title:	INTEGRATED CIRCUIT SYSTEM EMPLOYING MULTIPLE EXPOSURE DUMMY PATTERNING TECHNOLOGY

Patent #:	8338245	Issue Dt:	12/25/2012	Application #:	12048994	Filing Dt:	03/14/2008
Publication #:	US20080173934	Pub Dt:	07/24/2008
Title:	INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED SPACERS

Patent #:	8274115	Issue Dt:	09/25/2012	Application #:	12050956	Filing Dt:	03/19/2008
Publication #:	US20090236663	Pub Dt:	09/24/2009
Title:	HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER

Patent #:	8013372	Issue Dt:	09/06/2011	Application #:	12062535	Filing Dt:	04/04/2008
Publication #:	US20090250764	Pub Dt:	10/08/2009
Title:	AN INTEGRATED CIRCUIT INCLUDING A STRESSED DIELECTRIC LAYER WITH STABLE STRESS

Patent #:	8178417	Issue Dt:	05/15/2012	Application #:	12107751	Filing Dt:	04/22/2008
Publication #:	US20090261448	Pub Dt:	10/22/2009
Title:	METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES FOR INTEGRATED CIRCUITS

Patent #:	8158513	Issue Dt:	04/17/2012	Application #:	12247479	Filing Dt:	10/08/2008
Publication #:	US20100087061	Pub Dt:	04/08/2010
Title:	INTEGRATED CIRCUIT SYSTEM EMPLOYING BACKSIDE ENERGY SOURCE FOR ELECTRICAL CONTACT FORMATION

Patent #:	8153527	Issue Dt:	04/10/2012	Application #:	12249970	Filing Dt:	10/13/2008
Publication #:	US20100091424	Pub Dt:	04/15/2010
Title:	METHOD FOR REDUCING SIDEWALL ETCH RESIDUE

Patent #:	8101487	Issue Dt:	01/24/2012	Application #:	12466391	Filing Dt:	05/15/2009
Publication #:	US20090286373	Pub Dt:	11/19/2009
Title:	METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH SHALLOW DIFFUSION REGIONS

Patent #:	8035201	Issue Dt:	10/11/2011	Application #:	12473232	Filing Dt:	05/27/2009
Publication #:	US20100301461	Pub Dt:	12/02/2010
Title:	RELIABLE INTERCONNECTION

Patent #:	8268733	Issue Dt:	09/18/2012	Application #:	12537268	Filing Dt:	08/07/2009
Publication #:	US20110034040	Pub Dt:	02/10/2011
Title:	LOCALIZED ANNEAL

Patent #:	9159565	Issue Dt:	10/13/2015	Application #:	12544747	Filing Dt:	08/20/2009
Publication #:	US20110042757	Pub Dt:	02/24/2011
Title:	INTEGRATED CIRCUIT SYSTEM WITH BAND TO BAND TUNNELING AND METHOD OF MANUFACTURE THEREOF

Patent #:	8446779	Issue Dt:	05/21/2013	Application #:	12583486	Filing Dt:	08/21/2009
Publication #:	US20110044115	Pub Dt:	02/24/2011
Title:	Non-volatile memory using pyramidal nanocrystals as electron storage elements

Patent #:	8470700	Issue Dt:	06/25/2013	Application #:	12804487	Filing Dt:	07/22/2010
Publication #:	US20120018815	Pub Dt:	01/26/2012
Title:	Semiconductor device with reduced contact resistance and method of manufacturing thereof

Patent #:	8405222	Issue Dt:	03/26/2013	Application #:	12825266	Filing Dt:	06/28/2010
Publication #:	US20110316166	Pub Dt:	12/29/2011
Title:	INTEGRATED CIRCUIT SYSTEM WITH VIA AND METHOD OF MANUFACTURE THEREOF

Patent #:	8114769	Issue Dt:	02/14/2012	Application #:	12982956	Filing Dt:	12/31/2010
Title:	METHODS AND STRUCTURES TO ENABLE SELF-ALIGNED VIA ETCH FOR CU DAMASCENE STRUCTURE USING TRENCH FIRST METAL HARD MASK (TFMHM) SCHEME

Patent #:	NONE	Issue Dt:		Application #:	13112317	Filing Dt:	05/20/2011
Publication #:	US20120292735	Pub Dt:	11/22/2012
Title:	CORNER TRANSISTOR SUPPRESSION

Patent #:	NONE	Issue Dt:		Application #:	13225483	Filing Dt:	09/05/2011
Publication #:	US20110316085	Pub Dt:	12/29/2011
Title:	INTEGRATED CIRCUIT INCLUDING A STRESSED DIELECTRIC LAYER WITH STABLE STRESS

Patent #:	8153537	Issue Dt:	04/10/2012	Application #:	13236627	Filing Dt:	09/19/2011
Publication #:	US20120070971	Pub Dt:	03/22/2012
Title:	METHOD FOR FABRICATING SEMICONDUCTOR DEVICES USING STRESS ENGINEERING

Patent #:	8637370	Issue Dt:	01/28/2014	Application #:	13354158	Filing Dt:	01/19/2012
Publication #:	US20130187224	Pub Dt:	07/25/2013
Title:	INTEGRATION OF TRENCH MOS WITH LOW VOLTAGE INTEGRATED CIRCUITS

Patent #:	NONE	Issue Dt:		Application #:	13443891	Filing Dt:	04/11/2012
Publication #:	US20120255586	Pub Dt:	10/11/2012
Title:	APPARATUS AND METHODS FOR CLEANING AND DRYING OF WAFERS

Patent #:	8824208	Issue Dt:	09/02/2014	Application #:	13891967	Filing Dt:	05/10/2013
Publication #:	US20130328118	Pub Dt:	12/12/2013
Title:	NON-VOLATILE MEMORY USING PYRAMIDAL NANOCRYSTALS AS ELECTRON STORAGE ELEMENTS

Patent #:	9411341	Issue Dt:	08/09/2016	Application #:	13900542	Filing Dt:	05/23/2013
Publication #:	US20130317640	Pub Dt:	11/28/2013
Title:	VACUUM PUMP CONTROLLER

Patent #:	8975708	Issue Dt:	03/10/2015	Application #:	13915221	Filing Dt:	06/11/2013
Publication #:	US20130270654	Pub Dt:	10/17/2013
Title:	SEMICONDUCTOR DEVICE WITH REDUCED CONTACT RESISTANCE AND METHOD OF MANUFACTURING THEREOF

Patent #:	9368386	Issue Dt:	06/14/2016	Application #:	13927588	Filing Dt:	06/26/2013
Publication #:	US20130288452	Pub Dt:	10/31/2013
Title:	CORNER TRANSISTOR SUPPRESSION

Patent #:	9129910	Issue Dt:	09/08/2015	Application #:	14032203	Filing Dt:	09/20/2013
Publication #:	US20150087132	Pub Dt:	03/26/2015
Title:	WAFER PROCESSING

Patent #:	9153473	Issue Dt:	10/06/2015	Application #:	14032206	Filing Dt:	09/20/2013
Publication #:	US20150087133	Pub Dt:	03/26/2015
Title:	WAFER PROCESSING

Patent #:	9293388	Issue Dt:	03/22/2016	Application #:	14060582	Filing Dt:	10/22/2013
Publication #:	US20150108654	Pub Dt:	04/23/2015
Title:	RELIABLE PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES

Patent #:	9209297	Issue Dt:	12/08/2015	Application #:	14083557	Filing Dt:	11/19/2013
Publication #:	US20140070310	Pub Dt:	03/13/2014
Title:	INTEGRATION OF TRENCH MOS WITH LOW VOLTAGE INTEGRATED CIRCUITS

Patent #:	9299798	Issue Dt:	03/29/2016	Application #:	14091291	Filing Dt:	11/26/2013
Publication #:	US20150145060	Pub Dt:	05/28/2015
Title:	SEMICONDUCTOR DEVICE AND METHODS FOR FORMING A SEMICONDUCTOR DEVICE

Patent #:	9620642	Issue Dt:	04/11/2017	Application #:	14103780	Filing Dt:	12/11/2013
Publication #:	US20150162436	Pub Dt:	06/11/2015
Title:	FINFET WITH ISOLATION

Patent #:	9305886	Issue Dt:	04/05/2016	Application #:	14132368	Filing Dt:	12/18/2013
Publication #:	US20150171025	Pub Dt:	06/18/2015
Title:	INTEGRATED CIRCUITS HAVING CRACK-STOP STRUCTURES AND METHODS FOR FABRICATING THE SAME

Patent #:	9252213	Issue Dt:	02/02/2016	Application #:	14134731	Filing Dt:	12/19/2013
Publication #:	US20150179734	Pub Dt:	06/25/2015
Title:	INTEGRATED CIRCUITS WITH A BURIED N LAYER AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS

Patent #:	9362171	Issue Dt:	06/07/2016	Application #:	14140553	Filing Dt:	12/26/2013
Publication #:	US20150187647	Pub Dt:	07/02/2015
Title:	THROUGH VIA CONTACTS WITH INSULATED SUBSTRATE

Patent #:	9240374	Issue Dt:	01/19/2016	Application #:	14142934	Filing Dt:	12/30/2013
Publication #:	US20150187700	Pub Dt:	07/02/2015
Title:	RELIABLE INTERCONNECTS

Patent #:	9202746	Issue Dt:	12/01/2015	Application #:	14145581	Filing Dt:	12/31/2013
Publication #:	US20150187641	Pub Dt:	07/02/2015
Title:	INTEGRATED CIRCUITS WITH IMPROVED GAP FILL DIELECTRIC AND METHODS FOR FABRICATING SAME

Patent #:	9287269	Issue Dt:	03/15/2016	Application #:	14173831	Filing Dt:	02/06/2014
Publication #:	US20150221652	Pub Dt:	08/06/2015
Title:	1T SRAM/DRAM

Patent #:	9349654	Issue Dt:	05/24/2016	Application #:	14228258	Filing Dt:	03/28/2014
Publication #:	US20150279743	Pub Dt:	10/01/2015
Title:	ISOLATION FOR EMBEDDED DEVICES

Patent #:	9257277	Issue Dt:	02/09/2016	Application #:	14253658	Filing Dt:	04/15/2014
Publication #:	US20150294858	Pub Dt:	10/15/2015
Title:	METHODS FOR EXTREME ULTRAVIOLET MASK DEFECT MITIGATION BY MULTI-PATTERNING

Patent #:	9640438	Issue Dt:	05/02/2017	Application #:	14585250	Filing Dt:	12/30/2014
Publication #:	US20160190012	Pub Dt:	06/30/2016
Title:	INTEGRATED CIRCUITS WITH INACTIVE GATES AND METHODS OF MANUFACTURING THE SAME

Patent #:	9406687	Issue Dt:	08/02/2016	Application #:	14664940	Filing Dt:	03/23/2015
Title:	INTEGRATION OF MEMORY DEVICES WITH DIFFERENT VOLTAGES

Patent #:	9543192	Issue Dt:	01/10/2017	Application #:	14715538	Filing Dt:	05/18/2015
Publication #:	US20160343610	Pub Dt:	11/24/2016
Title:	STITCHED DEVICES

Patent #:	9646934	Issue Dt:	05/09/2017	Application #:	14721121	Filing Dt:	05/26/2015
Publication #:	US20160351507	Pub Dt:	12/01/2016
Title:	INTEGRATED CIRCUITS WITH OVERLAY MARKS AND METHODS OF MANUFACTURING THE SAME

Patent #:	9614027	Issue Dt:	04/04/2017	Application #:	14840075	Filing Dt:	08/31/2015
Publication #:	US20170062554	Pub Dt:	03/02/2017
Title:	HIGH VOLTAGE TRANSISTOR WITH REDUCED ISOLATION BREAKDOWN

Patent #:	9673084	Issue Dt:	06/06/2017	Application #:	14958873	Filing Dt:	12/03/2015
Publication #:	US20160163583	Pub Dt:	06/09/2016
Title:	ISOLATION SCHEME FOR HIGH VOLTAGE DEVICE

Patent #:	9520299	Issue Dt:	12/13/2016	Application #:	14981881	Filing Dt:	12/28/2015
Publication #:	US20160189971	Pub Dt:	06/30/2016
Title:	ETCH BIAS CONTROL

Patent #:	9620373	Issue Dt:	04/11/2017	Application #:	14985800	Filing Dt:	12/31/2015
Title:	METHODS FOR FABRICATING SEMICONDUCTOR OR MICROMACHINED DEVICES WITH METAL STRUCTURES AND METHODS FOR FORMING SELF-ALIGNED DEEP CAVITY METAL STRUCTURES

Patent #:	9673111	Issue Dt:	06/06/2017	Application #:	15014211	Filing Dt:	02/03/2016
Publication #:	US20160148848	Pub Dt:	05/26/2016
Title:	METHODS FOR EXTREME ULTRAVIOLET MASK DEFECT MITIGATION BY MULTI-PATTERNING

Patent #:	NONE	Issue Dt:		Application #:	15055649	Filing Dt:	02/29/2016
Publication #:	US20160181197	Pub Dt:	06/23/2016
Title:	RELIABLE PASSIVATION LAYERS FOR SEMICONDUCTOR DEVICES

Patent #:	9679905	Issue Dt:	06/13/2017	Application #:	15094555	Filing Dt:	04/08/2016
Title:	INTEGRATED CIRCUITS WITH NON-VOLATILE MEMORY AND METHODS OF PRODUCING THE SAME

Patent #:	9905642	Issue Dt:	02/27/2018	Application #:	15138339	Filing Dt:	04/26/2016
Publication #:	US20160240611	Pub Dt:	08/18/2016
Title:	CORNER TRANSISTOR SUPPRESSION

Patent #:	10535645	Issue Dt:	01/14/2020	Application #:	15402166	Filing Dt:	01/09/2017
Publication #:	US20170125396	Pub Dt:	05/04/2017
Title:	STITCHED DEVICES

Assignor

GLOBALFOUNDRIES SINGAPORE PTE. LTD.

Exec Dt:

11/26/2018

Assignee

ALSEPHINA INNOVATIONS INC.

303 TERRY FOX DRIVE

SUITE 300

OTTAWA, CANADA K2K 3J1

Correspondence name and address
	ALSEPHINA INNOVATIONS INC.
	1891 ROBERSTON ROAD
	SUITE 100
	OTTAWA, K2H 5B7 CANADA

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