Patent Assignment Details
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| Reel/Frame: | 049840/0745 | |
| Pages: | 5 |
| | Recorded: | 07/23/2019 | | |
| Attorney Dkt #: | 10314.0067.02,-03,-05 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
3
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Patent #:
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Issue Dt:
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01/29/2013
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Application #:
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13446930
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Filing Dt:
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04/13/2012
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Publication #:
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Pub Dt:
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08/09/2012
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Title:
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EXECUTING MISALIGNED LOAD DEPENDENT INSTRUCTION IN SECOND EXECUTION STAGE IN PARITY PROTECTED MODE IN CONFIGURABLE PIPELINED PROCESSOR
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Patent #:
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Issue Dt:
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09/15/2015
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Application #:
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13750345
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Filing Dt:
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01/25/2013
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Publication #:
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Pub Dt:
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09/19/2013
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Title:
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Processor executing instructions in ALU in first / second pipeline stage during non-ECC / ECC mode
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Patent #:
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Issue Dt:
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11/05/2019
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Application #:
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16026733
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Filing Dt:
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07/03/2018
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Publication #:
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Pub Dt:
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02/28/2019
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Title:
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CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM
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Assignee
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| 6501 WILLIAM CANNON DRIVE WEST |
| AUSTIN, TEXAS 78735 |
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Correspondence name and address
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LEONIE SHAPIRO
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FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
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901 NEW YORK AVE. NW
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WASHINGTON, DC 20001
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