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Total properties:
33
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Patent #:
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Issue Dt:
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09/16/2003
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Application #:
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09467939
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Filing Dt:
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12/21/1999
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Title:
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ALTERNATE BOOTH PARTIAL PRODUCT GENERATION FOR A HARDWARE MULTIPLIER
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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09847849
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Filing Dt:
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04/30/2001
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Title:
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BRIDGE FOR COUPLING DIGITAL SIGNAL PROCESSOR TO ON-CHIP BUS AS MASTER
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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09847850
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Filing Dt:
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04/30/2001
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Title:
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BRIDGE FOR COUPLING DIGITAL SIGNAL PROCESSOR TO ON-CHIP BUS AS SLAVE
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Patent #:
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Issue Dt:
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11/08/2005
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Application #:
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09901455
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Filing Dt:
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07/09/2001
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Title:
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INCREASING DSP EFFICIENCY BY INDEPENDENT ISSUANCE OF STORE ADDRESS AND DATA
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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09924178
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Filing Dt:
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08/07/2001
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Title:
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INSTRUCTION FUSION FOR DIGITAL SIGNAL PROCESSOR
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Patent #:
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Issue Dt:
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11/01/2005
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Application #:
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09972404
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Filing Dt:
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10/05/2001
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Title:
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SYSTEM AND METHOD FOR EXTRACTING INSTRUCTION BOUNDARIES IN A FETCHED CACHELINE, GIVEN AN ARBITRARY OFFSET WITHIN THE CACHELINE
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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09975677
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Filing Dt:
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10/11/2001
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Title:
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INTEGRATED CIRCUIT CONTAINING MULTIPLE DIGITAL SIGNAL PROCESSORS
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Patent #:
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Issue Dt:
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07/31/2007
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Application #:
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09993114
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Filing Dt:
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11/05/2001
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Title:
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CONDITIONAL LINK POINTER REGISTER SETS MARKING THE BEGINNING AND END OF A CONDITIONAL INSTRUCTION BLOCK WHERE EACH SET CORRESPONDS TO A SINGLE STAGE OF A PIPELINE THAT MOVES LINK POINTERS THROUGH EACH CORRESPONDING REGISTER OF SAID REGISTER SETS AS INSTRUCTIONS MOVE THROUGH THE PIPELINE
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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09993431
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Filing Dt:
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11/05/2001
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Title:
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EFFICIENT MEMORY MANAGEMENT MECHANISM FOR DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION THEREOF
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Patent #:
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Issue Dt:
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03/14/2006
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Application #:
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10002817
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Filing Dt:
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11/02/2001
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Title:
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MECHANISM AND METHOD FOR REDUCING PIPELINE STALLS BETWEEN NESTED CALLS AND DIGITAL SIGNAL PROCESSOR INCORPORATING THE SAME
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Patent #:
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Issue Dt:
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06/12/2007
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Application #:
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10007498
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Filing Dt:
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11/13/2001
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Title:
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PIPELINED MULTIPLY-ACCUMULATE UNIT AND OUT-OF-ORDER COMPLETION LOGIC FOR A SUPERSCALAR DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION THEREOF
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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10007555
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Filing Dt:
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11/08/2001
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Title:
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MECHANISM FOR SUPPORTING SELF-MODIFYING CODE IN A HARVARD ARCHITECTURE DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION THEREOF
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10028898
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Filing Dt:
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12/20/2001
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Title:
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CHANGING INSTRUCTION ORDER BY REASSIGNING ONLY TAGS IN ORDER TAG FIELD IN INSTRUCTION QUEUE
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Patent #:
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Issue Dt:
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12/13/2005
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Application #:
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10047515
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Filing Dt:
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10/26/2001
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Title:
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PIPELINE STALL REDUCTION IN WIDE ISSUE PROCESSOR BY PROVIDING MISPREDICT PC QUEUE AND STAGING REGISTERS TO TRACK BRANCH INSTRUCTIONS IN PIPELINE
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Patent #:
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Issue Dt:
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09/12/2006
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Application #:
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10066147
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Filing Dt:
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10/26/2001
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Title:
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MECHANISM FOR RESOURCE ALLOCATION IN A DIGITAL SIGNAL PROCESSOR BASED ON INSTRUCTION TYPE INFORMATION AND FUNCTIONAL PRIORITY AND METHOD OF OPERATION THEREOF
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Patent #:
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Issue Dt:
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08/01/2006
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Application #:
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10066150
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Filing Dt:
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10/26/2001
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Title:
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EFFICIENT INSTRUCTION PREFETCH MECHANISM EMPLOYING SELECTIVE VALIDITY OF CACHED INSTRUCTIONS FOR DIGITAL SIGNAL PROCESSOR AND METHOD OF OPERATION THEREOF
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Patent #:
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Issue Dt:
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10/07/2008
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Application #:
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10231948
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Filing Dt:
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08/30/2002
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Title:
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SYSTEM AND METHOD FOR EXECUTING SOFTWARE PROGRAM INSTRUCTIONS USING A CONDITION SPECIFIED WITHIN A CONDITIONAL EXECUTION INSTRUCTION
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Patent #:
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Issue Dt:
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03/28/2006
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Application #:
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10256410
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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04/01/2004
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Title:
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MARKING QUEUE FOR SIMULTANEOUS EXECUTION OF INSTRUCTIONS IN CODE BLOCK SPECIFIED BY CONDITIONAL EXECUTION INSTRUCTION
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Patent #:
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Issue Dt:
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11/20/2007
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Application #:
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10256864
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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04/01/2004
| | | | |
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Title:
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SYSTEM AND METHOD FOR COOPERATIVE EXECUTION OF MULTIPLE BRANCHING INSTRUCTIONS IN A PROCESSOR
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Patent #:
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Issue Dt:
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09/05/2006
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Application #:
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10277339
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Filing Dt:
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10/22/2002
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Title:
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SYSTEM, CIRCUIT, AND METHOD FOR ADJUSTING THE PREFETCH INSTRUCTION RATE OF A PREFETCH UNIT
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Patent #:
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Issue Dt:
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11/22/2005
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Application #:
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10277341
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Filing Dt:
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10/22/2002
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Title:
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CIRCUIT AND METHOD FOR IMPROVING INSTRUCTION FETCH TIME FROM A CACHE MEMORY DEVICE
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Patent #:
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Issue Dt:
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04/15/2008
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Application #:
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10279344
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Filing Dt:
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10/24/2002
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Title:
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IN-CIRCUIT EMULATION DEBUGGER AND METHOD OF OPERATION THEREOF
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Patent #:
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Issue Dt:
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07/26/2005
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Application #:
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10310234
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Filing Dt:
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12/05/2002
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Publication #:
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Pub Dt:
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06/10/2004
| | | | |
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Title:
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DISTRIBUTED RESULT SYSTEM FOR HIGH-PERFORMANCE WIDE-ISSUE SUPERSCALAR PROCESSOR
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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10396265
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Filing Dt:
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03/25/2003
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Title:
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SYSTEM AND METHOD FOR EVALUATING AND EFFICIENTLY EXECUTING CONDITIONAL INSTRUCTIONS
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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10408387
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Filing Dt:
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04/07/2003
|
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Title:
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SYSTEM AND METHOD FOR REFERENCE-MODELING A PROCESSOR
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|
|
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Patent #:
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|
Issue Dt:
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04/11/2006
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Application #:
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10420581
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Filing Dt:
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04/22/2003
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Publication #:
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Pub Dt:
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10/28/2004
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Title:
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SYSTEM AND METHOD FOR ELECTRICAL POWER MANAGEMENT IN A DATA PROCESSING SYSTEM USING REGISTERS TO REFLECT CURRENT OPERATING CONDITIONS
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|
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Patent #:
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|
Issue Dt:
|
07/18/2006
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Application #:
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10437485
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Filing Dt:
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05/14/2003
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Publication #:
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Pub Dt:
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11/18/2004
| | | | |
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Title:
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SYSTEM AND METHOD FOR COOPERATIVE OPERATION OF A PROCESSOR AND COPROCESSOR
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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10603303
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Filing Dt:
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06/25/2003
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Publication #:
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Pub Dt:
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12/30/2004
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Title:
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DATA PROCESSING SYSTEMS INCLUDING HIGH PERFORMANCE BUSES AND INTERFACES, AND ASSOCIATED COMMUNICATION METHODS
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Patent #:
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Issue Dt:
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01/30/2007
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Application #:
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10613128
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Filing Dt:
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07/03/2003
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Publication #:
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Pub Dt:
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08/05/2004
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Title:
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PROCESSOR AND METHOD FOR CONVOLUTIONAL DECODING
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Patent #:
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Issue Dt:
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10/18/2005
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Application #:
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10701775
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Filing Dt:
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11/05/2003
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Title:
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ASYNCHRONOUS DATA STRUCTURE FOR STORING DATA GENERATED BY A DSP SYSTEM
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|
|
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Patent #:
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Issue Dt:
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09/18/2007
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Application #:
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10844941
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Filing Dt:
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05/13/2004
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Title:
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HARDWARE LOOPING MECHANISM AND METHOD FOR EFFICIENT EXECUTION OF DISCONTINUITY INSTRUCTIONS
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Patent #:
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Issue Dt:
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08/11/2009
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Application #:
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11083575
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Filing Dt:
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03/18/2005
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Title:
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DIGITAL SIGNAL PROCESSOR HAVING INVERSE DISCRETE COSINE TRANSFORM ENGINE FOR VIDEO DECODING AND PARTITIONED DISTRIBUTED ARITHMETIC MULTIPLY/ACCUMULATE UNIT THEREFOR
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Patent #:
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Issue Dt:
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08/26/2008
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Application #:
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11273679
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Filing Dt:
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11/14/2005
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Publication #:
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Pub Dt:
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05/11/2006
| | | | |
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Title:
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SIMULTANEOUSLY ASSIGNING CORRESPONDING ENTRY IN MULTIPLE QUEUES OF MULTI-STAGE ENTRIES FOR STORING CONDITION ATTRIBUTES FOR VALIDATING SIMULTANEOUSLY EXECUTED CONDITIONAL EXECUTION INSTRUCTION GROUPS
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