|
Total properties:
60
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/1997
|
Application #:
|
08323817
|
Filing Dt:
|
10/17/1994
|
|
Title:
|
METHOD FOR MOUNTING A MICROELECTRONIC CIRCUIT PERIPHERALLY-LEADED PACKAGE INCLUDING INTEGRAL SUPPORT MEMBER WITH SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/07/1997
|
Application #:
|
08323817
|
Filing Dt:
|
10/17/1994
|
|
Title:
|
METHOD FOR MOUNTING A MICROELECTRONIC CIRCUIT PERIPHERALLY-LEADED PACKAGE INCLUDING INTEGRAL SUPPORT MEMBER WITH SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1998
|
Application #:
|
08506382
|
Filing Dt:
|
07/24/1995
|
|
Title:
|
A METHOD OF PLANARIZING AN ARRAY OF PLASTICALLY DEFORMABLE ELECTRICAL CONTACTS ON AN INTEGRATED CIRCUIT PACKAGE TO COMPENSATE FOR BOTTOM SURFACE WARPAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1998
|
Application #:
|
08506382
|
Filing Dt:
|
07/24/1995
|
|
Title:
|
A METHOD OF PLANARIZING AN ARRAY OF PLASTICALLY DEFORMABLE ELECTRICAL CONTACTS ON AN INTEGRATED CIRCUIT PACKAGE TO COMPENSATE FOR BOTTOM SURFACE WARPAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/1997
|
Application #:
|
08595022
|
Filing Dt:
|
01/31/1996
|
|
Title:
|
MICROELECTRONIC INTEGRATED CIRCUIT MOUNTED ON CIRCUIT BOARD WITH SOLDER COLUMN GRID ARRAY INTERCONNECTION, AND METHOD OF FABRICATING THE SOLDER COLUMN GRID ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/1997
|
Application #:
|
08595022
|
Filing Dt:
|
01/31/1996
|
|
Title:
|
MICROELECTRONIC INTEGRATED CIRCUIT MOUNTED ON CIRCUIT BOARD WITH SOLDER COLUMN GRID ARRAY INTERCONNECTION, AND METHOD OF FABRICATING THE SOLDER COLUMN GRID ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/1997
|
Application #:
|
08655599
|
Filing Dt:
|
05/30/1996
|
|
Title:
|
APPARATUS TO DECOUPLE CORE CIRCUITS POWER SUPPLY FROM INPUT-OUTPUT CIRCUITS POWER SUPPLY IN A SEMICONDUCTOR DEVICE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/1997
|
Application #:
|
08655599
|
Filing Dt:
|
05/30/1996
|
|
Title:
|
APPARATUS TO DECOUPLE CORE CIRCUITS POWER SUPPLY FROM INPUT-OUTPUT CIRCUITS POWER SUPPLY IN A SEMICONDUCTOR DEVICE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08724076
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
BALL GRID ARRAY PACKAGE WITH INEXPENSIVE THREADED SECURE LOCKING MECHANISM TO ALLOW REMOVAL OF A THREADED HEAT SINK THEREFROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08724076
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
BALL GRID ARRAY PACKAGE WITH INEXPENSIVE THREADED SECURE LOCKING MECHANISM TO ALLOW REMOVAL OF A THREADED HEAT SINK THEREFROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08901489
|
Filing Dt:
|
07/28/1997
|
|
Title:
|
BALL GRID ARRAY WITH INEXPENSIVE THREADED SECURE LOCKING MECHANISM TO ALLOW REMOVAL OF A THREADED HEAT SINK THEREFROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08901489
|
Filing Dt:
|
07/28/1997
|
|
Title:
|
BALL GRID ARRAY WITH INEXPENSIVE THREADED SECURE LOCKING MECHANISM TO ALLOW REMOVAL OF A THREADED HEAT SINK THEREFROM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08938619
|
Filing Dt:
|
09/25/1997
|
|
Title:
|
SYSTEM AND METHOD FOR EMPIRICALLY DETERMINING SHRINKAGE STRESSES IN A MOLDED PACKAGE AND POWER MODULE EMPLOYING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08938619
|
Filing Dt:
|
09/25/1997
|
|
Title:
|
SYSTEM AND METHOD FOR EMPIRICALLY DETERMINING SHRINKAGE STRESSES IN A MOLDED PACKAGE AND POWER MODULE EMPLOYING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08955929
|
Filing Dt:
|
10/22/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE AND FABRICATION METHOD WHICH ADVANTAGEOUSLY COMBINE WIRE BONDING AND TAB TECHNIQUES TO INCREASE INTEGRATED CIRCUIT I/O PAD DENSITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08955929
|
Filing Dt:
|
10/22/1997
|
|
Title:
|
SEMICONDUCTOR DEVICE AND FABRICATION METHOD WHICH ADVANTAGEOUSLY COMBINE WIRE BONDING AND TAB TECHNIQUES TO INCREASE INTEGRATED CIRCUIT I/O PAD DENSITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
08975025
|
Filing Dt:
|
11/20/1997
|
|
Title:
|
REMOVAL OF A HEAT SPREADER FROM AN INTEGRATED CIRCUIT PACKAGE TO PERMIT TESTING OF THE INTEGRATED CIRCUIT AND OTHER ELEMENTS OF THE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
08975025
|
Filing Dt:
|
11/20/1997
|
|
Title:
|
REMOVAL OF A HEAT SPREADER FROM AN INTEGRATED CIRCUIT PACKAGE TO PERMIT TESTING OF THE INTEGRATED CIRCUIT AND OTHER ELEMENTS OF THE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
09006356
|
Filing Dt:
|
01/13/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE PACKAGE INCLUDING A SUBSTRATE HAVING BONDING FINGERS WITHIN AN ELECTRICALLY CONDUCTIVE RING SURROUNDING A DIE AREA AND A COMBINED POWER AND GROUND PLANE TO STABILIZE SIGNAL PATH IMPEDANCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2000
|
Application #:
|
09006356
|
Filing Dt:
|
01/13/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE PACKAGE INCLUDING A SUBSTRATE HAVING BONDING FINGERS WITHIN AN ELECTRICALLY CONDUCTIVE RING SURROUNDING A DIE AREA AND A COMBINED POWER AND GROUND PLANE TO STABILIZE SIGNAL PATH IMPEDANCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
09022733
|
Filing Dt:
|
02/12/1998
|
|
Title:
|
DEVICE AND METHOD OF MANUFACTURE FOR AN INTEGRATED CIRCUIT HAVING A BIST CIRCUIT AND BOND PADS INCORPORATED THEREIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
09022733
|
Filing Dt:
|
02/12/1998
|
|
Title:
|
DEVICE AND METHOD OF MANUFACTURE FOR AN INTEGRATED CIRCUIT HAVING A BIST CIRCUIT AND BOND PADS INCORPORATED THEREIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09072248
|
Filing Dt:
|
05/04/1998
|
|
Title:
|
LOW THERMAL EXPANSION COMPOSITE COMPRISING BODIES OF NEGATIVE CTE MATERIAL DISPOSED WITHIN A POSITIVE CTE MATRIX
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
|
Application #:
|
09072248
|
Filing Dt:
|
05/04/1998
|
|
Title:
|
LOW THERMAL EXPANSION COMPOSITE COMPRISING BODIES OF NEGATIVE CTE MATERIAL DISPOSED WITHIN A POSITIVE CTE MATRIX
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
09114345
|
Filing Dt:
|
07/13/1998
|
|
Title:
|
IMPROVED ENHANCED LAMINATION PROCESS BETWEEN HEATSPREADER TO PRESSURE SENSITIVE ADHESIVE (PSA) INTERFACE AS A STEP IN THE SEMICONDUCTOR ASSEMBLY PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
09114345
|
Filing Dt:
|
07/13/1998
|
|
Title:
|
IMPROVED ENHANCED LAMINATION PROCESS BETWEEN HEATSPREADER TO PRESSURE SENSITIVE ADHESIVE (PSA) INTERFACE AS A STEP IN THE SEMICONDUCTOR ASSEMBLY PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09122335
|
Filing Dt:
|
07/24/1998
|
|
Title:
|
LASER MARKING OF SEMICONDUCTOR WAFER SUBSTRATE WHILE INHIBITING ADHERENCE TO SUBSTRATE SURFACE OF PARTICLES GENERATED DURING LASER MARKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2000
|
Application #:
|
09122335
|
Filing Dt:
|
07/24/1998
|
|
Title:
|
LASER MARKING OF SEMICONDUCTOR WAFER SUBSTRATE WHILE INHIBITING ADHERENCE TO SUBSTRATE SURFACE OF PARTICLES GENERATED DURING LASER MARKING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
09127707
|
Filing Dt:
|
07/31/1998
|
|
Title:
|
SYSTEM AND METHOD FOR EMPIRICALLY DETERMINING SHRINKAGE STRESSES IN A MOLDED PACKAGE AND POWER MODULE EMPLOYING THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1999
|
Application #:
|
09127707
|
Filing Dt:
|
07/31/1998
|
|
Title:
|
SYSTEM AND METHOD FOR EMPIRICALLY DETERMINING SHRINKAGE STRESSES IN A MOLDED PACKAGE AND POWER MODULE EMPLOYING THE SAME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09351945
|
Filing Dt:
|
07/12/1999
|
|
Title:
|
ENCAPSULATED CIRCUIT USING VENTED MOLD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09351945
|
Filing Dt:
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07/12/1999
|
|
Title:
|
ENCAPSULATED CIRCUIT USING VENTED MOLD
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|
|
|
|
Patent #:
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Issue Dt:
|
01/04/2005
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Application #:
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09465089
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Filing Dt:
|
12/16/1999
|
|
Title:
|
DUAL DAMASCENE BOND PAD STRUCTURE FOR LOWERING STRESS AND ALLOWING CIRCUITRY UNDER PADS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2005
|
Application #:
|
09465089
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Filing Dt:
|
12/16/1999
|
|
Title:
|
DUAL DAMASCENE BOND PAD STRUCTURE FOR LOWERING STRESS AND ALLOWING CIRCUITRY UNDER PADS
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|
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|
Patent #:
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Issue Dt:
|
06/26/2001
|
Application #:
|
09480014
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Filing Dt:
|
01/10/2000
|
|
Title:
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ELECTRICAL CONTACT AND HOUSING FOR USE AS AN INTERFACE BETWEEN A TESTING FIXTURE AND A DEVICE UNDER TEST
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|
|
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Patent #:
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|
Issue Dt:
|
06/26/2001
|
Application #:
|
09480014
|
Filing Dt:
|
01/10/2000
|
|
Title:
|
ELECTRICAL CONTACT AND HOUSING FOR USE AS AN INTERFACE BETWEEN A TESTING FIXTURE AND A DEVICE UNDER TEST
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|
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|
Patent #:
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|
Issue Dt:
|
03/02/2004
|
Application #:
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09957410
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Filing Dt:
|
09/20/2001
|
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Title:
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METHOD FOR RELIABILITY TESTING LEAKAGE CHARACTERISTICS IN AN ELECTRONIC CIRCUIT AND A TESTING DEVICE FOR ACCOMPLISHING THE SAME
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Patent #:
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|
Issue Dt:
|
03/02/2004
|
Application #:
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09957410
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Filing Dt:
|
09/20/2001
|
|
Title:
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METHOD FOR RELIABILITY TESTING LEAKAGE CHARACTERISTICS IN AN ELECTRONIC CIRCUIT AND A TESTING DEVICE FOR ACCOMPLISHING THE SAME
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|
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|
Patent #:
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Issue Dt:
|
12/14/2004
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Application #:
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10173182
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Filing Dt:
|
06/17/2002
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|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
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FLIP CHIP SEMICONDUSTOR DEVICE AND METHOD OF MAKING THE SAME
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|
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Patent #:
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|
Issue Dt:
|
12/14/2004
|
Application #:
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10173182
|
Filing Dt:
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06/17/2002
|
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Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
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FLIP CHIP SEMICONDUSTOR DEVICE AND METHOD OF MAKING THE SAME
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Patent #:
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Issue Dt:
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03/24/2009
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Application #:
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11078052
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Filing Dt:
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03/11/2005
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|
Publication #:
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Pub Dt:
|
09/14/2006
| | | | |
|
Title:
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PACKAGE CONFIGURATION AND MANUFACTURING METHOD ENABLING THE ADDITION OF DECOUPLING CAPACITORS TO STANDARD PACKAGE DESIGNS
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Patent #:
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Issue Dt:
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03/24/2009
|
Application #:
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11078052
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Filing Dt:
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03/11/2005
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Publication #:
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Pub Dt:
|
09/14/2006
| | | | |
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Title:
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PACKAGE CONFIGURATION AND MANUFACTURING METHOD ENABLING THE ADDITION OF DECOUPLING CAPACITORS TO STANDARD PACKAGE DESIGNS
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Patent #:
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Issue Dt:
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02/20/2007
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Application #:
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11276938
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Filing Dt:
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03/17/2006
|
|
Title:
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DEVICE FOR MINIMIZING DIFFERENTIAL PAIR LENGTH MISMATCH AND IMPEDANCE DISCONTINUITIES IN AN INTEGRATED CIRCUIT PACKAGE DESIGN
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Patent #:
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Issue Dt:
|
02/20/2007
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Application #:
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11276938
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Filing Dt:
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03/17/2006
|
|
Title:
|
DEVICE FOR MINIMIZING DIFFERENTIAL PAIR LENGTH MISMATCH AND IMPEDANCE DISCONTINUITIES IN AN INTEGRATED CIRCUIT PACKAGE DESIGN
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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11283044
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Filing Dt:
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11/18/2005
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Title:
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REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES BY DOPING ALUMINUM USED IN BOND PADS DURING CU/LOW-K BEOL PROCESSING
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Patent #:
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Issue Dt:
|
04/17/2007
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Application #:
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11283044
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Filing Dt:
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11/18/2005
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Title:
|
REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES BY DOPING ALUMINUM USED IN BOND PADS DURING CU/LOW-K BEOL PROCESSING
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Patent #:
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Issue Dt:
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10/08/2013
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Application #:
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11283219
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Filing Dt:
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11/18/2005
|
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Publication #:
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Pub Dt:
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05/24/2007
| | | | |
|
Title:
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ALTERNATE PAD STRUCTURES/PASSIVATION INEGRATION SCHEMES TO REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES DURING CU/LOW-K BEOL PROCESSING
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Patent #:
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Issue Dt:
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10/08/2013
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Application #:
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11283219
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Filing Dt:
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11/18/2005
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Publication #:
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Pub Dt:
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05/24/2007
| | | | |
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Title:
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ALTERNATE PAD STRUCTURES/PASSIVATION INEGRATION SCHEMES TO REDUCE OR ELIMINATE IMC CRACKING IN POST WIRE BONDED DIES DURING CU/LOW-K BEOL PROCESSING
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11290087
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Filing Dt:
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11/30/2005
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Publication #:
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Pub Dt:
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05/31/2007
| | | | |
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Title:
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ELIMINATE IMC CRACKING IN POST WIREBONDED DIES: MACRO LEVEL STRESS REDUCTION BY MODIFYING DIELECTRIC/METAL FILM STACK IN BE LAYERS DURING CU/LOW-K PROCESSING
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11290087
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Filing Dt:
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11/30/2005
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Publication #:
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Pub Dt:
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05/31/2007
| | | | |
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Title:
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ELIMINATE IMC CRACKING IN POST WIREBONDED DIES: MACRO LEVEL STRESS REDUCTION BY MODIFYING DIELECTRIC/METAL FILM STACK IN BE LAYERS DURING CU/LOW-K PROCESSING
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Patent #:
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Issue Dt:
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12/10/2013
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Application #:
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11379256
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Filing Dt:
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04/19/2006
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Publication #:
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Pub Dt:
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08/10/2006
| | | | |
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Title:
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METHOD FOR ELECTRICAL INTERCONNECTION BETWEEN PRINTED WIRING BOARD LAYERS USING THROUGH HOLES WITH SOLID CORE CONDUCTIVE MATERIAL
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Patent #:
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Issue Dt:
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12/10/2013
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Application #:
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11379256
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Filing Dt:
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04/19/2006
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Publication #:
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Pub Dt:
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08/10/2006
| | | | |
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Title:
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METHOD FOR ELECTRICAL INTERCONNECTION BETWEEN PRINTED WIRING BOARD LAYERS USING THROUGH HOLES WITH SOLID CORE CONDUCTIVE MATERIAL
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Patent #:
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Issue Dt:
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10/19/2010
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Application #:
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11403492
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Filing Dt:
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04/13/2006
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Publication #:
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Pub Dt:
|
09/21/2006
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR IMPROVING THERMAL ENERGY DISSIPATION IN A DIRECT-CHIP-ATTACH COUPLING CONFIGURATION OF AN INTEGRATED CIRCUIT AND A CIRCUIT BOARD
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Patent #:
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Issue Dt:
|
10/19/2010
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Application #:
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11403492
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Filing Dt:
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04/13/2006
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Publication #:
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Pub Dt:
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09/21/2006
| | | | |
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Title:
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METHOD AND APPARATUS FOR IMPROVING THERMAL ENERGY DISSIPATION IN A DIRECT-CHIP-ATTACH COUPLING CONFIGURATION OF AN INTEGRATED CIRCUIT AND A CIRCUIT BOARD
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Patent #:
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Issue Dt:
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07/19/2011
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Application #:
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11562537
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Filing Dt:
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11/22/2006
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Publication #:
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Pub Dt:
|
05/22/2008
| | | | |
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Title:
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INTEGRATED CIRCUIT CHIP ASSEMBLY HAVING ARRAY OF THERMALLY CONDUCTIVE FEATURES ARRANGED IN APERTURE OF CIRCUIT SUBSTRATE
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Patent #:
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Issue Dt:
|
07/19/2011
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Application #:
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11562537
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Filing Dt:
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11/22/2006
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Publication #:
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Pub Dt:
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05/22/2008
| | | | |
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Title:
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INTEGRATED CIRCUIT CHIP ASSEMBLY HAVING ARRAY OF THERMALLY CONDUCTIVE FEATURES ARRANGED IN APERTURE OF CIRCUIT SUBSTRATE
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Patent #:
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Issue Dt:
|
11/09/2010
|
Application #:
|
12174479
|
Filing Dt:
|
07/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
|
Title:
|
PACKAGE CONFIGURATION AND MANUFACTURING METHOD ENABLING THE ADDITION OF DECOUPLING CAPACITORS TO STANDARD PACKAGE DESIGNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
12174479
|
Filing Dt:
|
07/16/2008
|
|
Publication #:
|
|
Pub Dt:
|
11/06/2008
| | | | |
|
Title:
|
PACKAGE CONFIGURATION AND MANUFACTURING METHOD ENABLING THE ADDITION OF DECOUPLING CAPACITORS TO STANDARD PACKAGE DESIGNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12526334
|
Filing Dt:
|
08/07/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/17/2010
| | | | |
|
Title:
|
QUAD FLAT NO LEAD (QFN) INTEGRATED CIRCUIT (IC) PACKAGE HAVING A MODIFIED PADDLE AND METHOD FOR DESIGNING THE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2012
|
Application #:
|
12526334
|
Filing Dt:
|
08/07/2009
|
|
Publication #:
|
|
Pub Dt:
|
06/17/2010
| | | | |
|
Title:
|
QUAD FLAT NO LEAD (QFN) INTEGRATED CIRCUIT (IC) PACKAGE HAVING A MODIFIED PADDLE AND METHOD FOR DESIGNING THE PACKAGE
|
|
