Total properties:
342
Page
1
of
4
Pages:
1 2 3 4
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14835687
|
Filing Dt:
|
08/25/2015
|
|
Publication #:
|
|
Pub Dt:
|
03/02/2017
| | | | |
|
Title:
|
METHOD FOR MANUFACTURING A WAFER LEVEL PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2019
|
Application #:
|
15172022
|
Filing Dt:
|
06/02/2016
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2016
| | | | |
|
Title:
|
ADVANCED MEMORY INTERFACES AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2019
|
Application #:
|
15396817
|
Filing Dt:
|
01/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2018
| | | | |
|
Title:
|
SEMICONDUCTOR PACKAGE WITH EMBEDDED MIM CAPACITOR, AND METHOD OF FABRICATING THEREOF
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15396828
|
Filing Dt:
|
01/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/05/2018
| | | | |
|
Title:
|
MIM CAPACITOR WITH ENHANCED CAPACITANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/13/2019
|
Application #:
|
15428124
|
Filing Dt:
|
02/08/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/09/2018
| | | | |
|
Title:
|
SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2019
|
Application #:
|
15569854
|
Filing Dt:
|
10/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/28/2019
| | | | |
|
Title:
|
METHODS OF PROGRAMMING DIFFERENT PORTIONS OF MEMORY CELLS OF A STRING OF SERIES-CONNECTED MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2019
|
Application #:
|
15583883
|
Filing Dt:
|
05/01/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/10/2017
| | | | |
|
Title:
|
SYSTEMS AND METHODS TO SELECTIVELY CONNECT ANTENNAS TO RECEIVE AND BACKSCATTER RADIO FREQUENCY SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2021
|
Application #:
|
15596649
|
Filing Dt:
|
05/16/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/31/2017
| | | | |
|
Title:
|
MICROPROCESSOR ARCHITECTURE HAVING ALTERNATIVE MEMORY ACCESS PATHS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15670961
|
Filing Dt:
|
08/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/25/2018
| | | | |
|
Title:
|
SOFTWARE DISTRIBUTION METHOD AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2019
|
Application #:
|
15714818
|
Filing Dt:
|
09/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/28/2019
| | | | |
|
Title:
|
MEMORY DECISION FEEDBACK EQUALIZER TESTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2019
|
Application #:
|
15720960
|
Filing Dt:
|
09/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/03/2018
| | | | |
|
Title:
|
APPARATUSES AND METHODS INVOLVING ACCESSING DISTRIBUTED SUB-BLOCKS OF MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2019
|
Application #:
|
15721985
|
Filing Dt:
|
10/02/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2018
| | | | |
|
Title:
|
ANALOG ASSISTED DIGITAL SWITCH REGULATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/2019
|
Application #:
|
15721994
|
Filing Dt:
|
10/02/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2018
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR PROVIDING REDUNDANCY IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2019
|
Application #:
|
15722054
|
Filing Dt:
|
10/02/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2018
| | | | |
|
Title:
|
SEQUENTIAL MEMORY ACCESS OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2018
|
Application #:
|
15722063
|
Filing Dt:
|
10/02/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2018
| | | | |
|
Title:
|
MEMORY DEVICES FOR READING MEMORY CELLS OF DIFFERENT MEMORY PLANES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2018
|
Application #:
|
15722580
|
Filing Dt:
|
10/02/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2018
| | | | |
|
Title:
|
THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2020
|
Application #:
|
15722624
|
Filing Dt:
|
10/02/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/25/2018
| | | | |
|
Title:
|
AUTONOMOUS MEMORY ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2018
|
Application #:
|
15789167
|
Filing Dt:
|
10/20/2017
|
|
Title:
|
SYSTEMS AND METHODS FOR THRESHOLD VOLTAGE MODIFICATION AND DETECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2020
|
Application #:
|
15790690
|
Filing Dt:
|
10/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
VIRTUAL PARTITION MANAGEMENT IN A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2019
|
Application #:
|
15790794
|
Filing Dt:
|
10/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
HOST ACCELERATED OPERATIONS IN MANAGED NAND DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2019
|
Application #:
|
15790882
|
Filing Dt:
|
10/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
Namespaces Allocation in Non-Volatile Memory Devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/2020
|
Application #:
|
15790896
|
Filing Dt:
|
10/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
ON-DIE TERMINATION ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2020
|
Application #:
|
15790969
|
Filing Dt:
|
10/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
Namespace Size Adjustment in Non-Volatile Memory Devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2019
|
Application #:
|
15790979
|
Filing Dt:
|
10/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
Namespace Management in Non-Volatile Memory Devices
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2018
|
Application #:
|
15791271
|
Filing Dt:
|
10/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2018
| | | | |
|
Title:
|
Memory Sense Amplifiers and Memory Verification Methods
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2019
|
Application #:
|
15791886
|
Filing Dt:
|
10/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
COMMAND SELECTION POLICY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2020
|
Application #:
|
15792473
|
Filing Dt:
|
10/24/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/25/2019
| | | | |
|
Title:
|
DEVICES AND METHODS TO WRITE BACKGROUND DATA PATTERNS IN MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/15/2020
|
Application #:
|
15792842
|
Filing Dt:
|
10/25/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2018
| | | | |
|
Title:
|
MEMORY CELL WITH INDEPENDENTLY-SIZED ELECTRODE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/17/2019
|
Application #:
|
15794563
|
Filing Dt:
|
10/26/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2018
| | | | |
|
Title:
|
SYSTEMS, DEVICES, AND METHODS FOR SELECTIVE COMMUNICATION THROUGH AN ELECTRICAL CONNECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
15794724
|
Filing Dt:
|
10/26/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2018
| | | | |
|
Title:
|
APPARATUSES INCLUDING MULTIPLE READ MODES AND METHODS FOR SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2020
|
Application #:
|
15795488
|
Filing Dt:
|
10/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
|
Title:
|
OXIDE BASED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/2021
|
Application #:
|
15795690
|
Filing Dt:
|
10/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
ASSEMBLIES INCLUDING HEAT DISPERSING ELEMENTS AND RELATED SYSTEMS AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/21/2020
|
Application #:
|
15796173
|
Filing Dt:
|
10/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
02/15/2018
| | | | |
|
Title:
|
CONNECTION VERIFICATION TECHNIQUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/01/2019
|
Application #:
|
15796340
|
Filing Dt:
|
10/27/2017
|
|
Title:
|
APPARATUS AND METHODS FOR REFRESHING MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2019
|
Application #:
|
15796611
|
Filing Dt:
|
10/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
10/25/2018
| | | | |
|
Title:
|
MEMORY CELLS AND MEMORY ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2018
|
Application #:
|
15797029
|
Filing Dt:
|
10/30/2017
|
|
Title:
|
Backside Stealth Dicing Through Tape Followed by Front Side Laser Ablation Dicing Process
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15797462
|
Filing Dt:
|
10/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/02/2018
| | | | |
|
Title:
|
INTEGRATED MEMORY ASSEMBLIES COMPRISING MULTIPLE MEMORY ARRAY DECKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2019
|
Application #:
|
15797638
|
Filing Dt:
|
10/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
3DI Solder Cup
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2019
|
Application #:
|
15797759
|
Filing Dt:
|
10/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
04/26/2018
| | | | |
|
Title:
|
APPARATUSES AND METHODS TO SELECTIVELY PERFORM LOGICAL OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2019
|
Application #:
|
15797812
|
Filing Dt:
|
10/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
DYNAMIC L2P CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2019
|
Application #:
|
15797900
|
Filing Dt:
|
10/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
Method for 3D Ink Jet TCB Interconnect Control
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2019
|
Application #:
|
15798083
|
Filing Dt:
|
10/30/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPERATING THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/11/2020
|
Application #:
|
15798672
|
Filing Dt:
|
10/31/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2018
| | | | |
|
Title:
|
METHODS OF FORMING NANOSTRUCTURES USING SELF-ASSEMBLED NUCLEIC ACIDS, AND NANOSTRUCTURES THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/2021
|
Application #:
|
15799508
|
Filing Dt:
|
10/31/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
COMMON POOL MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2019
|
Application #:
|
15799577
|
Filing Dt:
|
10/31/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
END OF LIFE PERFORMANCE THROTTLING TO PREVENT DATA LOSS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/2019
|
Application #:
|
15799616
|
Filing Dt:
|
10/31/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
Block Read Count Voltage Adjustment
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2020
|
Application #:
|
15799655
|
Filing Dt:
|
10/31/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
SLC PAGE READ
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/27/2018
|
Application #:
|
15800267
|
Filing Dt:
|
11/01/2017
|
|
Title:
|
SYSTEMS AND METHODS FOR MAINTAINING REFRESH OPERATIONS OF MEMORY BANKS USING A SHARED ADDRESS PATH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2019
|
Application #:
|
15800958
|
Filing Dt:
|
11/01/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
NAND FLASH THERMAL ALERTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
15801148
|
Filing Dt:
|
11/01/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2018
| | | | |
|
Title:
|
UNINTERRUPTED READ OF CONSECUTIVE PAGES FOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/08/2021
|
Application #:
|
15802016
|
Filing Dt:
|
11/02/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/02/2019
| | | | |
|
Title:
|
PERIPHERAL LOGIC CIRCUITS UNDER DRAM MEMORY ARRAYS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2019
|
Application #:
|
15802521
|
Filing Dt:
|
11/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
|
Title:
|
SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2021
|
Application #:
|
15802551
|
Filing Dt:
|
11/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
|
Title:
|
CONFIGURABLE TRIM SETTINGS ON A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/14/2020
|
Application #:
|
15802597
|
Filing Dt:
|
11/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
|
Title:
|
TRIM SETTING DETERMINATION FOR A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/18/2019
|
Application #:
|
15802652
|
Filing Dt:
|
11/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
|
Title:
|
TRIM SETTING DETERMINATION ON A MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/2019
|
Application #:
|
15803313
|
Filing Dt:
|
11/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2018
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2018
|
Application #:
|
15803690
|
Filing Dt:
|
11/03/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2018
| | | | |
|
Title:
|
ANTI-ECLIPSE CIRCUITRY WITH TRACKING OF FLOATING DIFFUSION RESET LEVEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2018
|
Application #:
|
15804981
|
Filing Dt:
|
11/06/2017
|
|
Title:
|
Memory Arrays
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/27/2020
|
Application #:
|
15806073
|
Filing Dt:
|
11/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2018
| | | | |
|
Title:
|
Methods and Devices for Saving and/or Restoring a State of a Pattern-Recognition Processor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2019
|
Application #:
|
15806123
|
Filing Dt:
|
11/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR COMPUTE COMPONENTS FORMED OVER AN ARRAY OF MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2018
|
Application #:
|
15806217
|
Filing Dt:
|
11/07/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/01/2018
| | | | |
|
Title:
|
MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2019
|
Application #:
|
15806808
|
Filing Dt:
|
11/08/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE SHINGLED STACKS OF SEMICONDUCTOR DIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/23/2020
|
Application #:
|
15808508
|
Filing Dt:
|
11/09/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
|
Title:
|
TRACKING AND CORRECTION OF TIMING SIGNALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2019
|
Application #:
|
15808567
|
Filing Dt:
|
11/09/2017
|
|
Title:
|
UFS BASED IDLE TIME GARBAGE COLLECTION MANAGEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2020
|
Application #:
|
15808727
|
Filing Dt:
|
11/09/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/10/2018
| | | | |
|
Title:
|
Transistors and Memory Arrays
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2019
|
Application #:
|
15808771
|
Filing Dt:
|
11/09/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2019
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR REPAIRING MEMORY DEVICES INCLUDING A PLURALITY OF MEMORY DIE AND AN INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/2020
|
Application #:
|
15809710
|
Filing Dt:
|
11/10/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/28/2018
| | | | |
|
Title:
|
MEMORY ARRAYS COMPRISING FERROELECTRIC CAPACITORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2018
|
Application #:
|
15810430
|
Filing Dt:
|
11/13/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
|
Title:
|
INVERT OPERATIONS USING SENSING CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2019
|
Application #:
|
15810880
|
Filing Dt:
|
11/13/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
|
Title:
|
COMPUTING REDUCTION AND PREFIX SUM OPERATIONS IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2020
|
Application #:
|
15811359
|
Filing Dt:
|
11/13/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
|
Title:
|
CAPACITOR HAVING BOTTOM ELECTRODE COMPRISING TiN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2018
|
Application #:
|
15811572
|
Filing Dt:
|
11/13/2017
|
|
Title:
|
SEMICONDUCTOR DEVICES WITH PACKAGE-LEVEL CONFIGURABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2019
|
Application #:
|
15811579
|
Filing Dt:
|
11/13/2017
|
|
Title:
|
SEMICONDUCTOR DEVICES WITH POST-PROBE CONFIGURABILITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2019
|
Application #:
|
15812274
|
Filing Dt:
|
11/14/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
|
Title:
|
CELL CONTACT
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15812932
|
Filing Dt:
|
11/14/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/08/2018
| | | | |
|
Title:
|
MEMORY WEAR LEVELING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2020
|
Application #:
|
15812949
|
Filing Dt:
|
11/14/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR PERFORMING A WRITE PATTERN IN MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/05/2019
|
Application #:
|
15814634
|
Filing Dt:
|
11/16/2017
|
|
Title:
|
NAMESPACE CHANGE PROPAGATION IN NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/2023
|
Application #:
|
15814679
|
Filing Dt:
|
11/16/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
|
Title:
|
NAMESPACE ENCRYPTION IN NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2021
|
Application #:
|
15814785
|
Filing Dt:
|
11/16/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
|
Title:
|
NAMESPACE MAPPING OPTIMIZATION IN NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/30/2018
|
Application #:
|
15814835
|
Filing Dt:
|
11/16/2017
|
|
Title:
|
ELECTRONIC DEVICE WITH A FUSE READ MECHANISM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2019
|
Application #:
|
15814882
|
Filing Dt:
|
11/16/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
|
Title:
|
Capacitors and Integrated Assemblies Which Include Capacitors
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/09/2020
|
Application #:
|
15814934
|
Filing Dt:
|
11/16/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/16/2019
| | | | |
|
Title:
|
NAMESPACE MAPPING STRUCTUAL ADJUSTMENT IN NON-VOLATILE MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
|
Application #:
|
15815037
|
Filing Dt:
|
11/16/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2018
| | | | |
|
Title:
|
APPARATUSES AND METHODS FOR MIXED CHARGE PUMPS WITH VOLTAGE REGULATOR CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/10/2019
|
Application #:
|
15815209
|
Filing Dt:
|
11/16/2017
|
|
Publication #:
|
|
Pub Dt:
|
11/22/2018
| | | | |
|
Title:
|
PROVIDING ENERGY INFORMATION TO MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2019
|
Application #:
|
15815521
|
Filing Dt:
|
11/16/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/29/2018
| | | | |
|
Title:
|
RECLAIMABLE SEMICONDUCTOR DEVICE PACKAGE AND ASSOCIATED SYSTEMS AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/2019
|
Application #:
|
15816484
|
Filing Dt:
|
11/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2019
| | | | |
|
Title:
|
MEMORY DEVICES WITH DISTRIBUTED BLOCK SELECT FOR A VERTICAL STRING DRIVER TILE ARCHITECTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2018
|
Application #:
|
15816889
|
Filing Dt:
|
11/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2018
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING FUSE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2020
|
Application #:
|
15817000
|
Filing Dt:
|
11/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2019
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE WITH A MULTI-LAYERED ENCAPSULANT AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/2019
|
Application #:
|
15818338
|
Filing Dt:
|
11/20/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/15/2018
| | | | |
|
Title:
|
Integrated Assemblies and Methods of Forming Integrated Assemblies
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2019
|
Application #:
|
15818571
|
Filing Dt:
|
11/20/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2018
| | | | |
|
Title:
|
Memory Cell, An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor With The Array Comprising Rows Of Access Lines And Columns Of Digit Lines, A 2T-1C Memory Cell, And Methods Of Forming An Array Of Capacitors And Access Transistors There-Above
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/12/2019
|
Application #:
|
15818934
|
Filing Dt:
|
11/21/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/12/2018
| | | | |
|
Title:
|
Arrays Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor, Methods Of Forming A Tier Of An Array Of Memory Cells, And Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/2019
|
Application #:
|
15819692
|
Filing Dt:
|
11/21/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2019
| | | | |
|
Title:
|
DATA CATEGORIZATION BASED ON INVALIDATION VELOCITIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2021
|
Application #:
|
15819941
|
Filing Dt:
|
11/21/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2019
| | | | |
|
Title:
|
LAST WRITTEN PAGE SEARCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2019
|
Application #:
|
15821240
|
Filing Dt:
|
11/22/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/23/2019
| | | | |
|
Title:
|
PULSED INTEGRATOR AND MEMORY TECHNIQUES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/17/2020
|
Application #:
|
15822748
|
Filing Dt:
|
11/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/22/2018
| | | | |
|
Title:
|
COMPARISON OPERATIONS IN MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2018
|
Application #:
|
15823013
|
Filing Dt:
|
11/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/22/2018
| | | | |
|
Title:
|
DATA SHIFTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
15823139
|
Filing Dt:
|
11/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
03/22/2018
| | | | |
|
Title:
|
Cross-Point Memory Cells, Non-Volatile Memory Arrays, Methods of Reading a Memory Cell, Methods of Programming a Memory Cell, Methods of Writing to and Reading from a Memory Cell, and Computer Systems
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/09/2019
|
Application #:
|
15824535
|
Filing Dt:
|
11/28/2017
|
|
Title:
|
POWER REDUCTION TECHNIQUE DURING WRITE BURSTS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15824559
|
Filing Dt:
|
11/28/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2019
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR TEMPERATURE SENSOR ACCESS IN DIE STACKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/17/2019
|
Application #:
|
15826236
|
Filing Dt:
|
11/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2019
| | | | |
|
Title:
|
SYSTEMS AND METHODS FOR IMPROVING WRITE PREAMBLES IN DDR MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2019
|
Application #:
|
15826404
|
Filing Dt:
|
11/29/2017
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2019
| | | | |
|
Title:
|
SIGNAL TRAINING FOR PREVENTION OF METASTABILITY DUE TO CLOCKING INDETERMINACY
|
|
