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Reel/Frame:050896/0366   Pages: 51
Recorded: 10/28/2019
Attorney Dkt #:127110/12
Conveyance: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY
Total properties: 1522
Page 2 of 16
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
Patent #:
Issue Dt:
05/24/2005
Application #:
09989819
Filing Dt:
11/19/2001
Title:
SYSTEM AND METHOD FOR CREATING A BOOT FILE UTILIZING A BOOT TEMPLATE
2
Patent #:
Issue Dt:
02/26/2008
Application #:
09994599
Filing Dt:
11/19/2001
Title:
AUTOMATIC APPLICATION PROGRAMMING INTERFACE (API) GENERATION FOR FUNCTIONAL BLOCKS
3
Patent #:
Issue Dt:
08/03/2010
Application #:
09994600
Filing Dt:
11/19/2001
Title:
SYSTEM AND METHOD FOR DYNAMICALLY GENERATING A CONFIGURATION DATASHEET
4
Patent #:
Issue Dt:
10/18/2011
Application #:
09998848
Filing Dt:
11/15/2001
Title:
DESIGN SYSTEM PROVIDING AUTOMATIC SOURCE CODE GENERATION FOR PERSONALIZATION AND PARAMETERIZATION OF USER MODULES
5
Patent #:
Issue Dt:
02/21/2006
Application #:
09999609
Filing Dt:
10/31/2001
Title:
METHOD AND SYSTEM FOR DATA-DRIVEN DISPLAY GRIDS
6
Patent #:
Issue Dt:
01/21/2003
Application #:
09999869
Filing Dt:
10/23/2001
Title:
DRAIN SIDE SENSING SCHEME FOR VIRTUAL GROUND FLASH EPROM ARRAY WITH ADJACENT BIT CHARGE AND HOLD
7
Patent #:
Issue Dt:
07/29/2008
Application #:
10002726
Filing Dt:
10/24/2001
Title:
METHOD AND APPARATUS FOR GENERATING MICROCONTROLLER CONFIGURATION INFORMATION
8
Patent #:
Issue Dt:
10/25/2005
Application #:
10008548
Filing Dt:
11/09/2001
Title:
QUICK CLICK ICONS FOR WORKSPACE FLOW BETWEEN VIEWS FOR MAJOR SUBSYSTEMS AND VIEWS WITHIN A DESIGN TOOL
9
Patent #:
Issue Dt:
03/30/2004
Application #:
10010837
Filing Dt:
12/04/2001
Title:
BORDERLESS CONTACT ARCHITECTURE
10
Patent #:
Issue Dt:
09/27/2005
Application #:
10011214
Filing Dt:
10/25/2001
Title:
METHOD AND CIRCUIT FOR SYNCHRONIZING A WRITE OPERATION BETWEEN AN ON-CHIP MICROPROCESSOR AND AN ON-CHIP PROGRAMMABLE ANALOG DEVICE OPERATING AT DIFFERENT FREQUENCIES
11
Patent #:
Issue Dt:
06/08/2004
Application #:
10011696
Filing Dt:
12/05/2001
Title:
INTERFACE SCHEME FOR CONNECTING A FIXED CIRCUITRY BLOCK TO A PROGRAMMABLE LOGIC CORE
12
Patent #:
Issue Dt:
10/01/2002
Application #:
10022119
Filing Dt:
12/13/2001
Title:
SELF REFERENCING 1T/1C FERROELECTRIC RANDOM ACCESS MEMORY
13
Patent #:
Issue Dt:
12/31/2002
Application #:
10023349
Filing Dt:
12/20/2001
Title:
METHOD FOR REPAIRING DAMAGE TO CHARGE TRAPPING DIELECTRIC LAYER FROM BIT LINE IMPLANTATION
14
Patent #:
Issue Dt:
11/25/2003
Application #:
10029371
Filing Dt:
12/20/2001
Title:
CIRCUIT AND METHOD FOR REDUCING VOLTAGE STRESS IN A MEMORY DECODER
15
Patent #:
Issue Dt:
11/28/2006
Application #:
10032986
Filing Dt:
10/29/2001
Title:
PIN-OUT CONNECTIONS/DRIVE LEVELS DIRECT-SET BY DROP DOWN LIST
16
Patent #:
Issue Dt:
05/08/2012
Application #:
10033027
Filing Dt:
10/22/2001
Publication #:
Pub Dt:
08/08/2002
Title:
MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP
17
Patent #:
Issue Dt:
01/11/2005
Application #:
10039469
Filing Dt:
11/08/2001
Title:
IN SITU DEPOSITION OF A NITRIDE LAYER AND OF AN ANTI-REFLECTIVE LAYER
18
Patent #:
Issue Dt:
02/04/2003
Application #:
10050254
Filing Dt:
01/16/2002
Title:
NEGATIVE PUMP REGULATOR USING MOS CAPACITOR
19
Patent #:
Issue Dt:
03/04/2003
Application #:
10050257
Filing Dt:
01/16/2002
Title:
SOURCE SIDE SENSING SCHEME FOR VIRTUAL GROUND READ OF FLASH EPROM ARRAY WITH ADJACENT BIT PRECHARGE
20
Patent #:
Issue Dt:
08/03/2004
Application #:
10050394
Filing Dt:
01/16/2002
Title:
DIODE FABRICATION FOR ESD/EOS PROTECTION
21
Patent #:
Issue Dt:
03/11/2003
Application #:
10050650
Filing Dt:
01/16/2002
Title:
METHOD AND APPARATUS FOR SOFT PROGRAM VERIFICATION IN A MEMORY DEVICE
22
Patent #:
Issue Dt:
02/08/2005
Application #:
10053256
Filing Dt:
01/18/2002
Title:
TWO-STEP SOURCE SIDE IMPLANT FOR IMPROVING SOURCE RESISTANCE AND SHORT CHANNEL EFFECT IN DEEP SUB-0.18MUM FLASH MEMORY TECHNOLOGY
23
Patent #:
Issue Dt:
04/11/2006
Application #:
10072164
Filing Dt:
02/07/2002
Title:
DUAL-DAMASCENE PROCESS AND ASSOCIATED FLOATING METAL STRUCTURES
24
Patent #:
Issue Dt:
03/11/2008
Application #:
10073570
Filing Dt:
02/11/2002
Publication #:
Pub Dt:
03/06/2003
Title:
DEVICE FOR PROCESSING DATA SIGNALS, METHOD THEREOF, AND DEVICE FOR MULTIPLEXING DATA SIGNALS
25
Patent #:
Issue Dt:
10/08/2002
Application #:
10081246
Filing Dt:
02/22/2002
Title:
DUMMY GATE PROCESS TO REDUCE THE VSS RESISTANCE OF FLASH PRODUCTS
26
Patent #:
Issue Dt:
05/04/2004
Application #:
10083592
Filing Dt:
02/27/2002
Publication #:
Pub Dt:
09/05/2002
Title:
DC-DC CONVERTER WITH CONTROL CIRCUIT CAPABLE OF GENERATING STEP-UP AND STEP-DOWN SIGNALS
27
Patent #:
Issue Dt:
11/25/2003
Application #:
10083789
Filing Dt:
02/27/2002
Title:
METHOD OF MATCHING CORE CELL AND REFERENCE CELL SOURCE RESISTANCES
28
Patent #:
Issue Dt:
08/26/2003
Application #:
10087852
Filing Dt:
03/05/2002
Publication #:
Pub Dt:
09/12/2002
Title:
DC-DC CONVERTER, POWER SUPPLY CIRCUIT, METHOD FOR CONTROLLING DC-DC CONVERTER, AND METHOD FOR CONTROLLING POWER SUPPLY CIRCUIT
29
Patent #:
Issue Dt:
11/14/2006
Application #:
10090822
Filing Dt:
03/06/2002
Publication #:
Pub Dt:
03/13/2003
Title:
SEMICONDUCTOR DEVICE
30
Patent #:
Issue Dt:
05/04/2004
Application #:
10091767
Filing Dt:
03/07/2002
Title:
PASSWORD AND DYNAMIC PROTECTION OF FLASH MEMORY DATA
31
Patent #:
Issue Dt:
12/19/2006
Application #:
10097674
Filing Dt:
03/14/2002
Title:
POLY/SILICIDE STACK AND METHOD OF FORMING THE SAME
32
Patent #:
Issue Dt:
10/28/2003
Application #:
10099499
Filing Dt:
03/13/2002
Title:
OVERERASE CORRECTION METHOD
33
Patent #:
Issue Dt:
03/16/2004
Application #:
10100485
Filing Dt:
03/14/2002
Publication #:
Pub Dt:
01/22/2004
Title:
HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
34
Patent #:
Issue Dt:
10/12/2004
Application #:
10109234
Filing Dt:
03/27/2002
Title:
LINER FOR SEMICONDUCTOR MEMORIES AND MANUFACTURING METHOD THEREFOR
35
Patent #:
Issue Dt:
09/09/2003
Application #:
10109235
Filing Dt:
03/27/2002
Title:
MEMORY WORDLINE HARD MASK
36
Patent #:
Issue Dt:
11/12/2002
Application #:
10109516
Filing Dt:
03/27/2002
Title:
METHOD OF MAKING MEMORY WORDLINE HARD MASK EXTENSION
37
Patent #:
Issue Dt:
06/27/2006
Application #:
10113107
Filing Dt:
03/29/2002
Title:
METHOD AND SYSTEM FOR PROVIDING A BINARY DEMODULATOR
38
Patent #:
Issue Dt:
06/28/2005
Application #:
10113180
Filing Dt:
03/29/2002
Title:
METHOD AND/OR APPARATUS FOR IMPLEMENTING SECURITY IN KEYBOARD-COMPUTER COMMUNICATION
39
Patent #:
Issue Dt:
03/25/2003
Application #:
10114535
Filing Dt:
04/01/2002
Title:
FERROELECTRIC MEMORY WITH BIT-PLATE PARALLEL ARCHITECTURE AND OPERATING METHOD THEREOF
40
Patent #:
Issue Dt:
06/15/2004
Application #:
10117818
Filing Dt:
04/08/2002
Title:
PRECISION HIGH-K INTERGATE DIELECTRIC LAYER
41
Patent #:
Issue Dt:
08/29/2006
Application #:
10118682
Filing Dt:
04/08/2002
Title:
PINOUT VIEWS FOR ALLOWED CONNECTIONS IN GUI
42
Patent #:
Issue Dt:
03/18/2014
Application #:
10118732
Filing Dt:
04/08/2002
Publication #:
Pub Dt:
10/09/2003
Title:
MEMORY MANUFACTURING PROCESS WITH BITLINE ISOLATION
43
Patent #:
Issue Dt:
03/02/2004
Application #:
10119273
Filing Dt:
04/08/2002
Publication #:
Pub Dt:
10/09/2003
Title:
REFRESH SCHEME FOR DYNAMIC PAGE PROGRAMMING
44
Patent #:
Issue Dt:
05/31/2005
Application #:
10119366
Filing Dt:
04/08/2002
Title:
ERASE METHOD FOR A DUAL BIT MEMORY CELL
45
Patent #:
Issue Dt:
02/10/2004
Application #:
10119391
Filing Dt:
04/08/2002
Title:
ALGORITHM DYNAMIC REFERENCE PROGRAMMING
46
Patent #:
Issue Dt:
01/04/2005
Application #:
10119574
Filing Dt:
04/09/2002
Title:
METHODS OF FORMING SEMICONDUCTOR STRUCTURES, AND ARTICLES AND DEVICES FORMED THEREBY
47
Patent #:
Issue Dt:
12/05/2006
Application #:
10124773
Filing Dt:
04/16/2002
Title:
HIDING REFRESH IN 1T-SRAM ARCHITECTURE
48
Patent #:
Issue Dt:
04/06/2004
Application #:
10126207
Filing Dt:
04/19/2002
Title:
USING A FIRST LINER LAYER AS A SPACER IN A SEMICONDUCTOR DEVICE
49
Patent #:
Issue Dt:
12/30/2003
Application #:
10128771
Filing Dt:
04/22/2002
Title:
SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
50
Patent #:
Issue Dt:
01/30/2007
Application #:
10134764
Filing Dt:
04/29/2002
Title:
CHIP SELECT METHOD THROUGH DOUBLE BONDING
51
Patent #:
Issue Dt:
09/16/2003
Application #:
10136033
Filing Dt:
04/29/2002
Title:
SYSTEM FOR PROGRAMMING A FLASH MEMORY DEVICE
52
Patent #:
Issue Dt:
11/09/2004
Application #:
10136034
Filing Dt:
04/29/2002
Publication #:
Pub Dt:
10/30/2003
Title:
SYSTEM FOR CONTROL OF PRE-CHARGE LEVELS IN A MEMORY DEVICE
53
Patent #:
Issue Dt:
10/09/2007
Application #:
10146560
Filing Dt:
05/15/2002
Title:
CIRCUIT FOR DRIVING A LASER DIODE AND METHOD
54
Patent #:
Issue Dt:
08/26/2003
Application #:
10150204
Filing Dt:
05/15/2002
Title:
SELF-ALIGNED POLYSILICON POLISH
55
Patent #:
Issue Dt:
10/26/2004
Application #:
10150240
Filing Dt:
05/15/2002
Title:
METHOD AND SYSTEM FOR TAILORING CORE AND PERIPHERY CELLS IN A NONVOLATILE MEMORY
56
Patent #:
Issue Dt:
10/19/2004
Application #:
10150255
Filing Dt:
05/15/2002
Title:
METHOD AND SYSTEM FOR SCALING NONVOLATILE MEMORY CELLS
57
Patent #:
Issue Dt:
12/26/2006
Application #:
10150677
Filing Dt:
05/17/2002
Title:
INTERMEDIATE FREQUENCY TUNER
58
Patent #:
Issue Dt:
04/24/2007
Application #:
10151595
Filing Dt:
05/16/2002
Title:
SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TRENCH
59
Patent #:
Issue Dt:
07/18/2006
Application #:
10163970
Filing Dt:
06/06/2002
Title:
IN SITU HARD MASK APPROACH FOR SELF-ALIGNED CONTACT ETCH
60
Patent #:
Issue Dt:
07/04/2006
Application #:
10164465
Filing Dt:
06/05/2002
Title:
USER MODULE PARAMETER AND REGISTER CONFIGURATION BLOCK
61
Patent #:
Issue Dt:
03/20/2007
Application #:
10184336
Filing Dt:
06/26/2002
Title:
PROTECTION OF A LOW-K DIELECTRIC IN A PASSIVATION LEVEL
62
Patent #:
Issue Dt:
04/27/2004
Application #:
10186466
Filing Dt:
06/28/2002
Title:
STOCHASTIC PULSE GENERATOR DEVICE AND METHOD OF SAME
63
Patent #:
Issue Dt:
05/30/2006
Application #:
10190002
Filing Dt:
07/03/2002
Title:
METHOD FOR SEMICONDUCTOR WAFER PLANARIZATION BY ISOLATION MATERIAL GROWTH
64
Patent #:
Issue Dt:
03/25/2003
Application #:
10194270
Filing Dt:
07/11/2002
Publication #:
Pub Dt:
12/26/2002
Title:
SUBSTRATE ISOLATED TRANSISTOR
65
Patent #:
Issue Dt:
11/02/2004
Application #:
10197116
Filing Dt:
07/16/2002
Publication #:
Pub Dt:
01/22/2004
Title:
SYSTEM FOR USING A DYNAMIC REFERENCE IN A DOUBLE-BIT CELL MEMORY
66
Patent #:
Issue Dt:
06/29/2004
Application #:
10198508
Filing Dt:
07/17/2002
Title:
CONTROL TRANSACTION HANDLING IN A DEVICE CONTROLLER
67
Patent #:
Issue Dt:
12/16/2003
Application #:
10200330
Filing Dt:
07/22/2002
Title:
ON-CHIP ERASE PULSE COUNTER FOR EFFICIENT ERASE VERIFY BIST (BUILT-IN-SELF-TEST) MODE
68
Patent #:
Issue Dt:
09/23/2003
Application #:
10200396
Filing Dt:
07/22/2002
Publication #:
Pub Dt:
11/28/2002
Title:
PROCESS FOR ANNEALING SEMICONDUCTORS AND/OR INTEGRATED CIRCUITS
69
Patent #:
Issue Dt:
10/07/2003
Application #:
10200544
Filing Dt:
07/22/2002
Title:
ON-CHIP REPAIR OF DEFECTIVE ADDRESS OF CORE FLASH MEMORY CELLS
70
Patent #:
Issue Dt:
08/29/2006
Application #:
10205414
Filing Dt:
07/26/2002
Publication #:
Pub Dt:
05/29/2003
Title:
SEMICONDUCTOR DEVICE AND LIQUID CRYSTAL PANEL DRIVER DEVICE
71
Patent #:
Issue Dt:
07/27/2004
Application #:
10210279
Filing Dt:
08/01/2002
Title:
INPUT GATE PROTECTION CIRCUIT AND METHOD
72
Patent #:
Issue Dt:
05/10/2005
Application #:
10210378
Filing Dt:
07/31/2002
Title:
SYSTEM AND METHOD FOR ERASE VOLTAGE CONTROL DURING MULTIPLE SECTOR ERASE OF A FLASH MEMORY DEVICE
73
Patent #:
Issue Dt:
10/26/2004
Application #:
10217403
Filing Dt:
08/14/2002
Title:
REFLOWABLE-DOPED HDP FILM
74
Patent #:
Issue Dt:
05/04/2004
Application #:
10217821
Filing Dt:
08/12/2002
Title:
SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
75
Patent #:
Issue Dt:
03/30/2010
Application #:
10222155
Filing Dt:
08/16/2002
Title:
APPARATUS, SYSTEM AND METHOD FOR SHARING DATA FROM A DEVICE BETWEEN MULTIPLE COMPUTERS
76
Patent #:
Issue Dt:
06/22/2004
Application #:
10223920
Filing Dt:
08/20/2002
Title:
MEMORY DEVICE AND METHOD OF MAKING
77
Patent #:
Issue Dt:
03/31/2009
Application #:
10225658
Filing Dt:
08/21/2002
Title:
DIFFERENTIAL CRYSTAL OSCILLATOR
78
Patent #:
Issue Dt:
09/19/2006
Application #:
10226778
Filing Dt:
08/23/2002
Title:
SYSTEM AND METHOD FOR DATA TRANSFORMATION OF DEVICE DATABASES FOR FORWARD COMPATIBILITY
79
Patent #:
Issue Dt:
08/03/2004
Application #:
10226912
Filing Dt:
08/22/2002
Publication #:
Pub Dt:
02/26/2004
Title:
PRECHARGING SCHEME FOR READING A MEMORY CELL
80
Patent #:
Issue Dt:
08/31/2004
Application #:
10229481
Filing Dt:
08/28/2002
Title:
INPUT BUFFER SYSTEM USING LOW VOLTAGE TRANSISTORS
81
Patent #:
Issue Dt:
08/31/2004
Application #:
10233696
Filing Dt:
09/03/2002
Title:
INPUT BUFFER CIRCUIT
82
Patent #:
Issue Dt:
07/20/2004
Application #:
10237805
Filing Dt:
09/10/2002
Publication #:
Pub Dt:
01/09/2003
Title:
METHOD FOR MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY AND NON-VOLATILE SEMICONDUCTOR MEMORY MANUFACTURED THEREBY
83
Patent #:
Issue Dt:
07/20/2010
Application #:
10238966
Filing Dt:
09/09/2002
Title:
METHOD FOR PARAMETERIZING A USER MODULE
84
Patent #:
Issue Dt:
06/07/2005
Application #:
10241236
Filing Dt:
09/11/2002
Title:
LOW-K DIELECTRIC LAYER WITH AIR GAPS
85
Patent #:
Issue Dt:
11/28/2006
Application #:
10243315
Filing Dt:
09/12/2002
Publication #:
Pub Dt:
03/18/2004
Title:
SYSTEM AND METHOD FOR Y-DECODING IN A FLASH MEMORY DEVICE
86
Patent #:
Issue Dt:
06/01/2004
Application #:
10243792
Filing Dt:
09/12/2002
Title:
METHOD AND SYSTEM TO MINIMIZE PAGE PROGRAMMING TIME FOR FLASH MEMORY DEVICES
87
Patent #:
Issue Dt:
06/22/2004
Application #:
10245146
Filing Dt:
09/16/2002
Title:
REFERENCE CELL WITH VARIOUS LOAD CIRCUITS COMPENSATING FOR SOURCE SIDE LOADING EFFECTS IN A NON-VOLATILE MEMORY
88
Patent #:
Issue Dt:
07/18/2006
Application #:
10251623
Filing Dt:
09/20/2002
Title:
AUTOMATIC BACKUP AND RETRIEVAL OF DATA BETWEEN VOLATILE AND NON-VOLATILE MEMORIES
89
Patent #:
Issue Dt:
09/10/2013
Application #:
10256829
Filing Dt:
09/27/2002
Title:
GRAPHICAL USER INTERFACE FOR DYNAMICALLY RECONFIGURING A PROGRAMMABLE DEVICE
90
Patent #:
Issue Dt:
03/20/2007
Application #:
10260108
Filing Dt:
09/27/2002
Title:
DEVICE AND METHOD FOR MANAGING POWER CONSUMED BY A USB DEVICE
91
Patent #:
Issue Dt:
10/21/2008
Application #:
10277395
Filing Dt:
10/22/2002
Publication #:
Pub Dt:
09/18/2003
Title:
SHALLOW TRENCH ISOLATION APPROACH FOR IMPROVED STI CORNER ROUNDING
92
Patent #:
Issue Dt:
11/16/2004
Application #:
10294808
Filing Dt:
11/13/2002
Title:
AMPLIFIER BIASING
93
Patent #:
Issue Dt:
09/12/2006
Application #:
10295662
Filing Dt:
11/15/2002
Title:
DEMODULATOR ARCHITECTURE AND ASSOCIATED METHODS
94
Patent #:
Issue Dt:
09/20/2005
Application #:
10301649
Filing Dt:
11/22/2002
Publication #:
Pub Dt:
06/05/2003
Title:
OFFSET CANCEL CIRCUIT OF VOLTAGE FOLLOWER EQUIPPED WITH OPERATIONAL AMPLIFIER
95
Patent #:
Issue Dt:
07/27/2004
Application #:
10302672
Filing Dt:
11/22/2002
Publication #:
Pub Dt:
05/27/2004
Title:
CASCODE AMPLIFIER CIRCUIT FOR PRODUCING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
96
Patent #:
Issue Dt:
08/22/2006
Application #:
10304389
Filing Dt:
11/25/2002
Title:
MEMORY MANAGEMENT
97
Patent #:
Issue Dt:
06/28/2005
Application #:
10305589
Filing Dt:
11/26/2002
Title:
CURRENT CONTROLLED DELAY CIRCUIT
98
Patent #:
Issue Dt:
07/11/2006
Application #:
10305700
Filing Dt:
11/26/2002
Title:
METHOD AND SYSTEM FOR DEFINING A REDUNDANCY WINDOW AROUND A PARTICULAR COLUMN IN A MEMORY ARRAY
99
Patent #:
Issue Dt:
05/24/2005
Application #:
10305750
Filing Dt:
11/26/2002
Title:
METHOD OF PROTECTING A MEMORY ARRAY FROM CHARGE DAMAGE DURING FABRICATION
100
Patent #:
Issue Dt:
06/14/2005
Application #:
10306252
Filing Dt:
11/27/2002
Publication #:
Pub Dt:
09/02/2004
Title:
METHOD AND SYSTEM FOR ERASING A NITRIDE MEMORY DEVICE
Assignor
1
Exec Dt:
07/31/2019
Assignee
1
350 CALIFORNIA STREET
17TH FLOOR
SAN FRANCISCO, CALIFORNIA 94104
Correspondence name and address
SKADDEN, ARPS, SLATE, MEAGHER & FLOM LLP
FOUR TIMES SQUARE
ATTN: JUSTIN C. SELLE
NEW YORK, NY 10036

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