|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/09/2005
|
Application #:
|
10821312
|
Filing Dt:
|
04/08/2004
|
|
Title:
|
NARROW WIDE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/2008
|
Application #:
|
10823529
|
Filing Dt:
|
04/13/2004
|
|
Title:
|
SOFT ERROR RESISTANT MEMORY CELL AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/15/2009
|
Application #:
|
10823970
|
Filing Dt:
|
04/13/2004
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A PAD METAL LAYER AND A LOWER METAL LAYER THAT ARE ELECTRICALLY COUPLED, WHEREAS APERTURES ARE FORMED IN THE LOWER METAL LAYER BELOW A CENTER AREA OF THE PAD METAL LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10823972
|
Filing Dt:
|
04/13/2004
|
|
Title:
|
MEMORY DEVICE WITH AN ALTERNATING VSS INTERCONNECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10827785
|
Filing Dt:
|
04/19/2004
|
|
Title:
|
CURRENT SOURCE ARCHITECTURE FOR MEMORY DEVICE STANDBY CURRENT REDUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2006
|
Application #:
|
10835341
|
Filing Dt:
|
04/28/2004
|
|
Title:
|
METHOD FOR PROVIDING SHORT CHANNEL EFFECT CONTROL USING A SILICIDE VSS LINE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
10838962
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
METHOD FOR MINIMIZING FALSE DETECTION OF STATES IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2006
|
Application #:
|
10839561
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
METHOD AND APPARATUS FOR ELIMINATING WORD LINE BENDING BY SOURCE SIDE IMPLANTATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10839562
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
POSITIVE GATE STRESS DURING ERASE TO IMPROVE RETENTION IN MULTI-LEVEL, NON-VOLATILE FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2007
|
Application #:
|
10839614
|
Filing Dt:
|
05/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/10/2005
| | | | |
|
Title:
|
METHODS AND APPARATUS FOR WORDLINE PROTECTION IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/08/2005
|
Application #:
|
10839626
|
Filing Dt:
|
05/04/2004
|
|
Title:
|
MEMORY ARRAY WITH MEMORY CELLS HAVING REDUCED SHORT CHANNEL EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/13/2005
|
Application #:
|
10841933
|
Filing Dt:
|
05/06/2004
|
|
Title:
|
STRUCTURE AND METHOD FOR PROTECTING MEMORY CELLS FROM UV RADIATION DAMAGE AND UV RADIATION-INDUCED CHARGING DURING BACKEND PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/24/2006
|
Application #:
|
10843289
|
Filing Dt:
|
05/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
11/17/2005
| | | | |
|
Title:
|
BITLINE IMPLANT UTILIZING DUAL POLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/2005
|
Application #:
|
10844116
|
Filing Dt:
|
05/12/2004
|
|
Title:
|
CASCODE AMPLIFIER CIRCUIT FOR GENERATING AND MAINTAINING A FAST, STABLE AND ACCURATE BIT LINE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/03/2009
|
Application #:
|
10849958
|
Filing Dt:
|
05/21/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/17/2005
| | | | |
|
Title:
|
OPERATION MODE CONTROL CIRCUIT, MICROCOMPUTER INCLUDING THE SAME, AND CONTROL SYSTEM USING THE MICROCOMPUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
10850286
|
Filing Dt:
|
05/19/2004
|
|
Title:
|
A USB PERIPHERAL DEVICE STORING AN INDICATION OF AN OPERATING POWER MODE WHEN A HOST WENT INTO HIBERNATE AND RESTARTING AT THE POWER MODE ACCORDINGLY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10857039
|
Filing Dt:
|
05/28/2004
|
|
Title:
|
POWER ON RESET CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2006
|
Application #:
|
10860450
|
Filing Dt:
|
06/03/2004
|
|
Title:
|
METHOD OF DETERMINING VOLTAGE COMPENSATION FOR FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2007
|
Application #:
|
10861575
|
Filing Dt:
|
06/04/2004
|
|
Title:
|
METHOD AND SYSTEM FOR IMPROVING THE TOPOGRAPHY OF A MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/06/2008
|
Application #:
|
10861714
|
Filing Dt:
|
06/04/2004
|
|
Title:
|
BALL GRID ARRAY PACKAGE HAVING INTEGRATED ANTENNA PAD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10862636
|
Filing Dt:
|
06/07/2004
|
|
Title:
|
LDC IMPLANT FOR MIRRORBIT TO IMPROVE VT ROLL-OFF AND FORM SHARPER JUNCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10864947
|
Filing Dt:
|
06/10/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
|
Title:
|
ERASE ALGORITHM FOR MULTI-LEVEL BIT FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
10869286
|
Filing Dt:
|
06/16/2004
|
|
Title:
|
ALIGNMENT MARKS WITH SALICIDED SPACERS BETWEEN BITLINES FOR ALIGNMENT SIGNAL IMPROVEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/07/2006
|
Application #:
|
10869774
|
Filing Dt:
|
06/16/2004
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH CORE AND PERIPHERY REGIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10871825
|
Filing Dt:
|
06/18/2004
|
|
Title:
|
MEMORY INTERFACE SYSTEM AND METHOD FOR REDUCING CYCLE TIME OF SEQUENTIAL READ AND WRITE ACCESSES USING SEPARATE ADDRESS AND DATA BUSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10877296
|
Filing Dt:
|
06/24/2004
|
|
Title:
|
BINDING FOR ONE-WAY WIRELESS TRANSMISSIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
10877313
|
Filing Dt:
|
06/25/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
MEMORY CELL ARRAY LATCHUP PREVENTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/19/2009
|
Application #:
|
10877932
|
Filing Dt:
|
06/25/2004
|
|
Title:
|
CONFIGURABLE DATA PATH ARCHITECTURE AND CLOCKING SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
10889245
|
Filing Dt:
|
07/12/2004
|
|
Title:
|
POWER ON RESET CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/09/2008
|
Application #:
|
10896292
|
Filing Dt:
|
07/20/2004
|
|
Title:
|
APPARATUS AND METHOD FOR A MEMORY ARRAY WITH SHALLOW TRENCH ISOLATION REGIONS BETWEEN BIT LINES FOR INCREASED PROCESS MARGINS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10896299
|
Filing Dt:
|
07/20/2004
|
|
Title:
|
METHOD FOR PROGRAMMING DUAL BIT MEMORY DEVICES TO REDUCE COMPLEMENTARY BIT DISTURBANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
10899072
|
Filing Dt:
|
07/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
06/09/2005
| | | | |
|
Title:
|
SERIAL COMMUNICATION DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
10899344
|
Filing Dt:
|
07/26/2004
|
|
Title:
|
THREE DIMENSIONAL POLYMER MEMORY CELL SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2006
|
Application #:
|
10909693
|
Filing Dt:
|
08/02/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/02/2006
| | | | |
|
Title:
|
FLASH MEMORY UNIT AND METHOD OF PROGRAMMING A FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/2009
|
Application #:
|
10916167
|
Filing Dt:
|
08/11/2004
|
|
Publication #:
|
|
Pub Dt:
|
02/16/2006
| | | | |
|
Title:
|
METHOD OF FORMING NARROWLY SPACED FLASH MEMORY CONTACT OPENINGS AND LITHOGRAPHY MASKS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
10917562
|
Filing Dt:
|
08/13/2004
|
|
Title:
|
USING THIN UNDOPED TEOS WITH BPTEOS ILD OR BPTEOS ILD ALONE TO IMPROVE CHARGE LOSS AND CONTACT RESISTANCE IN MULTI BIT MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
10927365
|
Filing Dt:
|
08/26/2004
|
|
Title:
|
METHOD OF REDUCING STEP HEIGHT DIFFERENCE BETWEEN DOPED REGIONS OF FIELD OXIDE IN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2007
|
Application #:
|
10927583
|
Filing Dt:
|
08/26/2004
|
|
Title:
|
MEMORY ARRAY WITH CURRENT LIMITING DEVICE FOR PREVENTING PARTICLE INDUCED LATCH-UP
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/11/2007
|
Application #:
|
10936275
|
Filing Dt:
|
09/08/2004
|
|
Title:
|
METHOD FOR REDUCING SOFT ERROR RATES OF MEMORY CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10939897
|
Filing Dt:
|
09/13/2004
|
|
Title:
|
METHOD OF FORMING COPPER SULFIDE LAYER OVER SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
10941753
|
Filing Dt:
|
09/15/2004
|
|
Title:
|
LOW VOLTAGE LOGIC CIRCUIT WITH SET AND/OR RESET FUNCTIONALITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2006
|
Application #:
|
10945914
|
Filing Dt:
|
09/22/2004
|
|
Title:
|
METHODS AND SYSTEMS FOR REDUCING ERASE TIMES IN FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2006
|
Application #:
|
10947538
|
Filing Dt:
|
09/23/2004
|
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND MICROCONTROLLER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2007
|
Application #:
|
10948524
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
10/27/2005
| | | | |
|
Title:
|
LEVEL CONVERSION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/2010
|
Application #:
|
10949093
|
Filing Dt:
|
09/23/2004
|
|
Title:
|
MAPPING OF NON-ISOCHRONOUS AND ISOCHRONOUS CHANNELS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2007
|
Application #:
|
10949176
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
|
Title:
|
NONVOLATILE PROGRAMMABLE CRYSTAL OSCILLATOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2008
|
Application #:
|
10950332
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/31/2005
| | | | |
|
Title:
|
OXIDE-NITRIDE STACK GATE DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2006
|
Application #:
|
10968713
|
Filing Dt:
|
10/19/2004
|
|
Title:
|
PATTERNING FOR ELONGATED VSS CONTACT FLASH MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2007
|
Application #:
|
10973257
|
Filing Dt:
|
10/27/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
|
Title:
|
CONTROL CIRCUIT OF DC-DC CONVERTER AND ITS CONTROL METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/22/2008
|
Application #:
|
10976816
|
Filing Dt:
|
11/01/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/04/2006
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR PROTECTING SEMICONDUCTOR DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2007
|
Application #:
|
10978045
|
Filing Dt:
|
10/29/2004
|
|
Title:
|
VARIABLE CAPACITANCE CHARGE PUMP SYSTEM AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
10979516
|
Filing Dt:
|
11/02/2004
|
|
Title:
|
METHOD OF MAKING A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
10981792
|
Filing Dt:
|
11/05/2004
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2005
| | | | |
|
Title:
|
CIRCUIT AND METHOD FOR CONTROLLING DC-DC CONVERTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/02/2006
|
Application #:
|
10982296
|
Filing Dt:
|
11/05/2004
|
|
Title:
|
MULTI BIT PROGRAM ALGORITHM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/28/2008
|
Application #:
|
10983919
|
Filing Dt:
|
11/08/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
|
Title:
|
CONTROL OF MEMORY DEVICES POSSESSING VARIABLE RESISTANCE CHARACTERISTICS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2006
|
Application #:
|
10984065
|
Filing Dt:
|
11/09/2004
|
|
Publication #:
|
|
Pub Dt:
|
05/11/2006
| | | | |
|
Title:
|
CIRCUIT FOR GENERATING A CENTERED REFERENCE VOLTAGE FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
10984104
|
Filing Dt:
|
11/09/2004
|
|
Title:
|
ADAPTIVE OUTPUT DRIVER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11001940
|
Filing Dt:
|
12/01/2004
|
|
Title:
|
METHOD, SYSTEM, AND CIRCUIT FOR PERFORMING A MEMORY RELATED OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2006
|
Application #:
|
11003208
|
Filing Dt:
|
12/02/2004
|
|
Title:
|
METHOD FOR ACHIEVING INCREASED CONTROL OVER INTERCONNECT LINE THICKNESS ACROSS A WAFER AND BETWEEN WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
|
Application #:
|
11003528
|
Filing Dt:
|
12/03/2004
|
|
Title:
|
HIGH-VOLTAGE TRANSISTOR HAVING A U-SHAPED GATE AND METHOD FOR FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/02/2010
|
Application #:
|
11006034
|
Filing Dt:
|
12/07/2004
|
|
Title:
|
INPUT OF TEST CONDITIONS AND OUTPUT GENERATION FOR BUILT-IN SELF TEST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
|
Application #:
|
11006934
|
Filing Dt:
|
12/07/2004
|
|
Title:
|
METHOD AND APPARATUS FOR USING EMPTY TIME SLOTS FOR SPREAD SPECTRUM ENCODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/2010
|
Application #:
|
11006998
|
Filing Dt:
|
12/07/2004
|
|
Title:
|
METHOD AND APPARATUS FOR TUNING A RADIO RECEIVER WITH A RADIO TRANSMITTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/2009
|
Application #:
|
11007072
|
Filing Dt:
|
12/07/2004
|
|
Title:
|
METHOD AND APPARATUS FOR BINDING PERIPHERAL DEVICES TO A COMPUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/29/2008
|
Application #:
|
11008233
|
Filing Dt:
|
12/10/2004
|
|
Title:
|
MEMORY CELL HAVING ENHANCED HIGH-K DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/06/2009
|
Application #:
|
11015105
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Filing Dt:
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12/17/2004
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Title:
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STAGED CORRELATOR
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Patent #:
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Issue Dt:
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10/10/2006
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Application #:
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11021394
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Filing Dt:
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12/23/2004
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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NON-VOLATILE COUNTER
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Patent #:
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Issue Dt:
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07/08/2008
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Application #:
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11023914
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Filing Dt:
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12/28/2004
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Title:
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CURRENT SENSING ARCHITECTURE FOR HIGH BITLINE VOLTAGE, RAIL TO RAIL OUTPUT SWING AND VCC NOISE CANCELLATION
|
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|
|
|
Patent #:
|
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Issue Dt:
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12/25/2007
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Application #:
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11024257
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Filing Dt:
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12/28/2004
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Publication #:
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Pub Dt:
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06/29/2006
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Title:
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SENSE AMPLIFIERS WITH HIGH VOLTAGE SWING
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Patent #:
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Issue Dt:
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09/07/2010
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Application #:
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11024843
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Filing Dt:
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12/30/2004
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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MEMORY CONTROL CIRCUIT AND MICROPROCESSORY SYSTEM FOR PRE-FETCHING INSTRUCTIONS
|
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|
|
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Patent #:
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Issue Dt:
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02/28/2012
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Application #:
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11033588
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Filing Dt:
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01/12/2005
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Publication #:
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Pub Dt:
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07/13/2006
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Title:
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MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD OF FABRICATING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
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10/31/2006
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Application #:
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11034642
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Filing Dt:
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01/13/2005
|
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Publication #:
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Pub Dt:
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07/13/2006
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Title:
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MULTI-LEVEL ONO FLASH PROGRAM ALGORITHM FOR THRESHOLD WIDTH CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
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Application #:
|
11035055
|
Filing Dt:
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01/14/2005
|
|
Publication #:
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Pub Dt:
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01/05/2006
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Title:
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A SEMICONDUCTOR DEVICE HAVING AN ARITHMETIC UNIT OF A RECONFIGURABLE CIRCUIT CONFIGURATION IN ACCORDANCE WITH STORED CONFIGURATION DATA AND A MEMORY STORING FIXED VALUE DATA TO BE SUPPLIED TO THE ARITHMETIC UNIT, REQUIRING NO DATA AREA FOR STORING FIXED VALUE DATA TO BE SET IN A CONFIGURATION MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
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Application #:
|
11035188
|
Filing Dt:
|
01/13/2005
|
|
Title:
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METHOD FOR CONTROLLING POLY 1 THICKNESS AND UNIFORMITY IN A MEMORY ARRAY FABRICATION PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2012
|
Application #:
|
11036332
|
Filing Dt:
|
01/18/2005
|
|
Publication #:
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|
Pub Dt:
|
09/29/2005
| | | | |
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Title:
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MICROCOMPUTER WITH INTERNAL DMA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11036395
|
Filing Dt:
|
01/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2005
| | | | |
|
Title:
|
MICROCOMPUTER CAPABLE OF MONITORING INTERNAL MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2007
|
Application #:
|
11041608
|
Filing Dt:
|
01/24/2005
|
|
Publication #:
|
|
Pub Dt:
|
07/27/2006
| | | | |
|
Title:
|
AUTOMATED TESTS FOR BUILT-IN SELF TEST
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2011
|
Application #:
|
11049855
|
Filing Dt:
|
02/04/2005
|
|
Title:
|
NON-VOLATILE MEMORY DEVICE WITH IMPROVED ERASE SPEED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/27/2008
|
Application #:
|
11052688
|
Filing Dt:
|
02/07/2005
|
|
Publication #:
|
|
Pub Dt:
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08/10/2006
| | | | |
|
Title:
|
MEMORY ELEMENT USING ACTIVE LAYER OF BLENDED MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/2010
|
Application #:
|
11059139
|
Filing Dt:
|
02/15/2005
|
|
Title:
|
MULTIPLE DUAL BIT MEMORY INTEGRATED CIRCUIT SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/16/2006
|
Application #:
|
11061119
|
Filing Dt:
|
02/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
|
Title:
|
CURRENT-VOLTAGE CONVERTER CIRCUIT AND ITS CONTROL METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2006
|
Application #:
|
11061307
|
Filing Dt:
|
02/18/2005
|
|
Publication #:
|
|
Pub Dt:
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08/25/2005
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY STORAGE DEVICE AND A REDUNDANCY CONTROL METHOD THEREFOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2006
|
Application #:
|
11061365
|
Filing Dt:
|
02/18/2005
|
|
Publication #:
|
|
Pub Dt:
|
08/25/2005
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY STORAGE DEVICE AND ITS REDUNDANT METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/22/2008
|
Application #:
|
11062629
|
Filing Dt:
|
02/23/2005
|
|
Title:
|
SYSTEM AND METHOD FOR GATE FORMATION IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/23/2007
|
Application #:
|
11062641
|
Filing Dt:
|
02/23/2005
|
|
Title:
|
SYSTEM AND METHOD FOR ERASING A MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2008
|
Application #:
|
11063975
|
Filing Dt:
|
02/24/2005
|
|
Publication #:
|
|
Pub Dt:
|
05/18/2006
| | | | |
|
Title:
|
RESET CONTROL CIRCUIT AND RESET CONTROL METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/2010
|
Application #:
|
11069500
|
Filing Dt:
|
03/01/2005
|
|
Title:
|
WIRELESS HUMAN INTERFACE DEVICE PACKET COMPRESSION SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/2010
|
Application #:
|
11075999
|
Filing Dt:
|
03/08/2005
|
|
Title:
|
METHOD FOR CONTAINING A SILICIDED GATE WITHIN A SIDEWALL SPACER IN INTEGRATED CIRCUIT TECHNOLOGY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2006
|
Application #:
|
11076252
|
Filing Dt:
|
03/08/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
|
Title:
|
DECODER FOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2012
|
Application #:
|
11078873
|
Filing Dt:
|
03/11/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/14/2006
| | | | |
|
Title:
|
MEMORY DEVICE WITH IMPROVED SWITCHING SPEED AND DATA RETENTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2006
|
Application #:
|
11082526
|
Filing Dt:
|
03/17/2005
|
|
Publication #:
|
|
Pub Dt:
|
06/29/2006
| | | | |
|
Title:
|
COUNTING SCHEME WITH AUTOMATIC POINT-OF-REFERENCE GENERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11083534
|
Filing Dt:
|
03/18/2005
|
|
Title:
|
METHOD AND APPARATUS FOR USING VALID BITS FOR ERASURE CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/05/2006
|
Application #:
|
11086884
|
Filing Dt:
|
03/22/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
|
Title:
|
TEMPERATURE COMPENSATION OF THIN FILM DIODE VOLTAGE THRESHOLD IN MEMORY SENSING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
11087944
|
Filing Dt:
|
03/23/2005
|
|
Title:
|
CURRENT SENSING CIRCUIT WITH A CURRENT-COMPENSATED DRAIN VOLTAGE REGULATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/11/2007
|
Application #:
|
11089707
|
Filing Dt:
|
03/25/2005
|
|
Title:
|
MEMORY DEVICE WITH IMPROVED DATA RETENTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/2010
|
Application #:
|
11089708
|
Filing Dt:
|
03/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/28/2006
| | | | |
|
Title:
|
MEMORY DEVICE WITH IMPROVED DATA RETENTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/29/2008
|
Application #:
|
11089732
|
Filing Dt:
|
03/25/2005
|
|
Title:
|
INCREASING SELF-ALIGNED CONTACT AREAS IN INTEGRATED CIRCUITS USING A DISPOSABLE SPACER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2007
|
Application #:
|
11090716
|
Filing Dt:
|
03/25/2005
|
|
Publication #:
|
|
Pub Dt:
|
09/29/2005
| | | | |
|
Title:
|
SEMICONDUCTOR DEVICE AND METHOD FOR WRITING DATA INTO THE SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/20/2011
|
Application #:
|
11091519
|
Filing Dt:
|
03/29/2005
|
|
Title:
|
ULTRAVIOLET RADIATION BLOCKING INTERLAYER DIELECTRIC
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/19/2011
|
Application #:
|
11091524
|
Filing Dt:
|
03/29/2005
|
|
Title:
|
FILM STACKS TO PREVENT UV-INDUCED DEVICE DAMAGE
|
|
