|
|
Patent #:
|
|
Issue Dt:
|
03/14/2000
|
Application #:
|
08874389
|
Filing Dt:
|
06/13/1997
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Title:
|
METHOD OF FABRICATING INTEGRATED CIRCUIT WIRING WITH LOW RC TIME DELAY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08874496
|
Filing Dt:
|
06/13/1997
|
Title:
|
VARIABLE LOADING APPARATUS FOR OUTPUT LOADING OF INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
08874602
|
Filing Dt:
|
06/13/1997
|
Title:
|
AUTOMATED LOAD DETERMINATION FOR PARTITIONED SIMULATION
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08877066
|
Filing Dt:
|
06/17/1997
|
Title:
|
SINGLE-CELL REFERENCE SIGNAL GENERATING CIRCUIT FOR READING NONVOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
08877527
|
Filing Dt:
|
06/16/1997
|
Title:
|
METHOD OF ETCHING THERMALLY GROWN OXIDE SUBSTANTIALLY SELECTIVELY RELATIVE TO DEPOSITED OXIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/1999
|
Application #:
|
08877613
|
Filing Dt:
|
06/17/1997
|
Title:
|
TREATMENT OF A SURFACE HAVING AN EXPOSE SILICON./SILICA INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08877788
|
Filing Dt:
|
06/18/1997
|
Title:
|
METHOD FOR ETCHING NITRIDE FEATURES IN INTEGRATED CIRCUIT CONSTRUCTION
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/1998
|
Application #:
|
08877921
|
Filing Dt:
|
06/18/1997
|
Title:
|
CIRCUIT AND METHOD FOR GENERATING A READ REFERENCE SIGNAL FOR NONVOLATILE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08877922
|
Filing Dt:
|
06/18/1997
|
Title:
|
READ CIRCUIT AND METHOD FOR NONVOLATILE MEMORY CELLS WITH AN EQUALIZING STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08877927
|
Filing Dt:
|
06/18/1997
|
Title:
|
LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY DEVICE WITH VOLTAGE BOOSTING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08878657
|
Filing Dt:
|
06/19/1997
|
Title:
|
VARIABLE VOLTAGE ISOLATION GATE AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08878752
|
Filing Dt:
|
06/19/1997
|
Title:
|
MEMORY DEVICE HAVING TWO OR MORE MEMORY ARRAYS AND A TESTPATH CONNECTED TO ONE OF THE MEMORY ARRAYS AND NOT OPERABLY CONNECTED TO ANOTHER MEMORY ARRAY, AND A METHOD OF OPERATING THE TESTPATH
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
08878935
|
Filing Dt:
|
06/19/1997
|
Title:
|
PLASTIC LEAD FRAMES FOR SEMICONDUCTOR DEVICES, PACKAGES INCLUDING SAME, AND METHODS OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
08879017
|
Filing Dt:
|
06/18/1997
|
Title:
|
METHOD AND CIRCUIT FOR READING LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
08879400
|
Filing Dt:
|
06/20/1997
|
Title:
|
COMPUTER SYSTEM CAPABLE OF SYMMETRICAL PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
08879409
|
Filing Dt:
|
06/20/1997
|
Title:
|
METHOD AND APPARATUS FOR COMPRESSED DATA TESTING OF MORE THAN ONE MEMORY ARRAY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08879833
|
Filing Dt:
|
06/19/1997
|
Title:
|
METHOD AND APPARATUS FOR TESTING OF DIELECTRIC DEFECTS IN A PACKAGED SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08879983
|
Filing Dt:
|
06/20/1997
|
Title:
|
LOW CURRENT REDUNDANCY ANTI-FUSE ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
08880085
|
Filing Dt:
|
06/20/1997
|
Title:
|
METHOD FOR SYMMETRICALLY PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/14/1999
|
Application #:
|
08880251
|
Filing Dt:
|
06/23/1997
|
Title:
|
METHOD OF CHECKING DATA INTEGRITY FOR A RAID 1 SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08880275
|
Filing Dt:
|
06/23/1997
|
Title:
|
PROCESS OF FORMING TITANIUM SILICIDE INTERCONNECTS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08880350
|
Filing Dt:
|
06/23/1997
|
Title:
|
A SYSTEM AND METHOD FOR PROVIDING A FAST AND EFFICIENT COMPARISON OF CYCLIC REDUNDANCY CHECK (CRC/CHECK SUM) VALUES OF TWO MIRRORED DISKS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
08880351
|
Filing Dt:
|
06/23/1997
|
Title:
|
METHOD FOR TESTING A CONTROLLER WITH RANDOM CONSTRAINTS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
08880356
|
Filing Dt:
|
06/23/1997
|
Title:
|
PROCESSING METHODS OF FORMING A CAPACITOR
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/2000
|
Application #:
|
08880840
|
Filing Dt:
|
06/23/1997
|
Title:
|
METHOD FOR MOUNTING AN ELEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
03/27/2001
|
Application #:
|
08881519
|
Filing Dt:
|
06/24/1997
|
Title:
|
METHOD FOR FORMING A DIELECTRIC
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/1998
|
Application #:
|
08881716
|
Filing Dt:
|
06/23/1997
|
Title:
|
APPARATUS FOR TESTING A CONTROLLER WITH RANDOM CONTRAINTS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08881737
|
Filing Dt:
|
06/24/1997
|
Title:
|
METHOD OF MAKING SEMICONDUCTOR DEVICE INCORPORATING AN ELECTRICAL CONTACT TO AN INTERMAL CONDUCTIVE LAYER
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08883027
|
Filing Dt:
|
06/26/1997
|
Title:
|
METHOD OF SPUTTER DEPOSITION OF METALS ONTO SUBSTRATES AND METHOD OF FORMING PLASMA
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08883181
|
Filing Dt:
|
06/26/1997
|
Title:
|
CIRCUIT AND METHOD TO PREVENT INADVERTENT TEST MODE ENTRY
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08883822
|
Filing Dt:
|
06/27/1997
|
Title:
|
CLOCK CIRCUIT FOR READING A MUTILEVEL NON VOLATILE MEMORY CELLS DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08884902
|
Filing Dt:
|
06/30/1997
|
Title:
|
PACKAGING FOR BARE DICE EMPLOYING EMR-SENSITIVE ADHESIVES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08885060
|
Filing Dt:
|
06/30/1997
|
Title:
|
A METHOD FOR FORMING A CAPACITOR, THE FIRST CAPACITOR PLATE OF THE CAPACITOR INCLUDING ELECTRICALLY COUPLED FIRST AND SECOND CONDUCTIVE LAYERS SEPARATED BY AN INTERVENING INSULATIVE LAYER, WHEREIN THE FIRST AND SECOND CONDUCTIVE LAYERS CONSTITUTE DIFFERENT MATERIALS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
08885127
|
Filing Dt:
|
06/30/1997
|
Title:
|
TRAY FOR PROCESSING AND/OR SHIPPING INTEGRATED CIRCUIT DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/1999
|
Application #:
|
08885535
|
Filing Dt:
|
06/30/1997
|
Title:
|
METHOD AND APPARATUS FOR SIMULTANEOUS MEMORY SUBARRAY TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/2000
|
Application #:
|
08885803
|
Filing Dt:
|
06/30/1997
|
Title:
|
SCALABLE RECEIVER STRUCTURE FOR EFFICIENT BIT SEQUENCE DECODING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
08886384
|
Filing Dt:
|
07/01/1997
|
Title:
|
FIELD EFFECT TRANSISTOR ASSEMBLIES AND TRANSISTOR GATE BLOCK STACKS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
08886529
|
Filing Dt:
|
07/02/1997
|
Title:
|
POSITIONER FOR OVERHANGING COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
08886707
|
Filing Dt:
|
07/01/1997
|
Title:
|
METHOD FOR FORMING A SEMICONDUCTOR BURIED CONTACT WITH A REMOVABLE SPACER
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
08887381
|
Filing Dt:
|
07/02/1997
|
Title:
|
VARIED-THICKNESS HEAT SINK FOR INTEGRATED CIRCUIT (IC) PACKAGES AND METHOD OF FABRICATING IC PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
08887547
|
Filing Dt:
|
07/03/1997
|
Title:
|
METHOD FOR IMPROVING A STEPPER SIGNAL IN A PLANARIZED SURFACE OVER ALIGNMENT TOPOGRAPHY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08887687
|
Filing Dt:
|
07/03/1997
|
Title:
|
INTERLOCKING CONDUCTIVE PLUG FOR USE WITH AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08887801
|
Filing Dt:
|
07/03/1997
|
Title:
|
SEMICONDUCTOR CIRCUIT INTERCONNECTIONS AND METHODS OF MAKING SUCH INTERCONNECTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/2001
|
Application #:
|
08887915
|
Filing Dt:
|
07/02/1997
|
Title:
|
A ROUGH ELECTRODE (HIGH SURFACE AREA) FROM TI AND TIN
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/2000
|
Application #:
|
08888075
|
Filing Dt:
|
07/03/1997
|
Title:
|
CARRIER AND SYSTEM FOR TESTING BUMPED SEMICONDUCTOR COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/1999
|
Application #:
|
08888336
|
Filing Dt:
|
07/02/1997
|
Title:
|
LEAD FRAME ASSEMBLIES WITH VOLTAGE REFERENCE PLANE AND IC PACKAGES INCLUDING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
08888501
|
Filing Dt:
|
07/07/1997
|
Title:
|
SYSTEM AND METHOD FOR INVALIDATING CACHE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/1998
|
Application #:
|
08888857
|
Filing Dt:
|
07/07/1997
|
Title:
|
METHOD AND APPARATUS FOR LEAK CHECKING UNPACKAGED SEMICONDUCTOR DICE
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08888994
|
Filing Dt:
|
07/07/1997
|
Title:
|
WAFER PROCESSING APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2001
|
Application #:
|
08889395
|
Filing Dt:
|
07/08/1997
|
Title:
|
SEMICONDUCTOR-ON-INSULATOR MEMORY CELL WITH BURIED WORD AND BODY LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
08889396
|
Filing Dt:
|
07/08/1997
|
Title:
|
METHOD OF MAKING MEMORY CELL WITH VERTICAL TRANSISTOR AND BURIED WORD AND BODY LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
08889462
|
Filing Dt:
|
07/08/1997
|
Title:
|
MEMORY CELL HAVING A VERTICAL TRANSISTOR WITH BURIED SOURCE/DRAIN AND DUAL GATES
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
08889463
|
Filing Dt:
|
07/08/1997
|
Title:
|
FOUR F2 FOLDED BIT LINE DRAM CELL STRUCTURE HAVING BURIED BIT AND WORD LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
08889535
|
Filing Dt:
|
07/08/1997
|
Title:
|
METHOD FOR TESTING INTERCONNECTS AND SEMICONDUCTOR DICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08889553
|
Filing Dt:
|
07/08/1997
|
Title:
|
YIGH DENSITY FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
08889554
|
Filing Dt:
|
07/08/1997
|
Title:
|
ULTRA HIGH DENSITY FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08889653
|
Filing Dt:
|
07/08/1997
|
Title:
|
LOW NOISE OUTPUT BUFFER FOR SEMICONDUCTOR ELECTRONIC CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
08890257
|
Filing Dt:
|
07/09/1997
|
Title:
|
METHOD AND APPARATUS FOR ENABLING REDUNDANT MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
08890368
|
Filing Dt:
|
07/14/1997
|
Title:
|
TREATMENT OF A SURFACE HAVING AN EXPOSED SILICON/SILICA INTERFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08890414
|
Filing Dt:
|
07/09/1997
|
Title:
|
PACKAGE STACK VIA BOTTOM LEADED PLASTIC (BLP) PACKAGING
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
08891097
|
Filing Dt:
|
07/10/1997
|
Title:
|
METHOD AND APPARATUS FOR COLLISION-FREE DATA TRANSFERS IN A MEMORY DEVICE WITH SELECTABLE DATA OR ADDRESS PATHS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
08891279
|
Filing Dt:
|
07/10/1997
|
Title:
|
ENCAPSULANT DAM STANDOFF FOR SHELL-ENCLOSED DIE ASSEMBLIES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
08891669
|
Filing Dt:
|
07/10/1997
|
Title:
|
CIRCUIT FOR PROGRAMMING ANTIFUSE BITS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/20/2000
|
Application #:
|
08892114
|
Filing Dt:
|
07/14/1997
|
Title:
|
A METHOD OF FORMING FOAMED POLYMERIC MATERIAL FOR AN INTEGRATED CIRCUIT
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08892605
|
Filing Dt:
|
07/14/1997
|
Title:
|
CIRCUIT AND METHOD FOR ANTIFUSE STRESS TEST
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08892718
|
Filing Dt:
|
07/15/1997
|
Title:
|
ALUMINUM-CONTAINING FILMS DERIVED FROM USING HYDROGEN AND OXYGEN GAS IN SPUTTTER DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
08892930
|
Filing Dt:
|
07/15/1997
|
Title:
|
METHOD OF USING HYDROGEN GAS IN SPUTTER DEPOSITION OF ALUMINUM-CONTAINING FILMS AND ALUMINUM-CONTAINING FILMS DERIVED THEREFROM
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/1998
|
Application #:
|
08893931
|
Filing Dt:
|
07/14/1997
|
Title:
|
A PROCESS FOR FORMING CAPACITOR ARRAY STRUCTURE FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08893938
|
Filing Dt:
|
07/15/1997
|
Title:
|
MOBILE STATION LOCATING SYSTEM AND METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/16/1999
|
Application #:
|
08895620
|
Filing Dt:
|
07/17/1997
|
Title:
|
FOCUS SPOT DETECTION METHOD AND SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
08896490
|
Filing Dt:
|
07/18/1997
|
Publication #:
|
|
Pub Dt:
|
08/16/2001
| | | | |
Title:
|
LOW CURRENT REDUNDANCY ANTI -FUSE APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
12/08/1998
|
Application #:
|
08896701
|
Filing Dt:
|
07/18/1997
|
Title:
|
LOW CURRENCY REDUNDANCY ANTI-FUSE METHOD AND APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
08896702
|
Filing Dt:
|
07/18/1997
|
Title:
|
LOW CURRENT REDUNDANCY ANTI-FUSE METHOD AND APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
08896936
|
Filing Dt:
|
07/18/1997
|
Title:
|
DYNAMIC BUFFER ALLOCATION FOR A COMPUTER SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
08896938
|
Filing Dt:
|
07/18/1997
|
Title:
|
SYSTEM FOR DYNAMIC BUFFER ALLOCATION COMPRISING CONTROL LOGIC FOR CONTROLLING A FIRST ADDRESS BUFFER AND A FIRST DATA BUFFER AS A MATCHED PAIR
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/1999
|
Application #:
|
08897364
|
Filing Dt:
|
07/22/1997
|
Title:
|
FABRICATION OF SEMICONDUCTOR STRUCTURES BY ION IMPLANTATION
|
|
|
Patent #:
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|
Issue Dt:
|
09/28/1999
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Application #:
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08897492
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Filing Dt:
|
07/21/1997
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Title:
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CHARGE-PUMPING TO INCREASE ELECTRON COLLECTION EFFICIENCY
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Patent #:
|
|
Issue Dt:
|
11/02/1999
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Application #:
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08897799
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Filing Dt:
|
07/21/1997
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Title:
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PROCESS FOR MANUFACTURING AN INTEGRATED CIRCUIT COMPRISING AN ARRAY OF MEMORY CELLS
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Patent #:
|
|
Issue Dt:
|
09/07/1999
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Application #:
|
08898099
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Filing Dt:
|
07/22/1997
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Title:
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LAMINATED FILM/METAL STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
08/15/2000
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Application #:
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08898155
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Filing Dt:
|
07/22/1997
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Title:
|
METHOD FOR IMPROVING THE INTERMEDIATE DIELECTRIC PROFILE, PARTICULARLY FOR NON-VOLATILE MEMORIES
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|
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Patent #:
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|
Issue Dt:
|
11/09/1999
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Application #:
|
08898177
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Filing Dt:
|
07/22/1997
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Title:
|
OUTPUT BUFFER HAVING INHERENTLY PRECISE DATA MASKING
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Patent #:
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|
Issue Dt:
|
06/05/2001
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Application #:
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08898527
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Filing Dt:
|
07/22/1997
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Title:
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RESISTOR CONSTRUCTIONS
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|
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Patent #:
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|
Issue Dt:
|
08/03/1999
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Application #:
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08898530
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Filing Dt:
|
07/22/1997
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Title:
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INTEGRATED CIRCUITRY HAVING A PAIR OF ADJACENT CONDUCTIVE LINES AND METHOD OF FORMING
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|
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Patent #:
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|
Issue Dt:
|
12/07/1999
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Application #:
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08898532
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Filing Dt:
|
07/22/1997
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Title:
|
METHODS OF MAKING A SRAM CELL EMPLOYING SUBSTANTIALLY VERTICALLY ELONGATED PULL-UP RESISTORS AND METHODS OF MAKING RESISTOR CONSTRUCTIONS
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|
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Patent #:
|
|
Issue Dt:
|
11/21/2000
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Application #:
|
08898811
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Filing Dt:
|
07/23/1997
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Title:
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HIGH VOLTAGE TOLERANCE OUTPUT STAGE
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|
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Patent #:
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|
Issue Dt:
|
07/13/1999
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Application #:
|
08898812
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Filing Dt:
|
07/23/1997
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Title:
|
BALL GRID ARRY (BGA) ENCAPSULATION MOLD
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|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
08899228
|
Filing Dt:
|
07/23/1997
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Title:
|
OUTPUT STAGE FOR A MEMORY DEVICE AND FOR LOW VOLTAGE APPLICATIONS
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|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
08899524
|
Filing Dt:
|
07/24/1997
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Title:
|
SENSE AMPLIFIER FOR COMPLEMENT OR NO-COMPLEMENTARY DATA SIGNALS
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|
|
Patent #:
|
|
Issue Dt:
|
09/15/1998
|
Application #:
|
08899525
|
Filing Dt:
|
07/24/1997
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Title:
|
METHOD AND APPARATUS FOR READING COMPRESSED TEST DATA FROM MEMORY DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
01/11/2000
|
Application #:
|
08899729
|
Filing Dt:
|
07/24/1997
|
Title:
|
APPARATUS FOR ATTACHING ADHESIVE TAPE TO LEAD-ON-CHIP LEADFRAMES
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|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
08900165
|
Filing Dt:
|
07/28/1997
|
Title:
|
BIDIRECTIONAL CHARGE PUMP GENERATING EITHER A POSITIVE OR NEGATIVE VOLTAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
08900424
|
Filing Dt:
|
07/25/1997
|
Title:
|
ASYMMETRICAL PULSIVE DELAY NETWORK
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|
|
Patent #:
|
|
Issue Dt:
|
04/13/1999
|
Application #:
|
08901601
|
Filing Dt:
|
07/28/1997
|
Title:
|
METHOD AND APPARATUS FOR CONTINUOUS PROCESSING OF SEMICONDUCTOR WAFERS
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|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
08901921
|
Filing Dt:
|
07/28/1997
|
Title:
|
ROTATING SYSTEM AND METHOD FOR ELECTRODEPOSITING MATERIALS ON SEMICONDUCTOR WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08902004
|
Filing Dt:
|
07/29/1997
|
Title:
|
SRAM CELL EMPLOYING SUBSTANTIALLY VERTICALLY ELONGATED PULL-UP RESISTORS AND METHODS OF MAKING, AND RESISTOR CONSTRUCTIONS AND METHODS OF MAKING
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
08902098
|
Filing Dt:
|
07/29/1997
|
Title:
|
DEAPROM AND TRANSISTOR WITH GALLIUM NITRIDE OR GALLIIUM ALUMINIUM NITRIDE GATE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/2006
|
Application #:
|
08902133
|
Filing Dt:
|
07/29/1997
|
Title:
|
MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
08902470
|
Filing Dt:
|
07/29/1997
|
Title:
|
METHOD AND APPARATUS PROVIDING REDUNDANCY FOR FABRICATING HIGHLY RELIABLE MEMORY MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/1998
|
Application #:
|
08903198
|
Filing Dt:
|
07/15/1997
|
Title:
|
INTEGRATED CIRCUITRY WITH INTERCONNECTION PILLAR
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08903222
|
Filing Dt:
|
07/22/1997
|
Title:
|
ARTICLE TRANSFER METHODS
|
|