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03/22/2012
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03/22/2012
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03/22/2012
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03/22/2012
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03/22/2012
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03/29/2012
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03/29/2012
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06/06/2013
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09/30/2014
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03/29/2012
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03/29/2012
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03/29/2012
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12/05/2011
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03/29/2012
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12/05/2011
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03/29/2012
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10/23/2012
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12/06/2011
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03/29/2012
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09/16/2014
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12/06/2011
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03/29/2012
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05/07/2013
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12/06/2011
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02/04/2014
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12/06/2011
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03/29/2012
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02/05/2013
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12/06/2011
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05/10/2012
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SEMICONDUCTOR DEVICE COMPRISING TRANSISTOR STRUCTURES AND METHODS FOR FORMING SAME
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11/20/2012
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12/07/2011
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03/29/2012
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09/11/2012
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12/07/2011
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03/29/2012
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12/24/2013
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12/07/2011
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06/13/2013
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10/02/2012
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12/08/2011
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04/05/2012
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03/04/2014
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13315337
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12/09/2011
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04/05/2012
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10/20/2015
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12/09/2011
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04/05/2012
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06/26/2012
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12/09/2011
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04/05/2012
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08/05/2014
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12/09/2011
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06/13/2013
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01/28/2014
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12/09/2011
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06/13/2013
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MEMORY CELLS HAVING A PLURALITY OF HEATERS
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12/23/2014
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12/09/2011
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06/13/2013
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SLEW RATE MODULATION
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02/05/2013
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12/09/2011
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04/05/2012
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04/30/2013
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12/09/2011
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04/05/2012
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03/12/2013
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12/12/2011
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04/05/2012
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MEMORY FOR ACCESSING MULTIPLE SECTORS OF INFORMATION SUBSTANTIALLY CONCURRENTLY
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09/17/2013
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12/12/2011
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05/03/2012
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03/19/2013
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12/12/2011
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04/12/2012
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10/21/2014
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12/12/2011
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04/05/2012
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05/21/2013
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12/12/2011
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04/05/2012
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01/28/2014
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12/13/2011
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06/13/2013
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06/04/2013
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12/13/2011
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04/05/2012
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05/21/2013
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12/13/2011
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04/05/2012
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CROSSLINKABLE GRAFT POLYMER NON-PREFERENTIALLY WETTED BY POLYSTYRENE AND POLYETHYLENE OXIDE
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06/10/2014
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12/13/2011
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04/12/2012
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11/04/2014
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12/13/2011
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06/13/2013
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10/07/2014
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12/14/2011
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06/20/2013
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05/13/2014
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12/15/2011
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06/20/2013
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WIRING CONFIGURATION OF A BUS SYSTEM AND POWER WIRES IN A MEMORY CHIP
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06/11/2013
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12/15/2011
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06/20/2013
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02/11/2014
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12/15/2011
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06/20/2013
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COUNTER OPERATION IN A STATE MACHINE LATTICE
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11/26/2013
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12/15/2011
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06/20/2013
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07/15/2014
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12/15/2011
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06/20/2013
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09/13/2016
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12/15/2011
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06/20/2013
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03/25/2014
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12/15/2011
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06/20/2013
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05/06/2014
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12/15/2011
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06/20/2013
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02/12/2013
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12/19/2011
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04/19/2012
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VERTICAL TRANSISTORS
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01/29/2013
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12/19/2011
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04/12/2012
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05/14/2013
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12/19/2011
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04/12/2012
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03/05/2013
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12/19/2011
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04/19/2012
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METHOD AND APPARATUS FOR IMAGE NOISE REDUCTION USING NOISE MODELS
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06/10/2014
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13330973
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12/20/2011
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Pub Dt:
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04/12/2012
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Title:
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Methods of Forming Patterns in Semiconductor Constructions, Methods of Forming Container Capacitors, and Methods of Forming Reticles Configured for Imprint Lithography
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06/11/2013
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13331185
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12/20/2011
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04/19/2012
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Title:
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MEMORY ERASE METHODS AND DEVICES
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06/11/2013
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13331932
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Filing Dt:
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12/20/2011
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Pub Dt:
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04/19/2012
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Title:
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COMMAND LATENCY SYSTEMS AND METHODS
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06/18/2013
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13332222
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12/20/2011
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Pub Dt:
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04/19/2012
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Title:
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HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC
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06/02/2015
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13332553
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12/21/2011
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04/19/2012
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Title:
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METHODS, APPARATUS, AND SYSTEMS TO REPAIR MEMORY
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02/03/2015
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13332816
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12/21/2011
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Pub Dt:
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06/27/2013
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Title:
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Methods Of Forming Capacitors
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07/02/2013
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13333245
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12/21/2011
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Pub Dt:
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04/19/2012
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Title:
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METHOD OF FORMING AN IMAGING DEVICE
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11/12/2013
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13333822
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12/21/2011
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Pub Dt:
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06/27/2013
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Title:
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SYSTEMS, CIRCUITS, AND METHODS FOR CHARGE SHARING
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08/27/2013
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13333850
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12/21/2011
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06/27/2013
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Title:
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METHODS, APPARATUSES, AND CIRCUITS FOR BIMODAL DISABLE CIRCUITS
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07/21/2015
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13334339
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12/22/2011
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Pub Dt:
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04/19/2012
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Title:
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TWO-PART PROGRAMMING METHODS
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03/11/2014
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13335107
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12/22/2011
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Pub Dt:
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05/31/2012
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Title:
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SEMICONDUCTOR STRUCTURES INCLUDING POLYMER MATERIAL PERMEATED WITH METAL OXIDE
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03/24/2015
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13335291
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12/22/2011
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06/27/2013
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Title:
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Apparatus and Methods of Programming Memory Cells using Adjustable Charge State Level(s)
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08/05/2014
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13335309
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12/22/2011
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Pub Dt:
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06/27/2013
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Title:
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METHODS AND APPARATUSES FOR DETERMINING THRESHOLD VOLTAGE SHIFT
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12/08/2015
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13335619
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12/22/2011
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Pub Dt:
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04/19/2012
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Title:
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PASS-THROUGH 3D INTERCONNECT FOR MICROELECTRONIC DIES AND ASSOCIATED SYSTEMS AND METHODS
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07/29/2014
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13335814
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12/22/2011
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Pub Dt:
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06/27/2013
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Title:
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APPARATUSES AND METHODS INCLUDING MEMORY WITH TOP AND BOTTOM DATA LINES
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08/06/2013
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13336516
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12/23/2011
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05/03/2012
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Title:
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METHOD OF MANUFACTURING DEVICES HAVING VERTICAL JUNCTION EDGE
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02/25/2014
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13336805
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12/23/2011
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Pub Dt:
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04/19/2012
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Title:
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TECHNIQUES FOR READING A MEMORY CELL WITH ELECTRICALLY FLOATING BODY TRANSISTOR
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04/02/2013
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13337567
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12/27/2011
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04/19/2012
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Title:
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Registered Structure Formation via the Application of Directed Thermal Energy to Diblock Copolymer Films
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03/25/2014
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13337810
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12/27/2011
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06/27/2013
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Title:
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VERTICAL TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING SAME
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06/10/2014
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13337943
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12/27/2011
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04/19/2012
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Title:
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MICROELECTRONIC DEVICES AND METHODS FOR FILING VIAS IN MICROELECTRONIC DEVICES
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05/28/2013
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13338484
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12/28/2011
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04/26/2012
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Title:
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METHODS OF FORMING SILICON OXIDES AND METHODS OF FORMING INTERLEVEL DIELECTRICS
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07/30/2013
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13338527
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12/28/2011
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04/26/2012
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Capacitors Including Conductive TiOxNx
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09/10/2013
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13339692
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12/29/2011
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04/26/2012
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Methods of Forming Capacitors
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02/03/2015
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13339721
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12/29/2011
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07/04/2013
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SHARING LOCAL CONTROL LINES ACROSS MULTIPLE PLANES IN A MEMORY DEVICE
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09/15/2015
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13340375
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12/29/2011
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07/04/2013
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Memory Structures and Arrays
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04/16/2013
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13341418
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12/30/2011
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07/19/2012
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SEAMLESS COARSE AND FINE DELAY STRUCTURE FOR HIGH PERFORMANCE DLL
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02/26/2013
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13341512
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12/30/2011
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04/26/2012
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CMOS IMAGER WITH INTEGRATED CIRCUITRY
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03/11/2014
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13342826
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01/03/2012
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06/14/2012
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BOOT BLOCK FEATURES IN SYNCHRONOUS SERIAL INTERFACE NAND
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09/09/2014
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13342844
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01/03/2012
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04/26/2012
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QUANTIZING CIRCUITS WITH VARIABLE PARAMETERS
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07/02/2013
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13342876
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01/03/2012
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04/26/2012
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METHODS AND APPARATUS FOR A STACKED-DIE INTERPOSER
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12/17/2013
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13343023
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01/04/2012
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05/03/2012
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NON-VOLATILE MULTILEVEL MEMORY CELLS
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12/09/2014
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13343087
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01/04/2012
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07/04/2013
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SOURCE/DRAIN ZONES WITH A DELECTRIC PLUG OVER AN ISOLATION REGION BETWEEN ACTIVE REGIONS AND METHODS
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08/16/2016
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13344226
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01/05/2012
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07/11/2013
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SOLID-STATE RADIATION TRANSDUCER DEVICES HAVING AT LEAST PARTIALLY TRANSPARENT BURIED-CONTACT ELEMENTS, AND ASSOCIATED SYSTEMS AND METHODS
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11/06/2012
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13344329
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01/05/2012
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05/03/2012
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METHOD OF FABRICATING DIFFERENT GATE OXIDES FOR DIFFERENT TRANSISTORS IN AN INTEGRATED CIRCUIT
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12/04/2012
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13345379
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01/06/2012
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05/03/2012
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METHOD AND APPARATUS FOR SENDING DATA FROM MULTIPLE SOURCES OVER A COMMUNICATIONS BUS
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11/04/2014
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13345417
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01/06/2012
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04/26/2012
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MULTI-RESISTIVE INTEGRATED CIRCUIT MEMORY
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09/01/2015
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13345422
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01/06/2012
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07/11/2013
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INTEGRATED CIRCUIT CONSTRUCTIONS HAVING THROUGH SUBSTRATE VIAS AND METHODS OF FORMING INTEGRATED CIRCUIT CONSTRUCTIONS HAVING THROUGH SUBSTRATE VIAS
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08/12/2014
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13345446
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01/06/2012
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05/03/2012
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ELECTRONIC DEVICE WITH ASYMMETRIC GATE STRAIN
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07/22/2014
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13345530
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01/06/2012
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05/10/2012
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LOW POWER, HASH-CONTENT ADDRESSABLE MEMORY ARCHITECTURE
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10/16/2012
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13345896
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01/09/2012
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05/03/2012
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PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL
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03/19/2013
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13345984
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01/09/2012
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05/03/2012
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ELECTRONIC APPARATUS CONTAINING LANTHANIDE YTTRIUM ALUMINUM OXIDE
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