|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
09025170
|
Filing Dt:
|
02/18/1998
|
|
Title:
|
FORMING TOOL AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/03/2000
|
Application #:
|
09025388
|
Filing Dt:
|
02/18/1998
|
|
Title:
|
METHOD FOR TERMINATING A PROCESSOR BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09025722
|
Filing Dt:
|
02/18/1998
|
|
Title:
|
DEVICE FOR TERMINATING A PROCESSOR BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
09026235
|
Filing Dt:
|
02/19/1998
|
|
Title:
|
LATERAL BIPOLAR TRANSISTOR AND APPARATUS USING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
09026244
|
Filing Dt:
|
02/19/1998
|
|
Title:
|
DEVICE AND METHOD FOR MARGIN TESTING A SEMICONDUCTOR MEMORY BY APPLYING A STRESSING VOLTAGE SIMULTANEOUSLY TO COMPLEMENTARY AND TRUE DIGIT LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
09026245
|
Filing Dt:
|
02/19/1998
|
|
Title:
|
DEVICE AND METHOD FOR STRESS TESTING A SEMICONDUCTOR MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09026246
|
Filing Dt:
|
02/19/1998
|
|
Title:
|
METHOD AND APPARATUS FOR CONTROLLING THE TEMPERATURE OF A GAS DISTRIBUTION PLATE IN A PROCESS REACTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/27/1999
|
Application #:
|
09026354
|
Filing Dt:
|
02/19/1998
|
|
Title:
|
METHOD FOR FORMING AN INTEGRATED CIRCUIT CONTAINER HAVING PARTIALLY RUGGED SURFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
09026542
|
Filing Dt:
|
02/19/1998
|
|
Title:
|
CONTROLLED REMOVAL OF ELECTRON BEAM CURABLE COATINGS AND ARTICLES FORMED THEREBY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09026566
|
Filing Dt:
|
02/19/1998
|
|
Title:
|
RF POWERED PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION REACTOR AND METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2001
|
Application #:
|
09026584
|
Filing Dt:
|
02/20/1997
|
|
Title:
|
SEMICONDUCTOR CHIP PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09026871
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
DEVICE FOR CLASSIFYING ELECTRONIC COMPONENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/10/2000
|
Application #:
|
09026873
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
METHOD FOR CLASSIFYING ELECTRONIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09026999
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
PACKAGING DIE PREPARATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/22/1999
|
Application #:
|
09027002
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
BUS BAR STRUCTURE ON LEAD FRAME OF SEMICONDUCTOR DEVICE PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/01/2000
|
Application #:
|
09027018
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
SYSTEM FOR CLEANING SEMICONDUCTOR DEVICE PROBE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09027131
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
METHOD OF SORTING COMPUTER CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/11/2000
|
Application #:
|
09027144
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
NON-LOT BASED METHOD FOR ASSEMBLING INTEGRATED CIRCUIT DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
09027343
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
MEMORY DEVICE WITH A MEMORY CELL ARRAY IN TRIPLE WELL, AND RELATED MANUFACTURING PROCESS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09027363
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
METHOD OF FORMING TUNGSTEN NITRIDE COMPRISING LAYERS USING NF3 AS A NITROGEN SOURCE GAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
09027411
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
METHOD AND SYSTEM FOR VERIFYING THE ACCURACY OF STORED DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09027440
|
Filing Dt:
|
02/20/1998
|
|
Title:
|
SORTING SYSTEM FOR COMPUTER CHIPS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
09027537
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
METHOD OF FORMING A LOCAL INTERCONNECTINCLUDING SELECTIVELY ETCHED CONDUCTIVE LAYERS AND RECESS FORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
09027603
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
PROCESS OF FORMING METAL SILICIDE INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/04/2000
|
Application #:
|
09027690
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
UTILIZE ULTRASONIC ENERGY TO REDUCE THE INITIAL CONTACT FORCES IN KNOWN-GOOD-DIE OR PERMANENT CONTACT SYSTEMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
09027845
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
MULTILAYERED LEAD FRAME FOR SEMICONDUCTOR PACKAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09027880
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
PROBE CARD, TEST METHOD AND TEST SYSTEM FOR SEMICONDUCTOR WAFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/2000
|
Application #:
|
09027977
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
PHOTOMASK INSPECTION METHOD AND APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/20/1999
|
Application #:
|
09027978
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
CIRCUITS AND METHODS FOR MULTI-LEVEL DATA THROUGH A SINGLE INPUT/OUTPUT PIN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/2000
|
Application #:
|
09028045
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
SEMICONDUCTOR PROCESSING METHOD OF MAKING ELECTRICAL CONTACT TO A NODE RECEIVED WITHIN A MASS OF INSULATING DIELECTRIC MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/19/2000
|
Application #:
|
09028133
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
DIE PADDLE CLAMPING METHOD FOR WIRE BOND ENHANCEMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
09028209
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
SRAM CELL EMPLOYING SUBSTANTIALLY VERTICALLY ELONGATED PULL-UP RESISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
09028249
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
VERTICAL BIPOLAR READ ACCESS FOR LOW VOLTAGE MEMORY CELL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
09028367
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
PERSONAL INFORMATION DEVICE AND METHOD FOR DOWNLOADING REPROGRAMMING DATA FROM A COMPUTER TO THE PERSONAL INFORMATION DEVICE VIA THE PCMCIA PORT OR THROUGH A DOCKING STATION WITH BAUD RATE CONVERSION MEANS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/29/2003
|
Application #:
|
09028373
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
WRITE REDUCTION IN FLASH MEMORY SYSTEMS THROUGH ECC USAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09028610
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
PLASMA ETCHING METHOD USING LOW IONIZATION POTENTIAL GAS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/09/2001
|
Application #:
|
09028646
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
LOW PROFILE BALL GRID ARRAY PACKAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/25/2000
|
Application #:
|
09028689
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
METHOD OF FORMING AN ELECTRICAL CONTACT TO A SILICON SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09028805
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
CIRCUITS AND METHODS USING VERTICAL COMPLEMENTARY TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09028807
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
VERTICAL GAIN CELL AND ARRAY FOR A DYNAMIC RANDOM ACCESS MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/03/2002
|
Application #:
|
09028876
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
LOW RESISTIVITY TITANIUM SILICIDE STRUCTURES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09028878
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
INSPECTION TECHNIQUE OF PHOTOMASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/29/2000
|
Application #:
|
09028944
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
METHOD AND APPARATUS FOR APPLYING ATOMIZED ADHESIVE TO A LEADFRAME FOR CHIP BONDING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
09028979
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
METHOD FOR PROCESSING WAFERS IN A SEMICONDUCTOR FABRICATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09030047
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
METHOD AND STENCIL FOR EXTRUDING MATERIAL ON A SUBSTRATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09030113
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
METHODS AND STRUCTURES FOR SILVER INTERCONNECTIONS IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09030181
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
SEMICONDUCTOR PROBE CARD HAVING RESISTANCE MEASURING CIRCUITRY AND METHOD FABRICATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
09030188
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
METHODS AND STRUCTURES FOR GOLD INTERCONNECTIONS IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09030498
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY REMAPPING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09030522
|
Filing Dt:
|
02/23/1998
|
|
Title:
|
MEMORY TEST MODE FOR WORDLINE RESISTIVE DEFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/05/1999
|
Application #:
|
09030574
|
Filing Dt:
|
02/24/1998
|
|
Title:
|
ANGULARLY OFFSET STACKED DIE MULTICHIP DEVICE AND METHOD OF MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
09030604
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
VOLTAGE LEVEL SHIFTER DEVICE, PARTICULARY FOR A NONVOLATILE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09030618
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
SEMICONDUCTOR PROCESSING METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
09030697
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
INCREASING THE MEMORY PERFORMANCE OF FLASH MEMORY DEVICES BY WRITING SECTORS SIMULTANEOUSLY TO MULTIPLE FLASH MEMORY DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/18/1999
|
Application #:
|
09030706
|
Filing Dt:
|
02/25/1998
|
|
Title:
|
FERROELECTRIC MEMORY USING FERROELECTRIC REFERENCE CELLS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/12/1999
|
Application #:
|
09031089
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
SEMICONDUCTOR PROCESSING FOR FORMING CAPACITORS BY ETCHING POLYSILICON AND COATING LAYER FORMED OVER THE POLYSILICON
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/13/2000
|
Application #:
|
09031090
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
METHOD OF FORMING OPENINGS AND METHODS OF CONTROLLING THE DEGREE OF TAPER OF OPENINGS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/04/2000
|
Application #:
|
09031095
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
METHODS OF ESTABLISHING ELECTRICAL COMMUNICATION WITH SUBSTRATE NODE LOCATIONS, SEMICONDUCTOR PROCESSING METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY, AND SEMICONDUCTOR ASSEMBLIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09031133
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
METHOD FOR OPERATING AN INPUT DEVICE AND A LAPTOP COMPUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
09031148
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
INTEGRATED CIRCUIT HAVING FORCED SUBSTRATE TEST MODE WITH IMPROVED SUBSTRATE ISOLATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09031149
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
INPUT DEVICE FOR A LAPTOP COMPUTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/09/2002
|
Application #:
|
09031159
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
INTERNAL GUARDBAND FOR SEMICONDUCTOR TESTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
09031397
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
METHOD FOR MULTIPLE PROCESS PARAMETER MATCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09031407
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
FORMING A CONDUCTIVE STRUCTURE IN A SEMICONDUCTOR DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09031411
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
METHOD AND SYSTEM FOR DYNAMIC DURATION BURN-IN
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09031526
|
Filing Dt:
|
02/26/1998
|
|
Publication #:
|
|
Pub Dt:
|
08/09/2001
| | | | |
|
Title:
|
CAPACITOR HAVING TANTALUM OXYNITRIDE FILM AND METHOD FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
09031616
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
DIFFERENTIAL FLASH MEMORY CELL AND METHOD FOR PROGRAMMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/25/2005
|
Application #:
|
09031617
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
MOCVD PROCESS USING OZONE AS A REACTANT TO DEPOSIT A METAL OXIDE BARRIER LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09031620
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
MEMORY CELL WITH VERTICAL TRANSISTOR AND BURIED WORD AND BODY LINES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
09031621
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
PROGRAMMABLE MEMORY ADDRESS DECODE ARRAY WITH VERTICAL TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09031639
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
METHOD FOR OPTIMIZING PRINTING OF AN ALTERNATING PHASE SHIFT MASK HAVING A PHASE SHIFT ERROR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
09031748
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
A READ CIRCUIT FOR MEMORY ADAPTED TO THE MEASUREMENT OF LEAKAGE CURRENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
09031924
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
METHOD AND APPARATUS FOR LIMITING BITLINE CURRENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/28/1999
|
Application #:
|
09031930
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
MULTI-STATE FLASH MEMORY CELL AND METHOD FOR PROGRAMMING SINGLE ELECTRON DIFFERENCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/2000
|
Application #:
|
09031934
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
CIRCUIT AND METHOD FOR MEASURING AND FORCING AN INTERNAL VOLTAGE OF AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
09031939
|
Filing Dt:
|
02/27/1997
|
|
Title:
|
ELECTRICALLY PROGRAMMABLE PHOTOLITHOGRAPHY MASK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2000
|
Application #:
|
09031955
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
METHODS USING ELECTROPHORETICALLY DEPOSITED PATTERNABLE MATERIAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09031960
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
METHODS, STRUCTURES, AND CIRCUITS FOR TRANSISTORS WITH GATE-TO-BODY CAPACITIVE COUPLING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/31/1999
|
Application #:
|
09031972
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
SEGMENTED NON-VOLATILE MEMORY ARRAY HAVING MULTIPLE SOURCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09031975
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
INTEGRATED CIRCUITS USING OPTICAL FIBER INTERCONNECTS FORMED THROUGH A SEMICONDUCTOR WAFER AND METHODS FOR FORMING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/01/2000
|
Application #:
|
09031976
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
THRESHOLD VOLTAGE COMPENSATION CIRCUITS FOR LOW VOLTAGE AND LOW POWER CMOS INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09031984
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
IMPEDANCE MATCHING DEVICE FOR HIGH SPEED MEMORY BUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09032119
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
METHOD AND APPARATUS FOR REMOVING CONTAMINANTS ON ELECTRONIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/26/1999
|
Application #:
|
09032122
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
SEMICONDUCTOR MEMORY BURST LENGTH COUNT DETERMINATION DETECTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/28/2000
|
Application #:
|
09032170
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
INFERRING THE IDENTITY OF A PREFERRED SERVER FROM CONFIGURATION INFORMATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09032181
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
APPARATUS FOR ISOLATING A CONDUCTIVE REGION FROM A SUBSTRATE DURING MANUFACTURE OF AN INTEGRATED CIRCUIT AND CONNECTING THE CONDUCTIVE REGION TO THE SUBSTRATE AFTER MANUFACTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09032189
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
METHOD FOR EFFICIENTLY EXECUTING SOFT PROGRAMMING OF A MEMORY BLOCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09032197
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
METHODS FOR MAKING COPPER AND OTHER METAL INTERCONNECTIONS IN INTEGRATED CIRCUITS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09032229
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
POST-PLANARIZATION, PRE-OXIDE REMOVAL OZONE TREATMENT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
09032230
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
POLISHING PAD REFURBISHER FOR IN SITU, REAL-TIME CONDITIONING AND CLEANING OF A POLISHING PAD USED IN CHEMICAL-MECHANICAL POLISHING OF MICROELECTRONIC SUBSTRATES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09032254
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
SEMICONDUCTOR PROCESSING METHODS OF FORMING A CONDUCTIVE PROJECTION AND METHODS OF INCREASING ALIGNMENT TOLERANCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09032261
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
METHODS OF FORMING ELECTRICAL CONTACTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09032267
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
METHODS OF FORMING FIELD EFFECT TRANSISTORS AND FIELD EFFECT TRANSISTOR CIRCUITRY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
09032272
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
METHOD AND CIRCUIT FOR TRIMMING THE INTERNAL TIMING CONDITIONS OF A SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/07/1999
|
Application #:
|
09032282
|
Filing Dt:
|
02/26/1998
|
|
Title:
|
STAIRCASE ADAPTIVE VOLTAGE GENERATOR CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09032417
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
METHOD AND APPARATUS FOR STORAGE OF TEST RESULTS WITHIN AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/24/1999
|
Application #:
|
09032422
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
CIRCUIT AND METHOD FOR TESTING AN INTEGRATED CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09032617
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
FIELD PROGRAMMABLE LOGIC ARRAYS WITH VERTICAL TRANSISTORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09032628
|
Filing Dt:
|
02/27/1998
|
|
Title:
|
ORGANIC SUBSTRATE (PCB) SLIP PLANE "STRESS DEFLECTOR" FOR FLIP CHIP DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/21/1999
|
Application #:
|
09032701
|
Filing Dt:
|
03/02/1998
|
|
Title:
|
A METHOD FOR CLEANING A SEMICONDUCTOR STRUCTURE
|
|
