|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
09387640
|
Filing Dt:
|
08/31/1999
|
Title:
|
CHIP PACKAGE WITH GREASE HEAT SINK AND METHOD OF MAKING
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/2000
|
Application #:
|
09387650
|
Filing Dt:
|
09/01/1999
|
Title:
|
CIRCUIT AND METHOD FOR A MULTIPLEXED REDUNDANCY SCHEME IN A MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/2002
|
Application #:
|
09387774
|
Filing Dt:
|
09/01/1999
|
Title:
|
SELF-ADJUSTING PRINTED CIRCUIT BOARD SUPPORT AND METHOD OF USE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
09388031
|
Filing Dt:
|
09/01/1999
|
Publication #:
|
|
Pub Dt:
|
05/16/2002
| | | | |
Title:
|
METALLIZATION STRUCTURES FOR SEMICONDUCTOR DEVICE INTERCONNECTS, METHODS FOR MAKING SAME, AND SEMICONDUCTOR DEVICES INCLUDING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09388032
|
Filing Dt:
|
09/01/1999
|
Title:
|
CONTINUOUS MODE SOLDER JET APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/12/2003
|
Application #:
|
09388045
|
Filing Dt:
|
09/01/1999
|
Title:
|
ASYMMETRIC TRANSFER MOLDING METHOD AND AN ASYMMETRIC ENCAPSULATION MADE THEREFROM
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09388126
|
Filing Dt:
|
09/01/1999
|
Title:
|
METHOD AND APPARATUS FOR SUPPLYING REGULATED POWER TO MEMORY DEVICE COMPONENTS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09388133
|
Filing Dt:
|
09/01/1999
|
Title:
|
AMMONIA PASSIVATION OF METAL GATE ELECTRODES TO INHIBIT OXIDATION OF METAL
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09388246
|
Filing Dt:
|
09/01/1999
|
Title:
|
NON-KNURLED INDUCTION COIL FOR IONIZED METAL DEPOSITION, SPUTTERING APPARATUS INCLUDING SAME, AND METHOD OF CONSTRUCTING THE APPARATUS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09388287
|
Filing Dt:
|
09/01/1999
|
Publication #:
|
|
Pub Dt:
|
07/18/2002
| | | | |
Title:
|
METHOD AND STRUCTURE FOR AN IMPROVED FLOATING GATE MEMORY CELL
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09388450
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD FOR IMPROVING CMP PROCESSING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
|
09388567
|
Filing Dt:
|
09/02/1999
|
Title:
|
LOCAL MULTILAYERED METALLIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09388656
|
Filing Dt:
|
09/02/1999
|
Title:
|
MEMORY USING INSULATOR TRAPS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/21/2003
|
Application #:
|
09388660
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD OF FORMING A SEMICONDUCTOR CONTACT THAT INCLUDES SELECTIVELY REMOVING A TI-CONTAINING LAYER FROM THE SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09388667
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD OF DEPOSITING FILMS BY USING CARBOXYLATE COMPLEXES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09388671
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD AND APPARATUS FOR PROGRAMMABLE FIELD EMISSION DISPLAY
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09388681
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD AND APPARATUS FOR APPLYING ATOMIZED ADHESIVE TO A LEADFRAME FOR CHIP BONDING
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09388685
|
Filing Dt:
|
09/02/1999
|
Title:
|
OXIDE ETCHING METHOD AND STRUCTURES RESULTING FROM SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
04/22/2003
|
Application #:
|
09388687
|
Filing Dt:
|
09/02/1999
|
Title:
|
MEMORY DEVICE INCLUDING REDUNDANCY ROUTINE FOR CORRECTING RANDOM ERRORS
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09388706
|
Filing Dt:
|
09/02/1999
|
Title:
|
BALL ARRAY LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/2002
|
Application #:
|
09388731
|
Filing Dt:
|
09/01/1999
|
Title:
|
METHOD OF FORMING A LAYER COMPRISING TUNGSTEN OXIDE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/2002
|
Application #:
|
09388764
|
Filing Dt:
|
09/02/1999
|
Title:
|
MIXED-MODE STACKED INTEGRATED CIRCUIT WITH POWER SUPPLY CIRCUIT PART OF THE STACK
|
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2001
|
Application #:
|
09388769
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHODS OF FABRICATING BURIED DIGIT LINES AND SEMICONDUCTOR DEVICES INCLUDING SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09388828
|
Filing Dt:
|
09/01/1999
|
Title:
|
METHOD AND APPARATUS FOR PLANARIZING A MICROELECTRONIC SUBSTRATE WITH A TILTED PLANARIZING SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/20/2002
|
Application #:
|
09388832
|
Filing Dt:
|
09/01/1999
|
Title:
|
LOCAL INTERCONNECT STRUCTURES AND METHODS FOR MAKING THE SAME
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
09388856
|
Filing Dt:
|
09/01/1999
|
Publication #:
|
|
Pub Dt:
|
12/13/2001
| | | | |
Title:
|
SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
09388857
|
Filing Dt:
|
09/01/1999
|
Publication #:
|
|
Pub Dt:
|
01/30/2003
| | | | |
Title:
|
SEMICONDUCTOR PROCESSING METHODS OF FORMING TRANSISTORS, SEMICONDUCTOR PROCESSING METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY CIRCUITRY, AND RELATED INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09388894
|
Filing Dt:
|
09/02/1999
|
Title:
|
METALLIZATION LINE LAYOUT
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09389106
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD AND MEMORY DEVICE FOR DYNAMIC CELL PLATE SENSING WITH AC EQUILIBRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/05/2000
|
Application #:
|
09389285
|
Filing Dt:
|
09/02/1999
|
Title:
|
UNIFORM TEMPERATURE ENVIRONMENTAL TESTING METHOD FOR SEMICONDUCTOR DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09389295
|
Filing Dt:
|
09/02/1999
|
Title:
|
CHANNEL IMPLANT THROUGH GATE POLYSILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
06/26/2001
|
Application #:
|
09389304
|
Filing Dt:
|
09/02/1999
|
Title:
|
MEMORY SYSTEM HAVING FLEXIBLE ADDRESSING AND METHOD USING TAG AND DATA BUS COMMUNICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09389313
|
Filing Dt:
|
09/02/1999
|
Title:
|
MEMORY WITH COMBINED SYNCHRONOUS BURST AND BUS EFFICIENT FUNCTIONALITY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/05/2001
|
Application #:
|
09389522
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD FOR FABRICATING ISOLATED ANTI-FUSE STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09389523
|
Filing Dt:
|
09/02/1999
|
Title:
|
SELECTIVELY FORMED CONTACT STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/27/2001
|
Application #:
|
09389526
|
Filing Dt:
|
09/02/1999
|
Title:
|
SEMICONDUCTOR PROCESSING METHOD OF REDUCING AN ETCH RATE OF ONE PORTION OF A DOPED MATERIAL RELATIVE TO ANOTHER PORTION, AND METHODS OF FORMING OPENINGS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09389536
|
Filing Dt:
|
09/02/1999
|
Title:
|
LASER PYROLYSIS PARTICLE FORMING METHOD AND PARTICLE FORMING METHOD
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09389656
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD TO FABRICATE AN INTRINSIC POLYCRYSTALLINE SILICON FILM
|
|
|
Patent #:
|
|
Issue Dt:
|
09/04/2001
|
Application #:
|
09389662
|
Filing Dt:
|
09/02/1999
|
Title:
|
OUTPUT DRIVER HAVING A PROGRAMMABLE EDGE RATE
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09389664
|
Filing Dt:
|
08/31/1999
|
Title:
|
METHODS FOR PREDICTING POLISHING PARAMETERS OF POLISHING PADS AND METHODS AND MACHINES FOR PLANARIZING MICROELECTRONIC SUBSTRATE ASSEMBLIES IN MECHANICAL OR CHEMICAL-MECHANICAL PLANARIZATION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/2002
|
Application #:
|
09389670
|
Filing Dt:
|
09/02/1999
|
Publication #:
|
|
Pub Dt:
|
06/13/2002
| | | | |
Title:
|
METHODS OF FORMING DRAM ASSEMBLIES, TRANSISTOR DEVICES, AND OPENINGS IN SUBSTRATES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/2004
|
Application #:
|
09389844
|
Filing Dt:
|
09/02/1999
|
Publication #:
|
|
Pub Dt:
|
05/23/2002
| | | | |
Title:
|
BOARD-ON-CHIP PACKAGES WITH CONDUCTIVE FOIL ON THE CHIP SURFACE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09389866
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD OF FORMING A CONTAINER CAPACITOR STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/27/2002
|
Application #:
|
09389870
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD OF FABRICATING ATTENUATED PHASE SHIFT MASK
|
|
|
Patent #:
|
|
Issue Dt:
|
06/06/2000
|
Application #:
|
09389955
|
Filing Dt:
|
09/03/1999
|
Title:
|
MEMORY DEVICE WITH A MEMORY CELL ARRAY IN TRIPLE WELL, AND RELATED MANUFACTURING PROCESS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09389994
|
Filing Dt:
|
09/03/1999
|
Title:
|
ORGANIZATION OF BLOCKS WITHIN A NONVOLATILE MEMORY UNIT TO EFFECTIVELY DECREASE SECTOR WRITE OPERATION TIME
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09390889
|
Filing Dt:
|
09/07/1999
|
Title:
|
DEVICE AND METHOD FOR STACKING WIRE-BONDED INTEGRATED CIRCUIT DICE ON FLIP-CHIP BONDED INTEGRATED CIRCUIT DICE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/2002
|
Application #:
|
09391078
|
Filing Dt:
|
09/02/1999
|
Title:
|
METHOD OF PROCESSING A SUBSTRATE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09391471
|
Filing Dt:
|
09/08/1999
|
Title:
|
METHOD FOR SUPPLYING FLUSH FLUID
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09392072
|
Filing Dt:
|
09/08/1999
|
Title:
|
METHODS OF FORMING ICS CONDUCTIVE LINES, A CONDUCTIVE GRID, A CONDUCTIVE NETWORK, AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION AND ICS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
09392153
|
Filing Dt:
|
09/08/1999
|
Title:
|
FLIP CHIP TECHNIQUE FOR CHIP ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09392154
|
Filing Dt:
|
09/08/1999
|
Title:
|
DEVICE AND METHOD FOR MARGIN TESTING A SEMICONDUCTOR MEMORY BY APPLYING A STRESSING VOLTAGE SIMULTANEOUSLY TO COMPLEMENTARY AND TRUE DIGIT LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09392819
|
Filing Dt:
|
09/09/1999
|
Title:
|
BONDING AND INSPECTION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09392937
|
Filing Dt:
|
09/09/1999
|
Title:
|
METHOD FOR MANUFACTURING ELECTRONIC DEVICES COMPRISING NON-VOLATILE MEMORY CELLS AND LV TRANSISTORS WITH SALICIDED JUNCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
09393078
|
Filing Dt:
|
09/07/1999
|
Title:
|
CAPACITORS, METHODS OF FORMING CAPACITORS, AND INTEGRATED CIRCUITRY
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/2002
|
Application #:
|
09393477
|
Filing Dt:
|
09/10/1999
|
Title:
|
STOCHASTIC SAMPLING WITH CONSTANT DENSITY IN OBJECT SPACE FOR ANISOTROPIC TEXTURE MAPPING
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/2002
|
Application #:
|
09393542
|
Filing Dt:
|
09/10/1999
|
Title:
|
SEMICONDUCTOR WAFER ASSEMBLIES COMPRISING SILICON NITRIDE, METHODS OF FORMING SILICON NITRIDE, AND METHODS OF REDUCING STRESS ON SEMICONDUCTIVE WAFERS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/22/2000
|
Application #:
|
09393757
|
Filing Dt:
|
09/10/1999
|
Title:
|
STEREOSCOPIC IMAGE SENSOR
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09394109
|
Filing Dt:
|
09/10/1999
|
Title:
|
MEMORY USING INSULATOR TRAPS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/26/2000
|
Application #:
|
09394994
|
Filing Dt:
|
09/13/1999
|
Title:
|
DEVICE AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
05/07/2002
|
Application #:
|
09395000
|
Filing Dt:
|
09/13/1999
|
Title:
|
METHOD AND APPARATUS FOR INTERLACED IMAGE ENHANCEMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09395777
|
Filing Dt:
|
09/14/1999
|
Title:
|
METHOD AND APPARATUS FOR ULTRASONIC WET ETCHING OF SILICON
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2000
|
Application #:
|
09396189
|
Filing Dt:
|
09/14/1999
|
Title:
|
NON-VOLATILE STORAGE LATCH
|
|
|
Patent #:
|
|
Issue Dt:
|
07/10/2001
|
Application #:
|
09396389
|
Filing Dt:
|
09/15/1999
|
Title:
|
PLASMA ETCHING METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09397387
|
Filing Dt:
|
09/15/1999
|
Title:
|
METHOD FOR MAINTAINING THE MEMORY CONTENT OF NON-VOLATILE MEMORY CELLS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2006
|
Application #:
|
09397952
|
Filing Dt:
|
09/17/1999
|
Title:
|
FABRICATION OF INTEGRATED DEVICES USING NITROGEN IMPLANTATION
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2003
|
Application #:
|
09398337
|
Filing Dt:
|
09/17/1999
|
Publication #:
|
|
Pub Dt:
|
05/16/2002
| | | | |
Title:
|
METHODS OF HIGH DENSITY FLIP-CHIP MEMORY ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09398575
|
Filing Dt:
|
09/17/1999
|
Title:
|
METHOD OF MAKING A SOCKET ASSEMBLY FOR USE WITH A SOLDER BALL
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2001
|
Application #:
|
09399591
|
Filing Dt:
|
09/20/1999
|
Title:
|
PLATINUM -CONTAINING MATERIALS AND CATALYSTS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09399640
|
Filing Dt:
|
09/20/1999
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATICALLY POSITIONING ELECTRONIC DICE WITHIN COMPONENT PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2000
|
Application #:
|
09400515
|
Filing Dt:
|
09/20/1999
|
Title:
|
METHOD AND APPARATUS FOR AUTOMATICALLY POSITIONING ELECTRONIC DICE WITHIN COMPONENT PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09401554
|
Filing Dt:
|
09/22/1999
|
Title:
|
SEMICONDUCTOR MEMORY REMAPPING
|
|
|
Patent #:
|
|
Issue Dt:
|
06/17/2003
|
Application #:
|
09401886
|
Filing Dt:
|
09/23/1999
|
Title:
|
SERIAL COMMAND PORT METHOD, CIRCUIT, AND SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2003
|
Application #:
|
09402694
|
Filing Dt:
|
10/08/1999
|
Title:
|
CLOSED-LOOP SYNCHRONISATION ARRANGEMENT FOR DATA TRANSMISSION SYSTEM
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/2002
|
Application #:
|
09405091
|
Filing Dt:
|
09/27/1999
|
Publication #:
|
|
Pub Dt:
|
12/20/2001
| | | | |
Title:
|
TRENCH DRAM CELL WITH VERTICAL DEVICE AND BURIED WORD LINES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09406329
|
Filing Dt:
|
09/27/1999
|
Title:
|
METHOD AND APPARATUS FOR RAPID INITIALIZATION OF CHARGE PUMP CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09407614
|
Filing Dt:
|
09/28/1999
|
Title:
|
DEVICE AND METHOD FOR SUPPLYING CURRENT TO A SEMICONDUCTOR MEMORY TO SUPPORT A BOOSTED VOLTAGE WITHIN THE MEMORY DURING TESTING
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/2004
|
Application #:
|
09409367
|
Filing Dt:
|
09/30/1999
|
Title:
|
METHOD AND APPARATUS FOR AN ADJUSTABLE DELAY CIRCUIT HAVING ARRANGED SERIALLY COARSE STAGES RECEIVED BY A FINE DELAY STAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09409523
|
Filing Dt:
|
09/30/1999
|
Title:
|
METHOD AND APPARATUS TO REDUCE MEMORY READ LATENCY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/31/2001
|
Application #:
|
09409782
|
Filing Dt:
|
09/30/1999
|
Title:
|
SEMICONDUCTOR DEVICE INCLUDING EDGE BOND PADS AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
07/01/2003
|
Application #:
|
09410164
|
Filing Dt:
|
09/30/1999
|
Title:
|
CIRCUIT AND METHOD FOR READING A MEMORY CELL THAT CAN STORE MULTIPLE BITS OF DATA
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/2002
|
Application #:
|
09410400
|
Filing Dt:
|
10/01/1999
|
Title:
|
METHOD AND APPARATUS FOR TRANSFERRING WAFER CASSETTES IN MICROELECTRONIC MANUFACTURING ENVIRONMENT
|
|
|
Patent #:
|
|
Issue Dt:
|
05/15/2001
|
Application #:
|
09410969
|
Filing Dt:
|
10/04/1999
|
Publication #:
|
|
Pub Dt:
|
05/31/2001
| | | | |
Title:
|
SUBSTRATE COATING APPARATUS AND SEMICONDUCTOR PROCESSING METHOD OF IMPROVING UNIFORMITY OF LIQUID DEPOSITION
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09411498
|
Filing Dt:
|
10/04/1999
|
Title:
|
SPIN COATING SPINDLE AND CHUCK ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09413382
|
Filing Dt:
|
10/06/1999
|
Title:
|
ADDRESS TRANSITION DETECTOR IN SEMICONDUCTOR MEMORIES
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2001
|
Application #:
|
09414203
|
Filing Dt:
|
10/07/1999
|
Title:
|
INTERPOSER/CONVERTER TO ALLOW SINGLE-SIDED CONTACT TO CIRCUIT MODULES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/03/2001
|
Application #:
|
09414426
|
Filing Dt:
|
10/07/1999
|
Title:
|
METHOD OF MAKING DENSE SOI FLASH MEMORY ARRAY STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09415472
|
Filing Dt:
|
10/08/1999
|
Title:
|
LAYOUT FOR A SEMICONDUCTOR MEMORY DEVICE HAVING PLURALITY OF PRIMARY AND REDUNDANT CIRCUIT ELEMENTS BEING DIVIDED INTO AT LEAST FIRST AND SECOND SETS NOT SIMULTANEOUSLY ACTIVE
|
|
|
Patent #:
|
|
Issue Dt:
|
06/12/2001
|
Application #:
|
09415739
|
Filing Dt:
|
10/12/1999
|
Title:
|
DOWNSET LEAD FRAME FOR SEMICONDUCTOR PACKAGES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09416301
|
Filing Dt:
|
10/12/1999
|
Title:
|
METHOD AND APPARATUS FOR CIRCUIT VARIABLE UPDATES
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2005
|
Application #:
|
09416368
|
Filing Dt:
|
10/12/1999
|
Title:
|
INTEGRATED CIRCUIT PACKAGE ALIGNMENT FEATURE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/04/2000
|
Application #:
|
09416369
|
Filing Dt:
|
10/12/1999
|
Title:
|
REDUCED STRESS LOC ASSEMBLY
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09416371
|
Filing Dt:
|
10/12/1999
|
Title:
|
METHOD AND APPARATUS FOR STRESS TESTING A SEMICONDUCTOR MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/15/2000
|
Application #:
|
09416711
|
Filing Dt:
|
10/12/1999
|
Title:
|
SEMICONDUCTOR MEMORY WITH LOCAL PHASE GENERATION FROM GLOBAL PHASE SIGNALS AND LOCAL ISOLATION SIGNALS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09416818
|
Filing Dt:
|
10/12/1999
|
Title:
|
INTEGRATED CIRCUITRY AND THIN FILM TRANSISTORS
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09417029
|
Filing Dt:
|
10/12/1999
|
Title:
|
CIRCUIT AND A METHOD FOR CONFIGURING PAD CONNECTIONS IN AN INTEGRATED DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
09417160
|
Filing Dt:
|
10/12/1999
|
Title:
|
MULTI-CAPACITANCE LEAD FRAME DECOUPLING DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
07/16/2002
|
Application #:
|
09417964
|
Filing Dt:
|
10/13/1999
|
Title:
|
METHOD AND APPARATUS FOR PROVIDING VISIBILITY AND CONTROL OVER COMPONENTS WITHIN A PROGRAMMABLE LOGIC CIRCUIT FOR EMULATION PURPOSES
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09418229
|
Filing Dt:
|
10/14/1999
|
Title:
|
SEMICONDUCTOR PROBE CARD HAVING RESISTANCE MEASURING CIRCUITRY AND METHOD OF FABRICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09418465
|
Filing Dt:
|
10/15/1999
|
Title:
|
APPARATUS FOR FLEXIBLY ALLOCATING REQUEST/GRANT PINS BETWEEN MULTIPLE BUS CONTROLLERS
|
|