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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:050937/0001   Pages: 964
Recorded: 10/09/2019
Attorney Dkt #:4816.244
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
08/14/2001
Application #:
09418466
Filing Dt:
10/15/1999
Title:
METHOD FOR PRESERVING MEMORY REQUEST ORDERING ACROSS MULTIPLE MEMORY CONTROLLERS
2
Patent #:
Issue Dt:
08/14/2001
Application #:
09418467
Filing Dt:
10/15/1999
Title:
APPARATUS FOR PRESERVING MEMORY REQUEST ORDERING ACROSS MULTIPLE MEMORY CONTROLLERS
3
Patent #:
Issue Dt:
05/07/2002
Application #:
09418468
Filing Dt:
10/15/1999
Title:
METHOD FOR FLEXIBLY ALLOCATING REQUEST/GRANT PINS BETWEEN MULTIPLE BUS CONTROLLERS
4
Patent #:
Issue Dt:
08/28/2001
Application #:
09419278
Filing Dt:
10/15/1999
Title:
APPARATUS FOR COOLING CENTRAL PROCESSING UNITS IN PERSONAL COMPUTERS
5
Patent #:
Issue Dt:
09/03/2002
Application #:
09419403
Filing Dt:
10/14/1999
Title:
SIMPLIFIED PROCESS FOR DEFINING THE TUNNEL AREA IN NON-ALIGNED, NON-VOLATILE SEMICONDUCTOR MEMORY CELLS
6
Patent #:
Issue Dt:
05/27/2003
Application #:
09420205
Filing Dt:
10/18/1999
Publication #:
Pub Dt:
10/03/2002
Title:
METHODS OF PATTERNING RADIATION , METHODS OF FORMING RADIATION- PATTERNING TOOLS, AND RADIATION-PATTERNING TOOLS
7
Patent #:
Issue Dt:
08/06/2002
Application #:
09420332
Filing Dt:
10/18/1999
Publication #:
Pub Dt:
11/08/2001
Title:
ELECTRONIC DEVICE WORKPIECE CARRIERS
8
Patent #:
Issue Dt:
04/29/2003
Application #:
09420635
Filing Dt:
10/21/1999
Publication #:
Pub Dt:
01/24/2002
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING DEVICES ON A SUBSTRATE, FORMING DEVICE ARRAYS ON A SUBSTRATE, FORMING CONDUCTIVE LINES ON A SUBSTRATE, AND FORMING CAPACITOR ARRAYS ON A SUBSTRATE, AND INTEGRATED CIRCUITRY
9
Patent #:
Issue Dt:
09/03/2002
Application #:
09420672
Filing Dt:
10/19/1999
Title:
METHOD OF FORMING A STACK OF PACKAGED MEMORY DIE AND RESULTING APPARATUS
10
Patent #:
Issue Dt:
04/10/2001
Application #:
09420964
Filing Dt:
10/20/1999
Title:
METHOD OF FORMING A DOPED REGION IN A SEMICONDUCTOR SUBSTRATE
11
Patent #:
Issue Dt:
12/12/2000
Application #:
09421164
Filing Dt:
10/19/1999
Title:
APPARATUS AND METHOD FOR FACILITATING CIRCUIT BOARD PROCESSING
12
Patent #:
Issue Dt:
02/27/2001
Application #:
09421165
Filing Dt:
10/19/1999
Title:
METHOD OF FORMING WIRE LINE
13
Patent #:
Issue Dt:
03/27/2001
Application #:
09421170
Filing Dt:
10/19/1999
Title:
LEAD PENETRATING CLAMPING SYSTEM
14
Patent #:
Issue Dt:
04/26/2005
Application #:
09422887
Filing Dt:
10/21/1999
Title:
ANGULARLY OFFSET STACKED DIE MULTICHIP DEVICE AND METHOD OF MANUFACTURE
15
Patent #:
Issue Dt:
08/14/2001
Application #:
09425115
Filing Dt:
10/20/1999
Title:
TUNGSTEN CHEMICAL-MECHANICAL POLISHING PROCESS USING A FIXED ABRASIVE POLISHING PAD AND A TUNGSTEN LAYER CHEMICAL-MECHANICAL POLISHING SOLUTION SPECIFICALLY ADAPTED FOR CHEMICAL-MECHANICAL POLISHING WITH A FIXED ABRASIVE PAD
16
Patent #:
Issue Dt:
02/27/2001
Application #:
09425446
Filing Dt:
10/22/1999
Title:
DEVICE FOR READING ANALOG NONVOLATILE MEMORY CELLS, IN PARTICULAR FLASH CELLS
17
Patent #:
Issue Dt:
04/03/2001
Application #:
09426451
Filing Dt:
10/25/1999
Title:
ULTRA HIGH DENSITY FLASH MEMORY HAVING VERTICALLY STACKED DEVICES
18
Patent #:
Issue Dt:
06/05/2001
Application #:
09426634
Filing Dt:
10/26/1999
Title:
CIRCUIT FOR PREVENTING BUS CONTENTION
19
Patent #:
Issue Dt:
11/04/2003
Application #:
09427920
Filing Dt:
10/27/1999
Title:
METHOD OF REDUCING WATER SPOTTING AND OXIDE GROWTH ON A SEMICONDUCTOR STRUCTURE
20
Patent #:
Issue Dt:
11/19/2002
Application #:
09428159
Filing Dt:
10/27/1999
Title:
METHOD FOR IMPROVED METAL FILL BY TREATMENT OF MOBILITY LAYERS
21
Patent #:
Issue Dt:
10/03/2000
Application #:
09428683
Filing Dt:
10/27/1999
Title:
NONVOLATILE MEMORY TEST STRUCTURE AND NONVOLATILE MEMORY RELIABILITY TEST METHOD
22
Patent #:
Issue Dt:
01/21/2003
Application #:
09429236
Filing Dt:
10/28/1999
Title:
METHOD OF DEPOSITING POLYSILICON, METHOD OF FABRICATING A FIELD EFFECT TRANSISTOR, METHOD OF FORMING A CONTACT TO A SUBSTRATE, METHOD OF FORMING A CAPACITOR
23
Patent #:
Issue Dt:
12/12/2000
Application #:
09429505
Filing Dt:
10/28/1999
Title:
APPARATUS FOR MOUNTING COMPUTER COMPONENTS
24
Patent #:
Issue Dt:
01/16/2001
Application #:
09429664
Filing Dt:
10/28/1999
Title:
NON-VOLATILE STORAGE LATCH
25
Patent #:
Issue Dt:
09/17/2002
Application #:
09429882
Filing Dt:
10/29/1999
Title:
OPTICAL RANGE FINDER
26
Patent #:
Issue Dt:
07/24/2001
Application #:
09430442
Filing Dt:
10/29/1999
Title:
METHOD FOR FORMING GATE SEGMENTS FOR AN INTEGRATED CIRCUIT
27
Patent #:
Issue Dt:
08/20/2002
Application #:
09430558
Filing Dt:
10/29/1999
Title:
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS WITH HIGH ASPECT RATIO FEATURES
28
Patent #:
Issue Dt:
07/15/2003
Application #:
09432050
Filing Dt:
11/01/1999
Title:
ELASTIC BUFFER
29
Patent #:
Issue Dt:
02/25/2003
Application #:
09432134
Filing Dt:
11/02/1999
Title:
METHOD AND APPARATUS FOR ADAPTIVE HIERARCHICAL VISIBILITY IN A TILED THREE-DIMENSIONAL GRAPHICS ARCHITECTURE
30
Patent #:
Issue Dt:
07/24/2001
Application #:
09432513
Filing Dt:
11/02/1999
Title:
METHOD FOR FORMING DIELECTRIC WITHIN A RECESS
31
Patent #:
Issue Dt:
07/25/2000
Application #:
09432642
Filing Dt:
11/02/1999
Title:
LINE DECODER FOR MEMORY DEVICES
32
Patent #:
Issue Dt:
01/13/2004
Application #:
09432687
Filing Dt:
11/03/1999
Publication #:
Pub Dt:
11/15/2001
Title:
METHOD AND DEVICE TO USE MEMORY ACCESS REQUEST TAGS
33
Patent #:
Issue Dt:
03/13/2001
Application #:
09433440
Filing Dt:
11/04/1999
Title:
METHOD OF ATTACHING A LEADFRAME TO SINGULATED SEMICONDUCTOR DICE
34
Patent #:
Issue Dt:
12/31/2002
Application #:
09433512
Filing Dt:
11/03/1999
Title:
METHOD FOR CONFIGURING A REDUNDANT BOND PAD FOR PROBING A SEMICONDUCTOR
35
Patent #:
Issue Dt:
07/29/2003
Application #:
09433513
Filing Dt:
11/03/1999
Title:
CIRCUIT HAVING A LONG L DEVICE CONFIGURED FOR TESTING
36
Patent #:
Issue Dt:
03/06/2001
Application #:
09434147
Filing Dt:
11/04/1999
Title:
METHOD FOR SAWING WAFERS EMPLOYING MULTIPLE INDEXING TECHNIQUES FOR MULTIPLE DIE DIMENSIONS
37
Patent #:
Issue Dt:
07/31/2001
Application #:
09434250
Filing Dt:
11/05/1999
Title:
SELF-TUNING AMPLIFIER
38
Patent #:
Issue Dt:
09/05/2000
Application #:
09435237
Filing Dt:
11/05/1999
Title:
PLASMA PROCESSING TOOLS, DUAL-SOURCE PLASMA ETCHERS, DUAL-SOURCE PLASMA ETCHING METHODS, AND METHODS OF FORMING PLANAR COIL DUAL-SOURCE PLASMA ETCHERS
39
Patent #:
Issue Dt:
08/21/2001
Application #:
09435588
Filing Dt:
11/08/1999
Title:
METHOD AND APPARATUS FOR LIMITING BITLINE CURRENT
40
Patent #:
Issue Dt:
08/21/2001
Application #:
09436483
Filing Dt:
11/08/1999
Title:
INTERCONNECT AND SYSTEM FOR MAKING TEMPORARY ELECTRICAL CONNECTIONS TO SEMICONDUCTOR COMPONENTS
41
Patent #:
Issue Dt:
05/27/2003
Application #:
09436967
Filing Dt:
11/09/1999
Title:
ANODE SCREEN FOR A PHOSPHOR DISPLAY WITH A PLURALITY OF PIXEL REGIONS DEFINING PHOSPHOR LAYER HOLES
42
Patent #:
Issue Dt:
03/27/2001
Application #:
09437595
Filing Dt:
11/10/1999
Title:
MULTI-CHIP MODULE WITH STACKED DICE
43
Patent #:
Issue Dt:
09/24/2002
Application #:
09437870
Filing Dt:
11/10/1999
Title:
COUPLING SPACED BOND PADS TO A CONTACT
44
Patent #:
Issue Dt:
09/18/2001
Application #:
09438186
Filing Dt:
11/11/1999
Title:
GATE ENHANCEMENT CHARGE PUMP FOR LOW VOLTAGE POWER SUPPLY
45
Patent #:
Issue Dt:
10/15/2002
Application #:
09438232
Filing Dt:
11/12/1999
Title:
DEVICE AND METHOD FOR PROGRAMMING NONVOLATILE MEMORY CELLS WITH AUTOMATIC GENERATION OF PROGRAMMING VOLTAGE
46
Patent #:
Issue Dt:
07/07/2009
Application #:
09438692
Filing Dt:
11/11/1999
Title:
SEMICONDUCTOR DEVICE WITH IMPROVED BOND PADS
47
Patent #:
Issue Dt:
10/03/2000
Application #:
09438823
Filing Dt:
11/12/1999
Title:
CIRCUIT FOR HIGH-PRECISION ANALOG READING OF NONVOLATILE MEMORY CELLS, IN PARTICULAR ANALOG OR MULTILEVEL FLASH OR EEPROM MEMORY CELLS
48
Patent #:
Issue Dt:
11/07/2000
Application #:
09439972
Filing Dt:
11/12/1999
Title:
DIE ARCHITECTURE ACCOMMODATING HIGH-SPEED SEMICONDUCTOR DEVICES
49
Patent #:
Issue Dt:
01/30/2001
Application #:
09440380
Filing Dt:
11/15/1999
Title:
METHOD FOR FABRICATING A SEMICONDUCTOR COMPONENT WITH EXTERNAL POLYMER SUPPORT LAYER
50
Patent #:
Issue Dt:
05/01/2001
Application #:
09440736
Filing Dt:
11/16/1999
Title:
NON-LOT BASED METHOD FOR ASSEMBLING INTEGRATED CIRCUIT DEVICES
51
Patent #:
Issue Dt:
07/25/2000
Application #:
09440839
Filing Dt:
11/15/1999
Title:
WAFER CARRIER HAVING BOTH A RIGID STRUCTURE AND RESISTANCE TO CORROSIVE ENVIRONMENTS
52
Patent #:
Issue Dt:
04/16/2002
Application #:
09440986
Filing Dt:
11/16/1999
Title:
DATA PIPELINING METHOD AND APPARATUS FOR MEMORY CONTROL CIRCUIT
53
Patent #:
Issue Dt:
05/27/2003
Application #:
09441524
Filing Dt:
11/16/1999
Title:
MULTI-PART LEAD FRAME WITH DISSIMILAR MATERIALS
54
Patent #:
Issue Dt:
11/28/2000
Application #:
09441718
Filing Dt:
11/16/1999
Title:
SEMICONDUCTOR PROCESSING METHOD OF MAKING ELECTRICAL CONTACT TO A NODE RECEIVED WITHIN A MASS OF INSULATING DIELECTRIC MATERIAL
55
Patent #:
Issue Dt:
04/10/2001
Application #:
09442340
Filing Dt:
11/17/1999
Title:
THIN FILM TRANSISTORS AND METHOD OF FORMING THIN FILM TRANSISTORS
56
Patent #:
Issue Dt:
05/14/2002
Application #:
09442834
Filing Dt:
11/18/1999
Title:
IMPROVED FIELD-EFFECT TRANSISTOR AND CORRESPONDING MANUFACTURING METHOD
57
Patent #:
Issue Dt:
04/10/2001
Application #:
09443080
Filing Dt:
11/18/1999
Title:
METHOD AND APPARATUS PROVIDING REDUNDANCY FOR FABRICATING HIGHLY RELIABLE MEMORY MODULES
58
Patent #:
Issue Dt:
10/17/2000
Application #:
09443661
Filing Dt:
11/19/1999
Title:
MULTI-STATE FLASH MEMORY DEFECT MANAGEMENT
59
Patent #:
Issue Dt:
05/08/2001
Application #:
09443666
Filing Dt:
11/19/1999
Title:
METHOD OF MAKING AN ANTIREFLECTIVE STRUCTURE
60
Patent #:
Issue Dt:
08/01/2000
Application #:
09443874
Filing Dt:
11/19/1999
Title:
SYNCHRONOUS MEMORY WITH PROGRAMMABLE READ LATENCY
61
Patent #:
Issue Dt:
07/09/2002
Application #:
09444024
Filing Dt:
11/19/1999
Publication #:
Pub Dt:
11/15/2001
Title:
MOSFET WITH NITROGEN ATOMS IN THE GATE OXIDE
62
Patent #:
Issue Dt:
05/15/2001
Application #:
09444280
Filing Dt:
11/19/1999
Title:
MICROELECTRONIC DEVICE FABRICATING METHOD, INTEGRATED CIRCUIT, AND INTERMEDIATE CONSTRUCTION
63
Patent #:
Issue Dt:
04/02/2002
Application #:
09447075
Filing Dt:
11/22/1999
Title:
METHOD AND APPARATUS FOR COUPLING SIGNALS BETWEEN TWO CIRCUITS OPERATING IN DIFFERENT CLOCK DOMAINS
64
Patent #:
Issue Dt:
12/19/2000
Application #:
09447531
Filing Dt:
11/23/1999
Title:
CIRCUIT FOR PARALLEL PROGRAMMING NONVOLATILE MEMORY CELLS, WITH ADJUSTABLE PROGRAMMING SPEED
65
Patent #:
Issue Dt:
02/03/2004
Application #:
09447981
Filing Dt:
11/23/1999
Title:
INTEGRATED CIRCUIT HAVING SELF-ALIGNED CVD-TUNGSTEN/TITANIUM CONTACT PLUGS STRAPPED WITH METAL INTERCONNECT AND METHOD OF MANUFACTURE
66
Patent #:
Issue Dt:
04/10/2001
Application #:
09447983
Filing Dt:
11/23/1999
Title:
METHOD OF FABRICATING A MULTI-CHIP MODULE
67
Patent #:
Issue Dt:
04/03/2001
Application #:
09448020
Filing Dt:
11/23/1999
Title:
METHODS AND ETCHANTS FOR ETCHING OXIDES OF SILICON WITH LOW SELECTIVITY
68
Patent #:
Issue Dt:
09/18/2001
Application #:
09448881
Filing Dt:
11/24/1999
Title:
SUPPLY VOLTAGE REDUCTION CIRCUIT FOR INTEGRATED CIRCUIT
69
Patent #:
Issue Dt:
03/16/2004
Application #:
09449026
Filing Dt:
11/24/1999
Publication #:
Pub Dt:
11/01/2001
Title:
METHODS OF FORMING AN INTEGRATED CIRCUIT DEVICE
70
Patent #:
Issue Dt:
06/25/2002
Application #:
09449044
Filing Dt:
11/24/1999
Title:
PROCESS FOR INTEGRATING IN A SAME CHIP A NON-VOLATILE MEMORY AND A HIGH-PERFORMANCE LOGIC CIRCUITRY
71
Patent #:
Issue Dt:
05/21/2002
Application #:
09449168
Filing Dt:
11/24/1999
Title:
METHOD FOR HIGH PRECISION PROGRAMMING NONVOLATILE MEMORY CELLS, WITH OPTIMIZED PROGRAMMING SPEED
72
Patent #:
Issue Dt:
07/16/2002
Application #:
09449580
Filing Dt:
11/29/1999
Title:
MULTIPLE IMAGE RETICLE FOR FORMING LAYERS
73
Patent #:
Issue Dt:
06/07/2011
Application #:
09449782
Filing Dt:
11/26/1999
Title:
COMMAND LINE OUTPUT REDIRECTION
74
Patent #:
Issue Dt:
01/30/2001
Application #:
09450241
Filing Dt:
11/29/1999
Title:
MULTI BANK TEST MODE FOR MEMORY DEVICES
75
Patent #:
Issue Dt:
07/09/2002
Application #:
09450301
Filing Dt:
11/29/1999
Title:
METHOD FOR MAKING A LOW RESISTIVITY ELECTRODE HAVING A NEAR NOBLE METAL
76
Patent #:
Issue Dt:
04/10/2001
Application #:
09450307
Filing Dt:
11/29/1999
Title:
METHOD AND APPARATUS FOR UNDERFILL OF BUMPED OR RAISED DIE
77
Patent #:
Issue Dt:
03/27/2001
Application #:
09451406
Filing Dt:
11/30/1999
Title:
PARTAL REPLACEMENT OF PARTIALLY DEFECTIVE MEMORY DEVICES
78
Patent #:
Issue Dt:
05/22/2001
Application #:
09451982
Filing Dt:
11/30/1999
Title:
CIRCUIT AND METHOD FOR LOW VOLTAGE, VOLTAGE SENSE AMPLIFIER
79
Patent #:
Issue Dt:
11/19/2002
Application #:
09452725
Filing Dt:
11/30/1999
Title:
METHODS OF FORMING DIODES
80
Patent #:
Issue Dt:
02/20/2001
Application #:
09453484
Filing Dt:
12/17/1999
Title:
WAFER SURFACE TREATMENT METHODS AND SYSTEMS USING ELECTROCAPILLARITY
81
Patent #:
Issue Dt:
06/11/2002
Application #:
09453753
Filing Dt:
12/02/1999
Title:
MULTIPLE LEVEL FLOATING-GATE MEMORY
82
Patent #:
Issue Dt:
09/19/2000
Application #:
09453848
Filing Dt:
12/01/1999
Title:
METHODS OF FABRICATING FLAT PANEL EVACUATED DISPLAYS
83
Patent #:
Issue Dt:
01/08/2002
Application #:
09454536
Filing Dt:
12/06/1999
Title:
BURIED BIT LINE MEMORY CIRCUITRY, METHOD OF FORMING BURIED BIT LINE MEMORY CIRCUITRY, AND SEMICONDUCTOR PROCESSING METHOD OF FORMING A CONDUCTIVE LINE
84
Patent #:
Issue Dt:
03/04/2003
Application #:
09454808
Filing Dt:
12/03/1999
Title:
APPARATUS AND METHOD FOR TESTING RAMBUS DRAMS
85
Patent #:
Issue Dt:
10/03/2006
Application #:
09455038
Filing Dt:
12/06/1999
Title:
METHOD AND APPARATUS FOR EPOXY LOC DIE ATTACHMENT
86
Patent #:
Issue Dt:
08/20/2002
Application #:
09455115
Filing Dt:
12/06/1999
Publication #:
Pub Dt:
04/18/2002
Title:
SEMICONDUCTOR STRUCTURE HAVING A DOPED CONDUCTIVE LAYER
87
Patent #:
Issue Dt:
10/03/2000
Application #:
09455365
Filing Dt:
12/06/1999
Title:
METHOD AND APPARATUS FOR ENHANCING THE PERFORMANCE OF SEMICONDUCTOR MEMORY DEVICES
88
Patent #:
Issue Dt:
05/21/2002
Application #:
09455537
Filing Dt:
12/07/1999
Publication #:
Pub Dt:
02/28/2002
Title:
METHOD AND APPARATUS FOR DIGITAL DELAY LOCKED LOOP CIRCUITS
89
Patent #:
Issue Dt:
01/23/2001
Application #:
09455850
Filing Dt:
12/07/1999
Title:
METHOD AND APPARATUS FOR WRITING DATA STATES TO NON-VOLATILE STORAGE DEVICES
90
Patent #:
Issue Dt:
06/17/2003
Application #:
09457058
Filing Dt:
12/07/1999
Title:
UP-SAMPLING DECIMATED COLOR PLANE DATA
91
Patent #:
Issue Dt:
09/18/2001
Application #:
09457264
Filing Dt:
12/09/1999
Title:
CMOS IMAGER CELL HAVING A BURIED CONTACT AND METHOD OF FABRICATION
92
Patent #:
Issue Dt:
11/13/2001
Application #:
09457429
Filing Dt:
12/07/1999
Title:
METHOD AND SYSTEM FOR ADAPTIVELY ADJUSTING CONTROL SIGNAL TIMING IN A MEMORY DEVICE
93
Patent #:
Issue Dt:
06/19/2001
Application #:
09457500
Filing Dt:
12/08/1999
Title:
ADDRESS LATCH ENABLE SIGNAL CONTROL CIRCUIT FOR ELECTRONIC MEMORIES
94
Patent #:
Issue Dt:
04/29/2003
Application #:
09458902
Filing Dt:
12/10/1999
Title:
PACKAGED SEMICONDUCTOR CHIP AND METHOD OF MAKING SAME
95
Patent #:
Issue Dt:
09/30/2003
Application #:
09459720
Filing Dt:
12/13/1999
Title:
MULTI-CHIP ADDRESSING FOR THE I2C BUS
96
Patent #:
Issue Dt:
04/23/2002
Application #:
09459754
Filing Dt:
12/10/1999
Title:
METHOD FOR FORMING NON VOLATILE MEMORY STRUCTURES ON A SEMICONDUCTOR SUBSTRATE
97
Patent #:
Issue Dt:
02/06/2001
Application #:
09459980
Filing Dt:
12/14/1999
Title:
METHOD AND APPARATUS FOR TRANSLATING SIGNALS
98
Patent #:
Issue Dt:
11/28/2000
Application #:
09460047
Filing Dt:
12/13/1999
Title:
MULTILAYERED LEAD FRAME FOR SEMICONDUCTOR PACKAGE
99
Patent #:
Issue Dt:
05/29/2001
Application #:
09460655
Filing Dt:
12/14/1999
Title:
HIGH-Q INDUCTIVE ELEMENTS
100
Patent #:
Issue Dt:
03/06/2001
Application #:
09461992
Filing Dt:
12/15/1999
Title:
SEMICONDUCTOR DEVICE SOCKET, ASSEMBLY AND METHODS
Assignor
1
Exec Dt:
07/31/2019
Assignee
1
8000 S FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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