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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:050937/0001   Pages: 964
Recorded: 10/09/2019
Attorney Dkt #:4816.244
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
08/03/2004
Application #:
09945337
Filing Dt:
08/31/2001
Publication #:
Pub Dt:
03/06/2003
Title:
SIDEWALL STRAP FOR COMPLEMENTARY SEMICONDUCTOR STRUCTURES AND METHOD OF MAKING SAME
2
Patent #:
Issue Dt:
06/24/2003
Application #:
09945380
Filing Dt:
08/31/2001
Publication #:
Pub Dt:
03/06/2003
Title:
CROSS-DIFFUSION RESISTANT DUAL-POLYCIDE SEMICONDUCTOR STRUCTURE AND METHOD
3
Patent #:
Issue Dt:
06/22/2004
Application #:
09945395
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
DRAM CELLS WITH REPRESSED FLOATING GATE MEMORY, LOW TUNNEL BARRIER INTERPOLY INSULATORS
4
Patent #:
Issue Dt:
05/04/2004
Application #:
09945398
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
02/21/2002
Title:
STATIC NVRAM WITH ULTRA THIN TUNNEL OXIDES
5
Patent #:
Issue Dt:
03/01/2005
Application #:
09945491
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
01/24/2002
Title:
ANTIFUSE STRUCTURES, METHODS, AND APPLICATIONS
6
Patent #:
Issue Dt:
10/05/2004
Application #:
09945495
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
VERTICAL TRANSISTORS, ELECTRICAL DEVICES CONTAINING A VERTICAL TRANSISTOR, AND COMPUTER SYSTEMS CONTAINING A VERTICAL TRANSISTOR
7
Patent #:
Issue Dt:
08/17/2004
Application #:
09945498
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
DEAPROM WITH INSULATING METAL OXIDE INTERPOLY INSULATORS
8
Patent #:
Issue Dt:
07/11/2006
Application #:
09945500
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
PROGRAMMABLE MEMORY ADDRESS AND DECODE CIRCUITS WITH LOW TUNNEL BARRIER INTERPOLY INSULATORS
9
Patent #:
Issue Dt:
06/27/2006
Application #:
09945507
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
FLASH MEMORY WITH LOW TUNNEL BARRIER INTERPOLY INSULATORS
10
Patent #:
Issue Dt:
05/07/2002
Application #:
09945509
Filing Dt:
08/30/2001
Title:
DELAY LOCKED LOOP MONITOR TEST MODE
11
Patent #:
Issue Dt:
06/10/2003
Application #:
09945511
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
02/28/2002
Title:
INTERNAL GUARDBAND FOR SEMICONDUCTOR TESTING
12
Patent #:
Issue Dt:
08/08/2006
Application #:
09945512
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
IN SERVICE PROGRAMMABLE LOGIC ARRAYS WITH LOW TUNNEL BARRIER INTERPOLY INSULATORS
13
Patent #:
Issue Dt:
01/14/2003
Application #:
09945513
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
04/25/2002
Title:
STRUCTURE FOR ESD PROCTECTION IN SEMICONDUCTOR CHIPS
14
Patent #:
Issue Dt:
07/01/2003
Application #:
09945514
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/13/2003
Title:
GRADED COMPOSITION GATE INSULATORS TO REDUCE TUNNELING BARRIERS IN FLASH MEMORY DEVICES
15
Patent #:
Issue Dt:
09/27/2011
Application #:
09945535
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/06/2003
Title:
HIGHLY RELIABLE AMORPHOUS HIGH-K GATE OXIDE ZRO2
16
Patent #:
Issue Dt:
04/15/2008
Application #:
09945553
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
04/17/2003
Title:
METHOD TO CHEMICALLY REMOVE METAL IMPURITIES FROM POLYCIDE GATE SIDEWALLS
17
Patent #:
Issue Dt:
06/10/2003
Application #:
09945567
Filing Dt:
08/30/2001
Publication #:
Pub Dt:
03/13/2003
Title:
TECHNIQUE FOR HIGH EFFICIENCY METALORGANIC CHEMICAL VAPOR DEPOSITION
18
Patent #:
Issue Dt:
03/03/2009
Application #:
09946054
Filing Dt:
09/04/2001
Publication #:
Pub Dt:
01/17/2002
Title:
METHOD FOR FORMING AN INDUCTOR
19
Patent #:
Issue Dt:
12/09/2003
Application #:
09946291
Filing Dt:
09/04/2001
Publication #:
Pub Dt:
02/28/2002
Title:
MICROELECTRONIC ASSEMBLY WITH PRE-DISPOSED FILL MATERIAL AND ASSOCIATED METHOD OF MANUFACTURE
20
Patent #:
Issue Dt:
05/10/2005
Application #:
09947331
Filing Dt:
09/05/2001
Publication #:
Pub Dt:
04/17/2003
Title:
SIGNAL TO NOISE RATIO OPTIMIZATION FOR VIDEO COMPRESSION BIT-RATE CONTROL
21
Patent #:
Issue Dt:
07/01/2003
Application #:
09947522
Filing Dt:
09/07/2001
Publication #:
Pub Dt:
01/17/2002
Title:
FREQUENCY SENSING NMOS VOLTAGE REGULATOR
22
Patent #:
Issue Dt:
05/20/2003
Application #:
09948496
Filing Dt:
09/06/2001
Publication #:
Pub Dt:
05/09/2002
Title:
SEMICONDUCTOR STRUCTURE HAVING MORE USABLE SUBSTRATE AREA AND METHOD FOR FORMING SAME
23
Patent #:
Issue Dt:
07/01/2003
Application #:
09948830
Filing Dt:
09/07/2001
Publication #:
Pub Dt:
03/13/2003
Title:
PHASE CHANGE MATERIAL MEMORY DEVICE
24
Patent #:
Issue Dt:
10/21/2003
Application #:
09949416
Filing Dt:
09/07/2001
Publication #:
Pub Dt:
01/17/2002
Title:
REFRACTORY METAL ROUGHNESS REDUCTION USING HIGH TEMPERATURE ANNEAL IN HYDRIDES OR ORGANO-SILANE AMBIENTS
25
Patent #:
Issue Dt:
06/07/2005
Application #:
09949683
Filing Dt:
09/10/2001
Publication #:
Pub Dt:
03/14/2002
Title:
METHOD AND APPARATUS FOR A SEMICONDUCTOR PACKAGE FOR VERTICAL SURFACE MOUNTING
26
Patent #:
Issue Dt:
01/27/2004
Application #:
09951152
Filing Dt:
09/12/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHODS OF FORMING TRANSISTORS ASSOCIATED WITH SEMICONDUCTOR SUBSTRATES
27
Patent #:
Issue Dt:
04/24/2007
Application #:
09951153
Filing Dt:
09/12/2001
Publication #:
Pub Dt:
04/25/2002
Title:
STRUCTURES COMPRISING A LAYER FREE OF NITROGEN BETWEEN SILICON NITRIDE AND PHOTORESIST
28
Patent #:
Issue Dt:
11/25/2003
Application #:
09951307
Filing Dt:
09/12/2001
Publication #:
Pub Dt:
01/17/2002
Title:
METHOD OF FORMING TRANSISTORS ASSOCIATED WITH SEMICONDUCTOR SUBSTRATES COMPRISING FORMING A NITROGEN-COMPRISING REGION ACROSS AN OXIDE REGION OF A TRANSISTOR GATE
29
Patent #:
Issue Dt:
03/04/2008
Application #:
09951904
Filing Dt:
09/14/2001
Publication #:
Pub Dt:
03/20/2003
Title:
SYSTEM AND METHOD FOR SPLIT AUTOMATIC GAIN CONTROL
30
Patent #:
Issue Dt:
03/25/2003
Application #:
09952123
Filing Dt:
09/11/2001
Publication #:
Pub Dt:
01/24/2002
Title:
METHOD OF FORMING A PSEUDO-DIFFERENTIAL CURRENT SENSE AMPLIFIER WITH HYSTERESIS
31
Patent #:
Issue Dt:
09/21/2004
Application #:
09952890
Filing Dt:
09/14/2001
Publication #:
Pub Dt:
02/07/2002
Title:
METHOD OF FABRICATION OF SEMICONDUCTOR STRUCTURES BY ION IMPLANTATION
32
Patent #:
Issue Dt:
02/25/2003
Application #:
09952957
Filing Dt:
09/12/2001
Publication #:
Pub Dt:
06/13/2002
Title:
METHOD AND CIRCUIT FOR PROGRAMMING A MULTILEVEL NON-VOLATILE MEMORY
33
Patent #:
Issue Dt:
05/13/2003
Application #:
09953070
Filing Dt:
09/13/2001
Publication #:
Pub Dt:
05/16/2002
Title:
READING CIRCUIT FOR SEMICONDUCTOR NON-VOLATILE MEMORIES
34
Patent #:
Issue Dt:
02/01/2005
Application #:
09953356
Filing Dt:
09/17/2001
Publication #:
Pub Dt:
03/20/2003
Title:
MEMORY SYSTEM ORGANIZED INTO BLOCKS OF DIFFERENT SIZES AND ALLOCATION METHOD THEREFOR
35
Patent #:
Issue Dt:
10/28/2003
Application #:
09953675
Filing Dt:
09/17/2001
Publication #:
Pub Dt:
06/06/2002
Title:
CONDUCTIVE STRUCTURE IN AN INTEGRATED CIRCUIT
36
Patent #:
Issue Dt:
03/01/2005
Application #:
09953833
Filing Dt:
09/17/2001
Publication #:
Pub Dt:
03/20/2003
Title:
REDUCING SHUNTS IN MEMORIES WITH PHASE-CHANGE MATERIAL
37
Patent #:
Issue Dt:
07/29/2003
Application #:
09954340
Filing Dt:
09/14/2001
Publication #:
Pub Dt:
04/18/2002
Title:
METHODS OF FORMING CAPACITORS, AND METHODS OF FORMING CAPACITOR-OVER-BIT LINE MEMORY CIRCUITRY, AND RELATED INTEGRATED CIRCUITRY CONSTRUCTIONS
38
Patent #:
Issue Dt:
01/08/2008
Application #:
09954402
Filing Dt:
09/11/2001
Publication #:
Pub Dt:
03/13/2003
Title:
EMBEDDED PCB IDENTIFICATION
39
Patent #:
Issue Dt:
09/03/2002
Application #:
09954552
Filing Dt:
09/17/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHOD AND APPARATUS FOR REDUCING BGA WARPAGE CAUSED BY ENCAPSULATION
40
Patent #:
Issue Dt:
02/25/2003
Application #:
09954600
Filing Dt:
09/11/2001
Publication #:
Pub Dt:
03/13/2003
Title:
METHODS OF PROGRAMMING AND CIRCUITRY FOR A PROGRAMMABLE ELEMENT
41
Patent #:
Issue Dt:
11/12/2002
Application #:
09954605
Filing Dt:
09/10/2001
Publication #:
Pub Dt:
02/14/2002
Title:
SELF-ALIGNED ETCH STOP FOR POLYCRYSTALLINE SILICON PLUGS ON A SEMICONDUCTOR DEVICE
42
Patent #:
Issue Dt:
08/13/2002
Application #:
09955072
Filing Dt:
09/19/2001
Publication #:
Pub Dt:
03/14/2002
Title:
SEMICONDUCTOR MEMORY HAVING MULTIPLE REDUNDANT COLUMNS WITH OFFSET SEGMENTATION BOUNDARIES
43
Patent #:
Issue Dt:
03/15/2005
Application #:
09955270
Filing Dt:
09/18/2001
Publication #:
Pub Dt:
03/21/2002
Title:
SUPPLY VOLTAGE REDUCTION CIRCUIT FOR INTEGRATED CIRCUIT
44
Patent #:
Issue Dt:
11/04/2003
Application #:
09955282
Filing Dt:
09/18/2001
Publication #:
Pub Dt:
03/20/2003
Title:
VARIABLE LEVEL MEMORY
45
Patent #:
Issue Dt:
09/09/2003
Application #:
09955503
Filing Dt:
09/18/2001
Publication #:
Pub Dt:
02/28/2002
Title:
USE OF SELECTIVE OZONE TEOS OXIDE TO CREATE VARIABLE THICKNESS LAYERS AND SPACERS
46
Patent #:
Issue Dt:
01/13/2004
Application #:
09955612
Filing Dt:
09/19/2001
Publication #:
Pub Dt:
05/02/2002
Title:
MICROELECTRONIC DEVICES AND MICROELECTRONIC DIE PACKAGES
47
Patent #:
Issue Dt:
12/16/2003
Application #:
09955613
Filing Dt:
09/19/2001
Publication #:
Pub Dt:
04/25/2002
Title:
METHOD AND APPARATUS FOR PACKAGING A MICROELECTRONIC DIE
48
Patent #:
Issue Dt:
11/25/2003
Application #:
09955620
Filing Dt:
09/19/2001
Publication #:
Pub Dt:
02/07/2002
Title:
METHOD AND APPARATUS FOR PACKAGING A MICROELECTRONIC DIE
49
Patent #:
Issue Dt:
06/24/2003
Application #:
09955846
Filing Dt:
09/18/2001
Publication #:
Pub Dt:
02/21/2002
Title:
PASSIVATION LAYER FOR PACKAGED INTEGRATED CIRCUITS
50
Patent #:
Issue Dt:
01/27/2004
Application #:
09955897
Filing Dt:
09/19/2001
Publication #:
Pub Dt:
05/02/2002
Title:
METHOD AND APPARATUS FOR PACKAGING A MICROELECTRONIC DIE
51
Patent #:
Issue Dt:
10/25/2005
Application #:
09956171
Filing Dt:
09/18/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHODS OF FORMING FIELD EFFECT TRANSISTORS AND FIELD EFFECT TRANSISTOR CIRCUITRY
52
Patent #:
Issue Dt:
09/19/2006
Application #:
09956783
Filing Dt:
09/20/2001
Publication #:
Pub Dt:
03/20/2003
Title:
ELECTRO-AND ELECTROLESS PLATING OF METAL IN THE MANUFACTURE OF PCRAM DEVICES
53
Patent #:
Issue Dt:
11/19/2002
Application #:
09956812
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
01/24/2002
Title:
VOLTAGE PUMP WITH DIODE FOR PRE-CHARGE
54
Patent #:
Issue Dt:
01/25/2005
Application #:
09960089
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
03/27/2003
Title:
BUMPING TECHNOLOGY IN STACKED DIE CONFIGURATIONS
55
Patent #:
Issue Dt:
08/27/2002
Application #:
09960119
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHODS OF FORMING INTEGRATED CIRCUITRY.
56
Patent #:
Issue Dt:
09/23/2003
Application #:
09960254
Filing Dt:
09/20/2001
Publication #:
Pub Dt:
04/11/2002
Title:
LATERAL DMOS TRANSISTOR WITH FIRST AND SECOND DRAIN ELECTRODES IN RESPECTIVE CONTACT WITH HIGH-AND LOW-CONCENTRATION PORTIONS OF A DRAIN REGION
57
Patent #:
Issue Dt:
10/29/2002
Application #:
09960818
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
01/31/2002
Title:
BUFFER LAYER IN FLAT PANEL DISPLAY
58
Patent #:
Issue Dt:
01/07/2003
Application #:
09960851
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
07/25/2002
Title:
CONTROL CIRCUIT FOR A VARIABLE-VOLTAGE REGULATOR OF A NONVOLATILE MEMORY WITH HIERARCHICAL ROW DECODING
59
Patent #:
Issue Dt:
07/24/2007
Application #:
09960912
Filing Dt:
09/21/2001
Publication #:
Pub Dt:
09/04/2003
Title:
BUFFER LAYER IN FLAT PANEL DISPLAY
60
Patent #:
Issue Dt:
08/31/2004
Application #:
09960945
Filing Dt:
09/25/2001
Publication #:
Pub Dt:
05/23/2002
Title:
DIE ATTACH CURING METHOD FOR SEMICONDUCTOR DEVICE
61
Patent #:
Issue Dt:
05/17/2005
Application #:
09961624
Filing Dt:
09/24/2001
Publication #:
Pub Dt:
06/13/2002
Title:
METHOD AND APPARATUS FOR INCREASING CHEMICAL-MECHANICAL-POLISHING SELECTIVITY
62
Patent #:
Issue Dt:
11/14/2006
Application #:
09963177
Filing Dt:
09/25/2001
Publication #:
Pub Dt:
03/27/2003
Title:
PROBABALISTIC NETWORKS FOR DETECTING SIGNAL CONTENT
63
Patent #:
Issue Dt:
06/17/2003
Application #:
09963291
Filing Dt:
09/25/2001
Publication #:
Pub Dt:
01/24/2002
Title:
METHOD AND APPARATUS FOR CONTROLLING CHEMICAL INTERACTIONS DURING PLANARIZATION OF MICROELECTRONIC SUBSTRATES
64
Patent #:
Issue Dt:
04/08/2003
Application #:
09964110
Filing Dt:
09/25/2001
Publication #:
Pub Dt:
03/27/2003
Title:
ANTIFUSE PROGRAMMING CURRENT LIMITER
65
Patent #:
Issue Dt:
11/16/2004
Application #:
09964113
Filing Dt:
09/25/2001
Publication #:
Pub Dt:
03/07/2002
Title:
METHOD AND APPARATUS FOR DATA COMPRESSION IN MEMORY DEVICES
66
Patent #:
Issue Dt:
08/06/2002
Application #:
09964134
Filing Dt:
09/25/2001
Publication #:
Pub Dt:
01/24/2002
Title:
DIE ARCHITECTURE ACCOMMODATING HIGH-SPEED SEMICONDUCTOR DEVICES
67
Patent #:
Issue Dt:
10/05/2004
Application #:
09964747
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
04/03/2003
Title:
EXTENSION MECHANISM AND METHOD FOR ASSEMBLING OVERHANGING COMPONENTS
68
Patent #:
Issue Dt:
08/05/2003
Application #:
09965209
Filing Dt:
09/26/2001
Publication #:
Pub Dt:
03/27/2003
Title:
REDUCED CURRENT ADDRESS SELECTION CIRCUIT AND METHOD
69
Patent #:
Issue Dt:
03/27/2007
Application #:
09965223
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
04/03/2003
Title:
GLOBAL I/O TIMING ADJUSTMENT USING CALIBRATED DELAY ELEMENTS
70
Patent #:
Issue Dt:
06/03/2003
Application #:
09965627
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
04/03/2003
Title:
DIGITAL UPDATE SCHEME FOR ADAPTIVE IMPEDANCE CONTROL OF ON-DIE INPUT/OUTPUT CIRCUITS
71
Patent #:
Issue Dt:
09/23/2003
Application #:
09966014
Filing Dt:
09/27/2001
Publication #:
Pub Dt:
03/27/2003
Title:
WRITE-ONCE POLYMER MEMORY WITH E-BEAM WRITING AND READING
72
Patent #:
Issue Dt:
12/02/2003
Application #:
09966699
Filing Dt:
09/27/2001
Publication #:
Pub Dt:
03/27/2003
Title:
METHODS OF FORMING MAGNETORESISTIVE DEVICES
73
Patent #:
Issue Dt:
01/06/2004
Application #:
09967060
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
04/03/2003
Title:
A ZERO INSERTION FORCE CONNECTOR FOR SUBSTRATES WITH EDGE CONTACTS
74
Patent #:
Issue Dt:
12/09/2003
Application #:
09967180
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
04/03/2003
Title:
RELEASING FUNCTIONAL BLOCKS IN RESPONSE TO A DETERMINATION OF A SUPPLY VOLTAGE PREDETERMINED LEVEL AND A LOGIC PREDETERMINED INITIAL STATE
75
Patent #:
Issue Dt:
02/08/2005
Application #:
09967367
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
07/17/2003
Title:
SOFTWARE CALL CONTROL AGENT
76
Patent #:
Issue Dt:
12/11/2007
Application #:
09968278
Filing Dt:
09/28/2001
Publication #:
Pub Dt:
04/03/2003
Title:
DUAL-TARGET BLOCK REGISTER ALLOCATION
77
Patent #:
Issue Dt:
11/25/2003
Application #:
09969464
Filing Dt:
10/01/2001
Publication #:
Pub Dt:
02/07/2002
Title:
METHOD AND STRUCTURE FOR AN OXIDE LAYER OVERLYING AN OXIDATION-RESISTANT LAYER
78
Patent #:
Issue Dt:
05/10/2005
Application #:
09970100
Filing Dt:
10/02/2001
Publication #:
Pub Dt:
02/14/2002
Title:
POLISHING PADS AND PLANARIZING MACHINES FOR MECHANICAL OR CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC-DEVICE SUBSTRATE ASSEMBLIES, AND METHODS FOR MAKING AND USING SUCH PADS AND MACHINES
79
Patent #:
Issue Dt:
06/01/2004
Application #:
09970275
Filing Dt:
10/02/2001
Publication #:
Pub Dt:
02/07/2002
Title:
METHODS OF PACKAGING AN INTEGRATED CIRCUIT
80
Patent #:
Issue Dt:
04/10/2007
Application #:
09970485
Filing Dt:
10/03/2001
Publication #:
Pub Dt:
04/03/2003
Title:
REMOVING REDUNDANT INFORMATION IN HYBRID BRANCH PREDICTION
81
Patent #:
Issue Dt:
03/02/2004
Application #:
09971250
Filing Dt:
10/04/2001
Publication #:
Pub Dt:
04/10/2003
Title:
ETCH STOP LAYER IN POLY-METAL STRUCTURES
82
Patent #:
Issue Dt:
12/02/2003
Application #:
09971758
Filing Dt:
10/04/2001
Publication #:
Pub Dt:
04/10/2003
Title:
METHODS OF MAKING MAGNETORESISTIVE MEMORY DEVICES
83
Patent #:
Issue Dt:
09/07/2004
Application #:
09971841
Filing Dt:
10/04/2001
Publication #:
Pub Dt:
04/10/2003
Title:
EMBEDDED DRAM CACHE MEMORY AND METHOD HAVING REDUCED LATENCY
84
Patent #:
Issue Dt:
08/24/2004
Application #:
09971851
Filing Dt:
10/04/2001
Publication #:
Pub Dt:
03/14/2002
Title:
SEMICONDUCTOR PACKAGES AND METHODS FOR MAKING THE SAME
85
Patent #:
Issue Dt:
12/09/2003
Application #:
09971945
Filing Dt:
10/04/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHOD OF FORMING HAZE- FREE BST FILMS
86
Patent #:
Issue Dt:
02/22/2005
Application #:
09971952
Filing Dt:
10/04/2001
Publication #:
Pub Dt:
02/21/2002
Title:
SEMICONDUCTOR PACKAGES AND METHODS FOR MAKING THE SAME
87
Patent #:
Issue Dt:
02/15/2005
Application #:
09971955
Filing Dt:
10/04/2001
Publication #:
Pub Dt:
03/21/2002
Title:
HAZE-FREE BST FILMS
88
Patent #:
Issue Dt:
03/04/2003
Application #:
09972266
Filing Dt:
10/09/2001
Title:
METHOD FOR FABRICATING AN INTERCONNECT FOR MAKING TEMPORARY ELECTRICAL CONNECTIONS TO SEMICONDUCTOR COMPONENTS
89
Patent #:
Issue Dt:
02/04/2003
Application #:
09972426
Filing Dt:
10/05/2001
Title:
FLASH MEMORY DEVICE WITH A VARIABLE ERASE PULSE
90
Patent #:
Issue Dt:
01/18/2005
Application #:
09972649
Filing Dt:
10/10/2001
Publication #:
Pub Dt:
09/12/2002
Title:
DIE SUPPORT STRUCTURE
91
Patent #:
Issue Dt:
04/01/2003
Application #:
09972726
Filing Dt:
10/04/2001
Publication #:
Pub Dt:
04/25/2002
Title:
SMALL SIZE, LOW CONSUMPTION, MULTILEVEL NONVOLATILE MEMORY
92
Patent #:
Issue Dt:
04/15/2003
Application #:
09972753
Filing Dt:
10/05/2001
Publication #:
Pub Dt:
06/06/2002
Title:
CONTROL AND TIMING STRUCTURE FOR A MEMORY
93
Patent #:
Issue Dt:
06/17/2003
Application #:
09972769
Filing Dt:
10/05/2001
Publication #:
Pub Dt:
06/06/2002
Title:
SEMICONDUCTOR MEMORY ARCHITECTURE
94
Patent #:
Issue Dt:
01/27/2004
Application #:
09973527
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
04/17/2003
Title:
SYSTEM AND METHOD OF TESTING NON-VOLATILE MEMORY CELLS
95
Patent #:
Issue Dt:
12/23/2003
Application #:
09973860
Filing Dt:
10/11/2001
Publication #:
Pub Dt:
04/17/2003
Title:
HIGH SPEED MEMORY ARCHITECTURE
96
Patent #:
Issue Dt:
04/29/2003
Application #:
09973999
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
02/21/2002
Title:
METHOD AND APPARATUS FOR SYNCHRONOUS DATA TRANSFERS IN A MEMORY DEVICE WITH SELECTABLE DATA OR ADDRESS PATHS
97
Patent #:
Issue Dt:
02/04/2003
Application #:
09974192
Filing Dt:
10/10/2001
Title:
PACKAGED STACKED SEMICONDUCTOR DIE AND METHOD OF PREPARING SAME
98
Patent #:
Issue Dt:
08/26/2003
Application #:
09974349
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
02/07/2002
Title:
METHOD AND APPARATUS FOR SYNCHRONOUS DATA TRANSFERS IN A MEMORY DEVICE WITH SELECTABLE DATA OR ADDRESS PATHS
99
Patent #:
Issue Dt:
09/07/2004
Application #:
09974350
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
02/07/2002
Title:
METHOD AND APPARATUS FOR SYNCHRONOUS DATA TRANSFERS IN A MEMORY DEVICE WITH SELECTABLE DATA OR ADDRESS PATHS
100
Patent #:
Issue Dt:
05/25/2004
Application #:
09974364
Filing Dt:
10/09/2001
Publication #:
Pub Dt:
04/10/2003
Title:
EMBEDDED MEMORY SYSTEM AND METHOD INCLUDING DATA ERROR CORRECTION
Assignor
1
Exec Dt:
07/31/2019
Assignee
1
8000 S FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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