skip navigationU S P T O SealUnited States Patent and Trademark Office AOTW logo
Home|Site Index|Search|Guides|Contacts|eBusiness|eBiz alerts|News|Help
Assignments on the Web > Patent Query
Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:050937/0001   Pages: 964
Recorded: 10/09/2019
Attorney Dkt #:4816.244
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
Total properties: 18018
Page 60 of 181
Pages: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181
1
Patent #:
6829177
Issue Dt:
12/07/2004
Application #:
10161055
Filing Dt:
05/30/2002
Publication #:
US20030059997
Pub Dt:
03/27/2003
Title:
OUTPUT BUFFER FOR A NONVOLATILE MEMORY WITH OPTIMIZED SLEW-RATE CONTROL
2
Patent #:
7435688
Issue Dt:
10/14/2008
Application #:
10161134
Filing Dt:
05/30/2002
Publication #:
US20020151160
Pub Dt:
10/17/2002
Title:
SEMICONDUCTOR PROCESSING METHODS OF TRANSFERRING PATTERNS FROM PATTERNED PHOTORESISTS TO MATERIALS, AND STRUCTURES COMPRISING SILICON NITRIDE
3
Patent #:
6858523
Issue Dt:
02/22/2005
Application #:
10161136
Filing Dt:
05/30/2002
Publication #:
US20020146910
Pub Dt:
10/10/2002
Title:
SEMICONDUCTOR PROCESSING METHODS OF TRANSFERRING PATTERNS FROM PATTERNED PHOTORESISTS TO MATERIALS, AND STRUCTURES COMPRISING SILICON NITRIDE
4
Patent #:
7190394
Issue Dt:
03/13/2007
Application #:
10161439
Filing Dt:
06/04/2002
Publication #:
US20030222992
Pub Dt:
12/04/2003
Title:
METHOD FOR STATISTICAL ANALYSIS OF IMAGES FOR AUTOMATIC WHITE BALANCE OF COLOR CHANNEL GAINS FOR IMAGE SENSORS
5
Patent #:
6731550
Issue Dt:
05/04/2004
Application #:
10161501
Filing Dt:
05/31/2002
Publication #:
US20030223282
Pub Dt:
12/04/2003
Title:
REDUNDANCY CIRCUIT AND METHOD FOR SEMICONDUCTOR MEMORY DEVICES
6
Patent #:
7189606
Issue Dt:
03/13/2007
Application #:
10161615
Filing Dt:
06/05/2002
Publication #:
US20030227056
Pub Dt:
12/11/2003
Title:
METHOD OF FORMING FULLY-DEPLETED (FD) (SOI) MOSFET ACCESS TRANSISTOR
7
Patent #:
6501165
Issue Dt:
12/31/2002
Application #:
10161839
Filing Dt:
06/03/2002
Title:
STACKABLE SEMICONDUCTOR PACKAGE HAVING CONDUCTIVE LAYER AND INSULATING LAYERS AND METHOD OF FABRICATION
8
Patent #:
6605985
Issue Dt:
08/12/2003
Application #:
10162135
Filing Dt:
06/03/2002
Publication #:
US20030034827
Pub Dt:
02/20/2003
Title:
HIGH-EFFICIENCY POWER CHARGE PUMP SUPPLYING HIGH DC OUTPUT CURRENTS
9
Patent #:
6784062
Issue Dt:
08/31/2004
Application #:
10162289
Filing Dt:
06/03/2002
Publication #:
US20030224574
Pub Dt:
12/04/2003
Title:
TRANSISTOR FORMATION FOR SEMICONDUCTOR DEVICES
10
Patent #:
6606270
Issue Dt:
08/12/2003
Application #:
10162354
Filing Dt:
06/03/2002
Publication #:
US20020149966
Pub Dt:
10/17/2002
Title:
DEVICE AND METHOD FOR SUPPLYING CURRENT TO A SEMICONDUCTOR MEMORY TO SUPPORT A BOOSTED VOLTAGE WITHIN THE MEMORY DURING TESTING
11
Patent #:
6835659
Issue Dt:
12/28/2004
Application #:
10163285
Filing Dt:
06/04/2002
Publication #:
US20030224597
Pub Dt:
12/04/2003
Title:
ELECTRICAL COUPLING STACK AND PROCESSES FOR MAKING SAME
12
Patent #:
6614116
Issue Dt:
09/02/2003
Application #:
10163289
Filing Dt:
06/04/2002
Title:
BURIED DIGIT LINE STACK AND PROCESS FOR MAKING SAME
13
Patent #:
6522577
Issue Dt:
02/18/2003
Application #:
10163476
Filing Dt:
06/05/2002
Title:
SYSTEM AND METHOD FOR ENABLING CHIP LEVEL ERASING AND WRITING FOR MAGNETIC RANDOM ACCESS MEMORY DEVICES
14
Patent #:
7205218
Issue Dt:
04/17/2007
Application #:
10163686
Filing Dt:
06/05/2002
Publication #:
US20030228747
Pub Dt:
12/11/2003
Title:
Method including forming gate dielectrics having multiple lanthanide oxide layers
15
Patent #:
6812095
Issue Dt:
11/02/2004
Application #:
10164048
Filing Dt:
06/04/2002
Publication #:
US20030137004
Pub Dt:
07/24/2003
Title:
METHODS OF FORMING FORMING FLOATING GATE TRANSISTORS USING STI
16
Patent #:
6910874
Issue Dt:
06/28/2005
Application #:
10164086
Filing Dt:
06/04/2002
Publication #:
US20020173070
Pub Dt:
11/21/2002
Title:
APPARATUS FOR ENCAPSULATING A MULTI-CHIP SUBSTRATE ARRAY
17
Patent #:
6633183
Issue Dt:
10/14/2003
Application #:
10164115
Filing Dt:
06/05/2002
Publication #:
US20020149391
Pub Dt:
10/17/2002
Title:
ANTIFUSE REROUTE OF DIES
18
Patent #:
RE38685
Issue Dt:
01/11/2005
Application #:
10164354
Filing Dt:
06/05/2002
Title:
DATA-OUTPUT DRIVER CIRCUIT AND METHOD
19
Patent #:
7101778
Issue Dt:
09/05/2006
Application #:
10164475
Filing Dt:
06/06/2002
Publication #:
US20020145901
Pub Dt:
10/10/2002
Title:
NOVEL TRANSMISSION LINES FOR CMOS INTEGRATED CIRCUITS
20
Patent #:
6900521
Issue Dt:
05/31/2005
Application #:
10164611
Filing Dt:
06/10/2002
Publication #:
US20030227072
Pub Dt:
12/11/2003
Title:
VERTICAL TRANSISTORS AND OUTPUT PREDICTION LOGIC CIRCUITS CONTAINING SAME
21
Patent #:
6825135
Issue Dt:
11/30/2004
Application #:
10164646
Filing Dt:
06/06/2002
Publication #:
US20030228771
Pub Dt:
12/11/2003
Title:
ELIMINATION OF DENDRITE FORMATION DURING METAL/CHALCOGENIDE GLASS DEPOSITION
22
Patent #:
6917228
Issue Dt:
07/12/2005
Application #:
10164735
Filing Dt:
06/06/2002
Publication #:
US20030227308
Pub Dt:
12/11/2003
Title:
DELAY LOCKED LOOP CIRCUIT WITH TIME DELAY QUANTIFIER AND CONTROL
23
Patent #:
6754861
Issue Dt:
06/22/2004
Application #:
10164975
Filing Dt:
06/06/2002
Publication #:
US20020152437
Pub Dt:
10/17/2002
Title:
CIRCUITRY FOR AND SYSTEM AND SUBSTRATE WITH CIRCUITRY FOR ALIGNING OUTPUT SIGNALS IN MASSIVELY PARALLEL TESTERS AND OTHER ELECTRONIC DEVICES
24
Patent #:
6849464
Issue Dt:
02/01/2005
Application #:
10165301
Filing Dt:
06/10/2002
Publication #:
US20030228710
Pub Dt:
12/11/2003
Title:
MULTILAYER DIELECTRIC TUNNEL BARRIER USED IN MAGNETIC TUNNEL JUNCTION DEVICES, AND ITS METHOD OF FABRICATION
25
Patent #:
6781907
Issue Dt:
08/24/2004
Application #:
10165665
Filing Dt:
06/06/2002
Publication #:
US20030227792
Pub Dt:
12/11/2003
Title:
TEMPERATURE COMPENSATED T-RAM MEMORY DEVICE AND METHOD
26
Patent #:
6836145
Issue Dt:
12/28/2004
Application #:
10165666
Filing Dt:
06/06/2002
Publication #:
US20030227294
Pub Dt:
12/11/2003
Title:
PROGRAMMING CIRCUIT AND METHOD HAVING EXTENDED DURATION PROGRAMMING CAPABILITIES
27
Patent #:
6822886
Issue Dt:
11/23/2004
Application #:
10166696
Filing Dt:
06/12/2002
Publication #:
US20030058673
Pub Dt:
03/27/2003
Title:
REDUCING SIGNAL SWING IN A MATCH DETECTION CIRCUIT
28
Patent #:
6891415
Issue Dt:
05/10/2005
Application #:
10167195
Filing Dt:
06/11/2002
Publication #:
US20030227305
Pub Dt:
12/11/2003
Title:
METHOD AND APPARATUS FOR ENABLING A TIMING SYNCHRONIZATION CIRCUIT
29
Patent #:
7579681
Issue Dt:
08/25/2009
Application #:
10167284
Filing Dt:
06/11/2002
Publication #:
US20030227079
Pub Dt:
12/11/2003
Title:
SUPER HIGH DENSITY MODULE WITH INTEGRATED WAFER LEVEL PACKAGES
30
Patent #:
6791893
Issue Dt:
09/14/2004
Application #:
10170161
Filing Dt:
06/12/2002
Publication #:
US20030231541
Pub Dt:
12/18/2003
Title:
REGULATING VOLTAGES IN SEMICONDUCTOR DEVICES
31
Patent #:
6691247
Issue Dt:
02/10/2004
Application #:
10170174
Filing Dt:
06/11/2002
Publication #:
US20030084370
Pub Dt:
05/01/2003
Title:
CIRCUIT AND METHOD FOR MASKING A DORMANT MEMORY CELL
32
Patent #:
6889902
Issue Dt:
05/10/2005
Application #:
10170508
Filing Dt:
06/12/2002
Publication #:
US20020148897
Pub Dt:
10/17/2002
Title:
DESCRIPTOR FOR IDENTIFYING A DEFECTIVE DIE SITE AND METHODS OF FORMATION
33
Patent #:
6716716
Issue Dt:
04/06/2004
Application #:
10170748
Filing Dt:
06/13/2002
Publication #:
US20030073285
Pub Dt:
04/17/2003
Title:
EVEN NUCLEATION BETWEEN SILICON AND OXIDE SURFACES FOR THIN SILICON NITRIDE FILM GROWTH
34
Patent #:
7133999
Issue Dt:
11/07/2006
Application #:
10171049
Filing Dt:
06/12/2002
Publication #:
US20030191922
Pub Dt:
10/09/2003
Title:
METHOD AND SYSTEM FOR LOCAL MEMORY ADDRESSING IN SINGLE INSTRUCTION, MULTIPLE DATA COMPUTER SYSTEM
35
Patent #:
6654287
Issue Dt:
11/25/2003
Application #:
10171078
Filing Dt:
06/12/2002
Publication #:
US20020186594
Pub Dt:
12/12/2002
Title:
METHOD OF RE-PROGRAMMING AN ARRAY OF NON-VOLATILE MEMORY CELLS, IN PARTICULAR OF THE NOR ARCHITECTURE FLASH TYPE, AFTER AN ERASE OPERATION, AND A CORRESPONDING MEMORY DEVICE
36
Patent #:
6677681
Issue Dt:
01/13/2004
Application #:
10172157
Filing Dt:
06/14/2002
Publication #:
US20020151176
Pub Dt:
10/17/2002
Title:
CARRIER SUBSTRATE AND CARRIER ASSEMBLY USING RESIDUAL ORGANIC COMPOUNDS TO FACILITATE GATE BREAK
37
Patent #:
6605502
Issue Dt:
08/12/2003
Application #:
10172895
Filing Dt:
06/17/2002
Publication #:
US20020155698
Pub Dt:
10/24/2002
Title:
ISOLATION USING AN ANTIREFLECTIVE COATING
38
Patent #:
7138711
Issue Dt:
11/21/2006
Application #:
10172922
Filing Dt:
06/17/2002
Publication #:
US20030230799
Pub Dt:
12/18/2003
Title:
INTRINSIC THERMAL ENHANCEMENT FOR FBGA PACKAGE
39
Patent #:
6673707
Issue Dt:
01/06/2004
Application #:
10173935
Filing Dt:
06/17/2002
Publication #:
US20020158321
Pub Dt:
10/31/2002
Title:
METHOD OF FORMING SEMICONDUCTOR DEVICE UTILIZING DIE ACTIVE SURFACES FOR LATERALLY EXTENDING DIE INTERNAL AND EXTERNAL CONNECTIONS
40
Patent #:
6599832
Issue Dt:
07/29/2003
Application #:
10174164
Filing Dt:
06/17/2002
Publication #:
US20020155696
Pub Dt:
10/24/2002
Title:
SILICIDE PATTERN STRUCTURES AND METHODS OF FABRICATING THE SAME
41
Patent #:
6744669
Issue Dt:
06/01/2004
Application #:
10174193
Filing Dt:
06/17/2002
Publication #:
US20030006742
Pub Dt:
01/09/2003
Title:
MEMORY CIRCUIT INCLUDING BOOSTER PUMP FOR PROGRAMMING VOLTAGE GENERATION
42
Patent #:
6600343
Issue Dt:
07/29/2003
Application #:
10174206
Filing Dt:
06/17/2002
Publication #:
US20020149399
Pub Dt:
10/17/2002
Title:
HIGH SPEED LOW POWER INPUT BUFFER
43
Patent #:
6538918
Issue Dt:
03/25/2003
Application #:
10174214
Filing Dt:
06/17/2002
Publication #:
US20020154539
Pub Dt:
10/24/2002
Title:
PULSED WRITE TECHNIQUES FOR MAGNETO-RESISTIVE MEMORIES
44
Patent #:
6532168
Issue Dt:
03/11/2003
Application #:
10174215
Filing Dt:
06/17/2002
Title:
PULSED WRITE TECHNIQUES FOR MAGNETO-RESISTIVE MEMORIES
45
Patent #:
7420239
Issue Dt:
09/02/2008
Application #:
10174434
Filing Dt:
06/17/2002
Publication #:
US20020192975
Pub Dt:
12/19/2002
Title:
DIELECTRIC LAYER FORMING METHOD AND DEVICES FORMED THEREWITH
46
Patent #:
6787413
Issue Dt:
09/07/2004
Application #:
10174436
Filing Dt:
06/17/2002
Publication #:
US20020192979
Pub Dt:
12/19/2002
Title:
CAPACITOR STRUCTURE FORMING METHODS
47
Patent #:
6785167
Issue Dt:
08/31/2004
Application #:
10174746
Filing Dt:
06/18/2002
Publication #:
US20030231519
Pub Dt:
12/18/2003
Title:
ROM EMBEDDED DRAM WITH PROGRAMMING
48
Patent #:
6693844
Issue Dt:
02/17/2004
Application #:
10174747
Filing Dt:
06/18/2002
Publication #:
US20020154566
Pub Dt:
10/24/2002
Title:
SENDING SIGNAL THROUGH INTEGRATED CIRCUIT DURING SETUP TIME
49
Patent #:
6678199
Issue Dt:
01/13/2004
Application #:
10175271
Filing Dt:
06/19/2002
Publication #:
US20030235102
Pub Dt:
12/25/2003
Title:
MEMORY DEVICE WITH SENSE AMP EQUILIBRATION CIRCUIT
50
Patent #:
6798055
Issue Dt:
09/28/2004
Application #:
10175291
Filing Dt:
06/20/2002
Publication #:
US20020153604
Pub Dt:
10/24/2002
Title:
DIE SUPPORT STRUCTURE
51
Patent #:
6636450
Issue Dt:
10/21/2003
Application #:
10175723
Filing Dt:
06/20/2002
Publication #:
US20020154563
Pub Dt:
10/24/2002
Title:
FUSE READ SEQUENCE FOR AUTO REFRESH POWER REDUCTION
52
Patent #:
6812103
Issue Dt:
11/02/2004
Application #:
10175774
Filing Dt:
06/20/2002
Publication #:
US20030234422
Pub Dt:
12/25/2003
Title:
METHODS OF FABRICATING A DIELECTRIC PLUG IN MOSFETS TO SUPPRESS SHORT-CHANNEL EFFECTS
53
Patent #:
6844118
Issue Dt:
01/18/2005
Application #:
10175832
Filing Dt:
06/21/2002
Publication #:
US20020160280
Pub Dt:
10/31/2002
Title:
METHOD AND LAYOUT FOR HIGH DENSITY RETICLE
54
Patent #:
6816402
Issue Dt:
11/09/2004
Application #:
10175844
Filing Dt:
06/21/2002
Publication #:
US20030235068
Pub Dt:
12/25/2003
Title:
ROW AND COLUMN LINE GEOMETRIES FOR IMPROVING MRAM WRITE OPERATIONS
55
Patent #:
7005697
Issue Dt:
02/28/2006
Application #:
10175861
Filing Dt:
06/21/2002
Publication #:
US20030235064
Pub Dt:
12/25/2003
Title:
METHOD OF FORMING A NON-VOLATILE ELECTRON STORAGE MEMORY AND THE RESULTING DEVICE
56
Patent #:
6587382
Issue Dt:
07/01/2003
Application #:
10175928
Filing Dt:
06/19/2002
Title:
NONVOLATILE MEMORY USING FLEXIBLE ERASING METHODS AND METHOD AND SYSTEM FOR USING SAME
57
Patent #:
6524901
Issue Dt:
02/25/2003
Application #:
10176228
Filing Dt:
06/20/2002
Title:
METHOD FOR FORMING A NOTCHED DAMASCENE PLANAR POLY/METAL GATE
58
Patent #:
6967348
Issue Dt:
11/22/2005
Application #:
10176330
Filing Dt:
06/20/2002
Publication #:
US20030235929
Pub Dt:
12/25/2003
Title:
SIGNAL SHARING CIRCUIT WITH MICROELECTRONIC DIE ISOLATION FEATURES
59
Patent #:
6574144
Issue Dt:
06/03/2003
Application #:
10176425
Filing Dt:
06/18/2002
Publication #:
US20020159292
Pub Dt:
10/31/2002
Title:
FLASH MEMORY WITH NANOCRYSTALLINE SILICON FILM FLOATING GATE
60
Patent #:
6621316
Issue Dt:
09/16/2003
Application #:
10176865
Filing Dt:
06/20/2002
Title:
SYNCHRONOUS MIRROR DELAY (SMD) CIRCUIT AND METHOD INCLUDING A COUNTER AND REDUCED SIZE BI-DIRECTIONAL DELAY LINE
61
Patent #:
6700819
Issue Dt:
03/02/2004
Application #:
10176954
Filing Dt:
06/20/2002
Publication #:
US20030016572
Pub Dt:
01/23/2003
Title:
MEMORY WITH IMPROVED DIFFERENTIAL READING SYSTEM
62
Patent #:
6703272
Issue Dt:
03/09/2004
Application #:
10177054
Filing Dt:
06/21/2002
Publication #:
US20030235945
Pub Dt:
12/25/2003
Title:
METHODS OF FORMING SPACED CONDUCTIVE REGIONS, AND METHODS OF FORMING CAPACITOR CONSTRUCTIONS
63
Patent #:
6780728
Issue Dt:
08/24/2004
Application #:
10177056
Filing Dt:
06/21/2002
Publication #:
US20030234433
Pub Dt:
12/25/2003
Title:
SEMICONDUCTOR CONSTRUCTIONS, AND METHODS OF FORMING SEMICONDUCTOR CONSTRUCTIONS
64
Patent #:
6804136
Issue Dt:
10/12/2004
Application #:
10177077
Filing Dt:
06/21/2002
Publication #:
US20030235085
Pub Dt:
12/25/2003
Title:
WRITE ONCE READ ONLY MEMORY EMPLOYING CHARGE TRAPPING IN INSULATORS
65
Patent #:
6970370
Issue Dt:
11/29/2005
Application #:
10177082
Filing Dt:
06/21/2002
Publication #:
US20030235066
Pub Dt:
12/25/2003
Title:
FERROELECTRIC WRITE ONCE READ ONLY MEMORY FOR ARCHIVAL STORAGE
66
Patent #:
7193893
Issue Dt:
03/20/2007
Application #:
10177083
Filing Dt:
06/21/2002
Publication #:
US20030235077
Pub Dt:
12/25/2003
Title:
WRITE ONCE READ ONLY MEMORY EMPLOYING FLOATING GATES
67
Patent #:
7135734
Issue Dt:
11/14/2006
Application #:
10177096
Filing Dt:
06/21/2002
Publication #:
US20030048666
Pub Dt:
03/13/2003
Title:
GRADED COMPOSITION METAL OXIDE TUNNEL BARRIER INTERPOLY INSULATORS
68
Patent #:
6853587
Issue Dt:
02/08/2005
Application #:
10177208
Filing Dt:
06/21/2002
Publication #:
US20030235075
Pub Dt:
12/25/2003
Title:
VERTICAL NROM HAVING A STORAGE DENSITY OF 1BIT PER 1F2
69
Patent #:
7154140
Issue Dt:
12/26/2006
Application #:
10177213
Filing Dt:
06/21/2002
Publication #:
US20030234420
Pub Dt:
12/25/2003
Title:
WRITE ONCE READ ONLY MEMORY WITH LARGE WORK FUNCTION FLOATING GATES
70
Patent #:
6888739
Issue Dt:
05/03/2005
Application #:
10177214
Filing Dt:
06/21/2002
Publication #:
US20030235081
Pub Dt:
12/25/2003
Title:
NANOCRYSTAL WRITE ONCE READ ONLY MEMORY FOR ARCHIVAL STORAGE
71
Patent #:
6996009
Issue Dt:
02/07/2006
Application #:
10177483
Filing Dt:
06/21/2002
Publication #:
US20030235079
Pub Dt:
12/25/2003
Title:
NOR FLASH MEMORY CELL WITH HIGH STORAGE DENSITY
72
Patent #:
6651127
Issue Dt:
11/18/2003
Application #:
10177623
Filing Dt:
06/24/2002
Publication #:
US20020178393
Pub Dt:
11/28/2002
Title:
METHOD OF DETECTING TERMINATION OF A BUS TRANSFER OPERATION
73
Patent #:
6630685
Issue Dt:
10/07/2003
Application #:
10178111
Filing Dt:
06/24/2002
Title:
PROBE LOOK AHEAD: TESTING PARTS NOT CURRENTLY UNDER A PROBEHEAD
74
Patent #:
6909196
Issue Dt:
06/21/2005
Application #:
10178172
Filing Dt:
06/21/2002
Publication #:
US20030234448
Pub Dt:
12/25/2003
Title:
METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS
75
Patent #:
6933221
Issue Dt:
08/23/2005
Application #:
10178703
Filing Dt:
06/24/2002
Title:
METHOD FOR UNDERFILLING SEMICONDUCTOR COMPONENTS USING NO FLOW UNDERFILL
76
Patent #:
6934192
Issue Dt:
08/23/2005
Application #:
10178796
Filing Dt:
06/24/2002
Publication #:
US20030035329
Pub Dt:
02/20/2003
Title:
EEPROM MEMORY PROTECTED AGAINST THE EFFECTS FROM A BREAKDOWN OF AN ACCESS TRANSISTOR
77
Patent #:
6611165
Issue Dt:
08/26/2003
Application #:
10178961
Filing Dt:
06/25/2002
Title:
ANTIFUSE CIRCUIT WITH IMPROVED GATE OXIDE RELIABILITY
78
Patent #:
6808989
Issue Dt:
10/26/2004
Application #:
10179122
Filing Dt:
06/25/2002
Publication #:
US20020197798
Pub Dt:
12/26/2002
Title:
SELF-ALIGNED FLOATING GATE FLASH CELL SYSTEM AND METHOD
79
Patent #:
6959358
Issue Dt:
10/25/2005
Application #:
10179383
Filing Dt:
06/26/2002
Publication #:
US20030009618
Pub Dt:
01/09/2003
Title:
DISTRIBUTED CONTENT ADDRESSABLE MEMORY
80
Patent #:
6683808
Issue Dt:
01/27/2004
Application #:
10179553
Filing Dt:
06/24/2002
Publication #:
US20020163833
Pub Dt:
11/07/2002
Title:
STRING PROGRAMMABLE NONVOLATILE MEMORY WITH NOR ARCHITECTURE
81
Patent #:
6801073
Issue Dt:
10/05/2004
Application #:
10179606
Filing Dt:
06/25/2002
Publication #:
US20030234674
Pub Dt:
12/25/2003
Title:
SYSTEM, CIRCUIT AND METHOD FOR LOW VOLTAGE OPERABLE, SMALL FOOTPRINT DELAY
82
Patent #:
7530066
Issue Dt:
05/05/2009
Application #:
10179790
Filing Dt:
06/24/2002
Publication #:
US20040015969
Pub Dt:
01/22/2004
Title:
CONTROLLING SNOOP ACTIVITIES USING TASK TABLE IN MULTIPROCESSOR SYSTEM
83
Patent #:
6759298
Issue Dt:
07/06/2004
Application #:
10179868
Filing Dt:
06/24/2002
Publication #:
US20030235963
Pub Dt:
12/25/2003
Title:
METHODS OF FORMING AN ARRAY OF FLASH FIELD EFFECT TRANSISTORS AND CIRCUITRY PERIPHERAL TO SUCH ARRAY
84
Patent #:
6746921
Issue Dt:
06/08/2004
Application #:
10179893
Filing Dt:
06/24/2002
Publication #:
US20030235956
Pub Dt:
12/25/2003
Title:
METHOD OF FORMING AN ARRAY OF FLASH FIELD EFFECT TRANSISTORS AND CIRCUITRY PERIPHERAL TO SUCH ARRAY
85
Patent #:
6579763
Issue Dt:
06/17/2003
Application #:
10179894
Filing Dt:
06/24/2002
Title:
METHODS OF FORMING AN ARRAY OF FLASH FIELD EFFECT TRANSISTORS AND CIRCUITRY PERIPHERAL TO THE ARRAY
86
Patent #:
6881260
Issue Dt:
04/19/2005
Application #:
10179946
Filing Dt:
06/25/2002
Publication #:
US20030233976
Pub Dt:
12/25/2003
Title:
PROCESS FOR DIRECT DEPOSITION OF ALD RHO2
87
Patent #:
7241662
Issue Dt:
07/10/2007
Application #:
10180415
Filing Dt:
06/24/2002
Publication #:
US20030235964
Pub Dt:
12/25/2003
Title:
REDUCTION OF FIELD EDGE THINNING IN PERIPHERAL DEVICES
88
Patent #:
6893905
Issue Dt:
05/17/2005
Application #:
10180847
Filing Dt:
06/26/2002
Publication #:
US20020190387
Pub Dt:
12/19/2002
Title:
METHOD OF FORMING SUBSTANTIALLY HILLOCK-FREE ALUMINUM-CONTAINING COMPONENTS
89
Patent #:
6731016
Issue Dt:
05/04/2004
Application #:
10183192
Filing Dt:
06/25/2002
Publication #:
US20020168832
Pub Dt:
11/14/2002
Title:
METHOD AND APPARATUS FOR MARKING MICROELECTRONIC DIES AND MICROELECTRONIC DEVICES
90
Patent #:
6865660
Issue Dt:
03/08/2005
Application #:
10183370
Filing Dt:
06/28/2002
Publication #:
US20040006680
Pub Dt:
01/08/2004
Title:
METHOD AND APPARATUS FOR GENERATING DETERMINISTIC, NON-REPEATING, PSEUDO-RANDOM ADDRESSES
91
Patent #:
6784544
Issue Dt:
08/31/2004
Application #:
10183705
Filing Dt:
06/25/2002
Title:
SEMICONDUCTOR COMPONENT HAVING CONDUCTORS WITH WIRE BONDABLE METALIZATION LAYERS
92
Patent #:
6727116
Issue Dt:
04/27/2004
Application #:
10183820
Filing Dt:
06/27/2002
Publication #:
US20030232460
Pub Dt:
12/18/2003
Title:
SEMICONDUCTOR DEVICES INCLUDING PERIPHERALLY LOCATED BOND PADS, ASSEMBLIES, PACKAGES, AND METHODS
93
Patent #:
6664175
Issue Dt:
12/16/2003
Application #:
10183852
Filing Dt:
06/28/2002
Publication #:
US20020158336
Pub Dt:
10/31/2002
Title:
Method of forming ruthenium interconnect for an integrated circuit
94
Patent #:
6744109
Issue Dt:
06/01/2004
Application #:
10184154
Filing Dt:
06/26/2002
Publication #:
US20040002179
Pub Dt:
01/01/2004
Title:
GLASS ATTACHMENT OVER MICRO-LENS ARRAYS
95
Patent #:
6737723
Issue Dt:
05/18/2004
Application #:
10184321
Filing Dt:
06/27/2002
Publication #:
US20020163044
Pub Dt:
11/07/2002
Title:
LOW DIELECTRIC CONSTANT SHALLOW TRENCH ISOLATION
96
Patent #:
6906415
Issue Dt:
06/14/2005
Application #:
10184340
Filing Dt:
06/27/2002
Publication #:
US20030230801
Pub Dt:
12/18/2003
Title:
SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES INCLUDING MULTIPLE SEMICONDUCTOR DEVICES AND METHODS
97
Patent #:
6784120
Issue Dt:
08/31/2004
Application #:
10184493
Filing Dt:
06/28/2002
Publication #:
US20020168874
Pub Dt:
11/14/2002
Title:
METHOD FOR PRETREATING A SUBSTRATE PRIOR TO APPLICATION OF A POLYMERIC COAT
98
Patent #:
6512695
Issue Dt:
01/28/2003
Application #:
10184546
Filing Dt:
06/28/2002
Publication #:
US20020167839
Pub Dt:
11/14/2002
Title:
FIELD PROGRAMMABLE LOGIC ARRAYS WITH TRANSISTORS WITH VERTICAL GATES
99
Patent #:
6756653
Issue Dt:
06/29/2004
Application #:
10184590
Filing Dt:
06/27/2002
Publication #:
US20020158322
Pub Dt:
10/31/2002
Title:
LOW DIELECTRIC CONSTANT SHALLOW TRENCH ISOLATION
100
Patent #:
6770537
Issue Dt:
08/03/2004
Application #:
10184592
Filing Dt:
06/27/2002
Publication #:
US20020164859
Pub Dt:
11/07/2002
Title:
LOW DIELECTRIC CONSTANT SHALLOW TRENCH ISOLATION METHOD
Assignor
1
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Exec Dt:
07/31/2019
Assignee
1
MICRON TECHNOLOGY, INC.
8000 S FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

Search Results as of: 05/14/2024 05:09 PM
If you have any comments or questions concerning the data displayed, contact PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified: August 25, 2017 v.2.6
| .HOME | INDEX| SEARCH | eBUSINESS | CONTACT US | PRIVACY STATEMENT