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Reel/Frame:	050937/0001			Pages:	964
		Recorded:	10/09/2019
Attorney Dkt #:	4816.244
Conveyance:	RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).

Total properties: 18018
Page 69 of 181
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Patent #:	6998667	Issue Dt:	02/14/2006	Application #:	10377904	Filing Dt:	02/27/2003
Publication #:	US20030160277	Pub Dt:	08/28/2003
Title:	SCALABLE GATE AND STORAGE DIELECTRIC

Patent #:	7087182	Issue Dt:	08/08/2006	Application #:	10378354	Filing Dt:	03/03/2003
Publication #:	US20030157807	Pub Dt:	08/21/2003
Title:	PROCESS OF FORMING AN ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY WITH AN OXIDE LAYER EXPOSED TO HYDROGEN AND NITROGEN

Patent #:	7112531	Issue Dt:	09/26/2006	Application #:	10378429	Filing Dt:	03/03/2003
Publication #:	US20030162346	Pub Dt:	08/28/2003
Title:	SILICON OXIDE CO-DEPOSITION/ETCHING PROCESS

Patent #:	6924197	Issue Dt:	08/02/2005	Application #:	10378568	Filing Dt:	03/03/2003
Publication #:	US20030157769	Pub Dt:	08/21/2003
Title:	METHOD OF FABRICATING AN INTEGRATED CIRCUIT WITH A DIELECTRIC LAYER EXPOSED TO A HYDROGEN-BEARING NITROGEN SOURCE

Patent #:	6921937	Issue Dt:	07/26/2005	Application #:	10378573	Filing Dt:	03/03/2003
Publication #:	US20030141536	Pub Dt:	07/31/2003
Title:	INTEGRATED CIRCUIT WITH A DIELECTRIC LAYER EXPOSED TO A HYDROGEN-BEARING NITROGEN SOURCE

Patent #:	7127622	Issue Dt:	10/24/2006	Application #:	10378692	Filing Dt:	03/04/2003
Publication #:	US20040174763	Pub Dt:	09/09/2004
Title:	MEMORY SUBSYSTEM VOLTAGE CONTROL AND METHOD

Patent #:	7619184	Issue Dt:	11/17/2009	Application #:	10378757	Filing Dt:	03/04/2003
Publication #:	US20040173599	Pub Dt:	09/09/2004
Title:	MULTI-PARAMETER PROCESS AND CONTROL METHOD

Patent #:	7074717	Issue Dt:	07/11/2006	Application #:	10378796	Filing Dt:	03/04/2003
Publication #:	US20040173912	Pub Dt:	09/09/2004
Title:	DAMASCENE PROCESSES FOR FORMING CONDUCTIVE STRUCTURES

Patent #:	6841478	Issue Dt:	01/11/2005	Application #:	10378934	Filing Dt:	03/05/2003
Publication #:	US20030160330	Pub Dt:	08/28/2003
Title:	Method of forming a multi-layered copper bond pad for an integrated circuit

Patent #:	6670550	Issue Dt:	12/30/2003	Application #:	10379218	Filing Dt:	03/04/2003
Publication #:	US20030141091	Pub Dt:	07/31/2003
Title:	UNDERFILL COATING FOR LOC PACKAGE

Patent #:	6956256	Issue Dt:	10/18/2005	Application #:	10379478	Filing Dt:	03/04/2003
Publication #:	US20040174734	Pub Dt:	09/09/2004
Title:	VERTICAL GAIN CELL

Patent #:	7198974	Issue Dt:	04/03/2007	Application #:	10379749	Filing Dt:	03/05/2003
Publication #:	US20040173798	Pub Dt:	09/09/2004
Title:	MICRO-MECHANICALLY STRAINED SEMICONDUCTOR FILM

Patent #:	6852627	Issue Dt:	02/08/2005	Application #:	10379890	Filing Dt:	03/05/2003
Publication #:	US20040173909	Pub Dt:	09/09/2004
Title:	CONDUCTIVE THROUGH WAFER VIAS

Patent #:	7153779	Issue Dt:	12/26/2006	Application #:	10382019	Filing Dt:	03/05/2003
Publication #:	US20030162395	Pub Dt:	08/28/2003
Title:	METHOD TO ELIMINATE STRIATIONS AND SURFACE ROUGHNESS CAUSED BY DRY ETCH

Patent #:	6906408	Issue Dt:	06/14/2005	Application #:	10382025	Filing Dt:	03/05/2003
Publication #:	US20030160321	Pub Dt:	08/28/2003
Title:	ASSEMBLIES AND PACKAGES INCLUDING DIE TO DIE CONNECTIONS

Patent #:	7268425	Issue Dt:	09/11/2007	Application #:	10382680	Filing Dt:	03/05/2003
Publication #:	US20040173901	Pub Dt:	09/09/2004
Title:	THERMALLY ENHANCED ELECTRONIC FLIP-CHIP PACKAGING WITH EXTERNAL-CONNECTOR SIDE DIE AND METHOD

Patent #:	6777289	Issue Dt:	08/17/2004	Application #:	10382801	Filing Dt:	03/05/2003
Publication #:	US20030143806	Pub Dt:	07/31/2003
Title:	PROCESSING METHODS OF FORMING AN ELECTRICALLY CONDUCTIVE PLUG TO A NODE LOCATION

Patent #:	6713861	Issue Dt:	03/30/2004	Application #:	10382835	Filing Dt:	03/07/2003
Publication #:	US20030183952	Pub Dt:	10/02/2003
Title:	METHOD OF REMOVING FREE HALOGEN FROM A HALOGENATED POLYMER INSULATING LAYER OF A SEMICONDUCTOR DEVICE AND RESULTING SEMICONDUCTOR DEVICE

Patent #:	7348652	Issue Dt:	03/25/2008	Application #:	10383893	Filing Dt:	03/07/2003
Publication #:	US20040173867	Pub Dt:	09/09/2004
Title:	BULK-ISOLATED PN DIODE AND METHOD OF FORMING A BULK-ISOLATED PN DIODE

Patent #:	7209359	Issue Dt:	04/24/2007	Application #:	10385004	Filing Dt:	03/10/2003
Publication #:	US20030179554	Pub Dt:	09/25/2003
Title:	UNIVERSAL MEMORY MODULE/PCB STORAGE, TRANSPORT, AUTOMATION HANDLING TRAY

Patent #:	6870714	Issue Dt:	03/22/2005	Application #:	10385858	Filing Dt:	03/12/2003
Publication #:	US20040180237	Pub Dt:	09/16/2004
Title:	OXIDE BUFFER LAYER FOR IMPROVED MAGNETIC TUNNEL JUNCTIONS

Patent #:	6813178	Issue Dt:	11/02/2004	Application #:	10386028	Filing Dt:	03/12/2003
Publication #:	US20040179390	Pub Dt:	09/16/2004
Title:	CHALCOGENIDE GLASS CONSTANT CURRENT DEVICE, AND ITS METHOD OF FABRICATION AND OPERATION

Patent #:	6856009	Issue Dt:	02/15/2005	Application #:	10386254	Filing Dt:	03/11/2003
Publication #:	US20040178488	Pub Dt:	09/16/2004
Title:	TECHNIQUES FOR PACKAGING MULTIPLE DEVICE COMPONENTS

Patent #:	7122404	Issue Dt:	10/17/2006	Application #:	10386261	Filing Dt:	03/11/2003
Publication #:	US20040178482	Pub Dt:	09/16/2004
Title:	TECHNIQUES FOR PACKAGING A MULTIPLE DEVICE COMPONENT

Patent #:	7183485	Issue Dt:	02/27/2007	Application #:	10386757	Filing Dt:	03/11/2003
Publication #:	US20040177984	Pub Dt:	09/16/2004
Title:	MICROELECTRONIC COMPONENT ASSEMBLIES HAVING LEAD FRAMES ADAPTED TO REDUCE PACKAGE BOW

Patent #:	6787917	Issue Dt:	09/07/2004	Application #:	10387036	Filing Dt:	03/12/2003
Publication #:	US20030164550	Pub Dt:	09/04/2003
Title:	APPARATUS FOR PACKAGE REDUCTION IN STACKED CHIP AND BOARD ASSEMBLIES

Patent #:	6900667	Issue Dt:	05/31/2005	Application #:	10387090	Filing Dt:	03/11/2003
Publication #:	US20040178826	Pub Dt:	09/16/2004
Title:	LOGIC CONSTRUCTIONS AND ELECTRONIC DEVICES

Patent #:	7216212	Issue Dt:	05/08/2007	Application #:	10387141	Filing Dt:	03/11/2003
Publication #:	US20030227801	Pub Dt:	12/11/2003
Title:	SEMICONDUCTOR MEMORY WITH SELF-REFRESH CAPABILITY

Patent #:	6847582	Issue Dt:	01/25/2005	Application #:	10387150	Filing Dt:	03/11/2003
Publication #:	US20040178824	Pub Dt:	09/16/2004
Title:	LOW SKEW CLOCK INPUT BUFFER AND METHOD

Patent #:	7387866	Issue Dt:	06/17/2008	Application #:	10387832	Filing Dt:	03/14/2003
Publication #:	US20030155626	Pub Dt:	08/21/2003
Title:	PHOTOLITHOGRAPHY PROCESS USING MULTIPLE ANTI-REFLECTIVE COATINGS

Patent #:	6765376	Issue Dt:	07/20/2004	Application #:	10388051	Filing Dt:	03/12/2003
Publication #:	US20030169608	Pub Dt:	09/11/2003
Title:	VOLTAGE CONVERTER SYSTEM AND METHOD HAVING A STABLE OUTPUT VOLTAGE

Patent #:	6865135	Issue Dt:	03/08/2005	Application #:	10388052	Filing Dt:	03/12/2003
Publication #:	US20040179419	Pub Dt:	09/16/2004
Title:	MULTI-FREQUENCY SYNCHRONIZING CLOCK SIGNAL GENERATOR

Patent #:	6788037	Issue Dt:	09/07/2004	Application #:	10388053	Filing Dt:	03/12/2003
Publication #:	US20030169609	Pub Dt:	09/11/2003
Title:	VOLTAGE CONVERTER SYSTEM AND METHOD HAVING A STABLE OUTPUT VOLTAGE

Patent #:	6900625	Issue Dt:	05/31/2005	Application #:	10388058	Filing Dt:	03/12/2003
Publication #:	US20030169610	Pub Dt:	09/11/2003
Title:	VOLTAGE CONVERTER SYSTEM AND METHOD HAVING A STABLE OUTPUT VOLTAGE

Patent #:	7019351	Issue Dt:	03/28/2006	Application #:	10388103	Filing Dt:	03/12/2003
Publication #:	US20040180487	Pub Dt:	09/16/2004
Title:	TRANSISTOR DEVICES, AND METHODS OF FORMING TRANSISTOR DEVICES AND CIRCUIT DEVICES

Patent #:	7022579	Issue Dt:	04/04/2006	Application #:	10388264	Filing Dt:	03/14/2003
Publication #:	US20040180533	Pub Dt:	09/16/2004
Title:	METHOD FOR FILLING VIA WITH METAL

Patent #:	7371608	Issue Dt:	05/13/2008	Application #:	10389433	Filing Dt:	03/14/2003
Publication #:	US20030162325	Pub Dt:	08/28/2003
Title:	METHOD OF FABRICATING A STACKED DIE HAVING A RECESS IN A DIE BGA PACKAGE

Patent #:	7146722	Issue Dt:	12/12/2006	Application #:	10389455	Filing Dt:	03/14/2003
Publication #:	US20030153103	Pub Dt:	08/14/2003
Title:	A METHOD OF FORMING A BOND PAD STRUCTURE

Patent #:	7071508	Issue Dt:	07/04/2006	Application #:	10389659	Filing Dt:	03/13/2003
Publication #:	US20030222300	Pub Dt:	12/04/2003
Title:	CAPACITOR CONSTRUCTIONS, SEMICONDUCTOR CONSTRUCTIONS, AND METHODS OF FORMING ELECTRICAL CONTACTS AND SEMICONDUCTOR CONSTRUCTIONS

Patent #:	6835980	Issue Dt:	12/28/2004	Application #:	10389910	Filing Dt:	03/18/2003
Publication #:	US20030181039	Pub Dt:	09/25/2003
Title:	SEMICONDUCTOR DEVICE WITH NOVEL FILM COMPOSITION

Patent #:	7149844	Issue Dt:	12/12/2006	Application #:	10390556	Filing Dt:	03/14/2003
Publication #:	US20030210585	Pub Dt:	11/13/2003
Title:	NON-VOLATILE MEMORY DEVICE

Patent #:	6906418	Issue Dt:	06/14/2005	Application #:	10390863	Filing Dt:	03/17/2003
Publication #:	US20040018713	Pub Dt:	01/29/2004
Title:	SEMICONDUCTOR COMPONENT HAVING ENCAPSULATED, BONDED, INTERCONNECT CONTACTS

Patent #:	6852999	Issue Dt:	02/08/2005	Application #:	10391067	Filing Dt:	03/17/2003
Publication #:	US20030178692	Pub Dt:	09/25/2003
Title:	REDUCED TERMINAL TESTING SYSTEM

Patent #:	6881606	Issue Dt:	04/19/2005	Application #:	10391080	Filing Dt:	03/18/2003
Publication #:	US20040183163	Pub Dt:	09/23/2004
Title:	METHOD FOR FORMING A PROTECTIVE LAYER FOR USE IN PACKAGING A SEMICONDUCTOR DIE

Patent #:	6885108	Issue Dt:	04/26/2005	Application #:	10391267	Filing Dt:	03/18/2003
Publication #:	US20040183210	Pub Dt:	09/23/2004
Title:	PROTECTIVE LAYERS FORMED ON SEMICONDUCTOR DEVICE COMPONENTS SO AS TO REDUCE OR ELIMINATE THE OCCURRENCE OF DELAMINATION THEREOF AND CRACKING THEREIN

Patent #:	6767690	Issue Dt:	07/27/2004	Application #:	10391310	Filing Dt:	03/17/2003
Publication #:	US20030162106	Pub Dt:	08/28/2003
Title:	METHODS OF FORMING PATTERNS ACROSS PHOTORESIST AND METHODS OF FORMING RADIATION-PATTERNING TOOLS

Patent #:	6921860	Issue Dt:	07/26/2005	Application #:	10391725	Filing Dt:	03/18/2003
Publication #:	US20040188123	Pub Dt:	09/30/2004
Title:	MICROELECTRONIC COMPONENT ASSEMBLIES HAVING EXPOSED CONTACTS

Patent #:	6884718	Issue Dt:	04/26/2005	Application #:	10391876	Filing Dt:	03/18/2003
Publication #:	US20040195606	Pub Dt:	10/07/2004
Title:	SEMICONDUCTOR MANUFACTURING PROCESS AND APPARATUS FOR MODIFYING IN-FILM STRESS OF THIN FILMS, AND PRODUCT FORMED THEREBY

Patent #:	6884691	Issue Dt:	04/26/2005	Application #:	10392047	Filing Dt:	03/18/2003
Publication #:	US20040185636	Pub Dt:	09/23/2004
Title:	METHOD OF FORMING A SUBSTRATE HAVING A SURFACE COMPRISING AT LEAST ONE OF PT, PD, CO AND AU IN AT LEAST ONE OF ELEMENTAL AND ALLOY FORMS

Patent #:	6791140	Issue Dt:	09/14/2004	Application #:	10393129	Filing Dt:	03/19/2003
Publication #:	US20040029370	Pub Dt:	02/12/2004
Title:	MEMORY TRANSISTOR STRUCTURE

Patent #:	7155370	Issue Dt:	12/26/2006	Application #:	10393223	Filing Dt:	03/20/2003
Publication #:	US20040186688	Pub Dt:	09/23/2004
Title:	REUSABLE, BUILT-IN SELF-TEST METHODOLOGY FOR COMPUTER SYSTEMS

Patent #:	6684303	Issue Dt:	01/27/2004	Application #:	10393240	Filing Dt:	03/20/2003
Publication #:	US20030191920	Pub Dt:	10/09/2003
Title:	METHOD AND DEVICE TO USE MEMORY ACCESS REQUEST TAGS

Patent #:	6839264	Issue Dt:	01/04/2005	Application #:	10393257	Filing Dt:	03/21/2003
Publication #:	US20030235091	Pub Dt:	12/25/2003
Title:	SEMICONDUCTOR DEVICE WITHOUT ADVERSE EFFECTS CAUSED BY INCLINATIONS OF WORD LINE AND BIT LINE

Patent #:	7183138	Issue Dt:	02/27/2007	Application #:	10393376	Filing Dt:	03/19/2003
Publication #:	US20050250251	Pub Dt:	11/10/2005
Title:	METHOD AND APPARATUS FOR DECOUPLING CONDUCTIVE PORTIONS OF A MICROELECTRONIC DEVICE PACKAGE

Patent #:	6746895	Issue Dt:	06/08/2004	Application #:	10394863	Filing Dt:	03/21/2003
Publication #:	US20030178748	Pub Dt:	09/25/2003
Title:	METHOD FOR ENCAPSULATING A MULTI-CHIP SUBSTRATE ARRAY

Patent #:	6853601	Issue Dt:	02/08/2005	Application #:	10395478	Filing Dt:	03/24/2003
Publication #:	US20030169632	Pub Dt:	09/11/2003
Title:	DEVICE FOR A MEMORY ARRAY BY STORING EACH BIT IN MULTIPLE MEMORY CELLS IN THE ARRAY

Patent #:	6873180	Issue Dt:	03/29/2005	Application #:	10395576	Filing Dt:	03/24/2003
Publication #:	US20030141897	Pub Dt:	07/31/2003
Title:	MULTI-ACCESS FIFO QUEUE

Patent #:	7206909	Issue Dt:	04/17/2007	Application #:	10395695	Filing Dt:	03/20/2003
Publication #:	US20040054844	Pub Dt:	03/18/2004
Title:	HOST MEMORY INTERFACE FOR A PARALLEL PROCESSOR

Patent #:	7319075	Issue Dt:	01/15/2008	Application #:	10396164	Filing Dt:	03/25/2003
Publication #:	US20030203639	Pub Dt:	10/30/2003
Title:	ETCHANT WITH SELECTIVITY FOR DOPED SILICON DIOXIDE OVER UNDOPED SILICON DIOXIDE AND SILICON NITRIDE, PROCESSES WHICH EMPLOY THE ETCHANT, AND STRUCTURES FORMED THEREBY

Patent #:	7405007	Issue Dt:	07/29/2008	Application #:	10396341	Filing Dt:	03/26/2003
Publication #:	US20030183527	Pub Dt:	10/02/2003
Title:	A SEMICONDUCTOR HAVING A SUBSTANTIALLY UNIFORM LAYER OF ELECTROPLATED METAL

Patent #:	6946378	Issue Dt:	09/20/2005	Application #:	10396849	Filing Dt:	03/25/2003
Publication #:	US20030181003	Pub Dt:	09/25/2003
Title:	METHODS FOR FABRICATING PROTECTIVE STRUCTURES FOR BOND WIRES

Patent #:	6784501	Issue Dt:	08/31/2004	Application #:	10400492	Filing Dt:	03/28/2003
Publication #:	US20030183822	Pub Dt:	10/02/2003
Title:	PROCESS FOR FORMING METALIZED CONTACTS TO PERIPHERY TRANSISTORS

Patent #:	6954392	Issue Dt:	10/11/2005	Application #:	10400620	Filing Dt:	03/28/2003
Publication #:	US20040190334	Pub Dt:	09/30/2004
Title:	METHOD FOR REDUCING POWER CONSUMPTION WHEN SENSING A RESISTIVE MEMORY

Patent #:	7098587	Issue Dt:	08/29/2006	Application #:	10400732	Filing Dt:	03/27/2003
Publication #:	US20030184213	Pub Dt:	10/02/2003
Title:	PREVENTING JUNCTION LEAKAGE IN FIELD EMISSION DEVICES

Patent #:	7155300	Issue Dt:	12/26/2006	Application #:	10401209	Filing Dt:	03/27/2003
Publication #:	US20030191550	Pub Dt:	10/09/2003
Title:	METHOD FOR USING DATA REGARDING MANUFACTURING PROCEDURES INTEGRATED CIRCUITS (IC'S) HAVE UNDERGONE, SUCH AS REPAIRS, TO SELECT PROCEDURES THE IC'S UNDERGO, SUCH AS ADDITIONAL REPAIRS

Patent #:	7206865	Issue Dt:	04/17/2007	Application #:	10402125	Filing Dt:	03/28/2003
Publication #:	US20040193757	Pub Dt:	09/30/2004
Title:	APPARATUS AND METHOD FOR COMBINING WRITES TO I/O

Patent #:	6933224	Issue Dt:	08/23/2005	Application #:	10402471	Filing Dt:	03/28/2003
Publication #:	US20040192028	Pub Dt:	09/30/2004
Title:	METHOD OF FABRICATING INTEGRATED CIRCUITRY

Patent #:	7135369	Issue Dt:	11/14/2006	Application #:	10403734	Filing Dt:	03/31/2003
Publication #:	US20050054165	Pub Dt:	03/10/2005
Title:	ATOMIC LAYER DEPOSITED ZRALXOY DIELECTRIC LAYERS INCLUDING ZR4AIO9

Patent #:	7084067	Issue Dt:	08/01/2006	Application #:	10404396	Filing Dt:	03/31/2003
Publication #:	US20030203630	Pub Dt:	10/30/2003
Title:	REMOVAL OF COPPER OXIDES FROM INTEGRATED INTERCONNECTS

Patent #:	6853591	Issue Dt:	02/08/2005	Application #:	10404836	Filing Dt:	03/31/2003
Publication #:	US20040190349	Pub Dt:	09/30/2004
Title:	CIRCUIT AND METHOD FOR DECREASING THE REQUIRED REFRESH RATE OF DRAM DEVICES

Patent #:	6934209	Issue Dt:	08/23/2005	Application #:	10404859	Filing Dt:	03/31/2003
Publication #:	US20030227790	Pub Dt:	12/11/2003
Title:	TEMPERATURE COMPENSATED T-RAM MEMORY DEVICE AND METHOD

Patent #:	7302652	Issue Dt:	11/27/2007	Application #:	10404937	Filing Dt:	03/31/2003
Publication #:	US20040194037	Pub Dt:	09/30/2004
Title:	LEAKAGE CONTROL IN INTEGRATED CIRCUITS

Patent #:	6703303	Issue Dt:	03/09/2004	Application #:	10405200	Filing Dt:	04/01/2003
Publication #:	US20030194852	Pub Dt:	10/16/2003
Title:	METHOD OF MANUFACTURING A PORTION OF A MEMORY

Patent #:	6686275	Issue Dt:	02/03/2004	Application #:	10405201	Filing Dt:	04/01/2003
Publication #:	US20030166329	Pub Dt:	09/04/2003
Title:	METHOD OF SELECTIVELY REMOVING METAL NITRIDE OR METAL OXYNITRIDE EXTRUSIONS FROM A SEMICONDUCTOR STRUCTURE

Patent #:	7183792	Issue Dt:	02/27/2007	Application #:	10405328	Filing Dt:	04/01/2003
Publication #:	US20040199841	Pub Dt:	10/07/2004
Title:	METHOD AND SYSTEM FOR DETECTING A MODE OF OPERATION OF AN INTEGRATED CIRCUIT, AND A MEMORY DEVICE INCLUDING SAME

Patent #:	7161246	Issue Dt:	01/09/2007	Application #:	10405796	Filing Dt:	03/31/2003
Publication #:	US20050230815	Pub Dt:	10/20/2005
Title:	INTERCONNECT ALLOYS AND METHODS AND APPARATUS USING SAME

Patent #:	7271581	Issue Dt:	09/18/2007	Application #:	10405940	Filing Dt:	04/02/2003
Publication #:	US20040196025	Pub Dt:	10/07/2004
Title:	INTEGRATED CIRCUIT CHARACTERIZATION PRINTED CIRCUIT BOARD, TEST EQUIPMENT INCLUDING SAME METHOD OF FABRICATION THEREOF AND METHOD OF CHARACTERIZING AN INTEGRATED CIRCUIT DEVICE

Patent #:	7330869	Issue Dt:	02/12/2008	Application #:	10406046	Filing Dt:	04/01/2003
Publication #:	US20040111455	Pub Dt:	06/10/2004
Title:	HYBRID ARITHMETIC LOGIC UNIT

Patent #:	6882231	Issue Dt:	04/19/2005	Application #:	10406628	Filing Dt:	04/02/2003
Publication #:	US20040008090	Pub Dt:	01/15/2004
Title:	ADJUSTABLE FREQUENCY OSCILLATOR WITH PROGRAMMABLE CALIBRATING CIRCUIT AND RELATED SYSTEM AND METHOD

Patent #:	6943432	Issue Dt:	09/13/2005	Application #:	10406755	Filing Dt:	04/02/2003
Publication #:	US20030207587	Pub Dt:	11/06/2003
Title:	SEMICONDUCTOR CONSTRUCTIONS

Patent #:	7081416	Issue Dt:	07/25/2006	Application #:	10406916	Filing Dt:	04/04/2003
Publication #:	US20040198058	Pub Dt:	10/07/2004
Title:	METHODS OF FORMING FIELD EFFECT TRANSISTOR GATES

Patent #:	6777351	Issue Dt:	08/17/2004	Application #:	10407625	Filing Dt:	04/03/2003
Title:	MASKING WITHOUT PHOTOLITHOGRAPHY DURING THE FORMATION OF A SEMICONDUCTOR DEVICE

Patent #:	6858525	Issue Dt:	02/22/2005	Application #:	10407957	Filing Dt:	04/04/2003
Publication #:	US20030211676	Pub Dt:	11/13/2003
Title:	STACKED LOCAL INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME

Patent #:	6689624	Issue Dt:	02/10/2004	Application #:	10408450	Filing Dt:	04/08/2003
Publication #:	US20030207471	Pub Dt:	11/06/2003
Title:	METHOD OF FORMING SELF-ALIGNED, TRENCHLESS MAGNETORESITIVE RANDOM-ACCESS MEMORY (MRAM) STRUCTURE WITH SIDEWALL CONTAINMENT OF MRAM STRUCTURE

Patent #:	6864153	Issue Dt:	03/08/2005	Application #:	10408528	Filing Dt:	04/07/2003
Publication #:	US20030211677	Pub Dt:	11/13/2003
Title:	METHODS EMPLOYING HYBRID ADHESIVE MATERIALS TO SECURE COMPONENTS OF SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES TO ONE ANOTHER AND ASSEMBLIES AND PACKAGES INCLUDING COMPONENTS SECURED TO ONE ANOTHER WITH SUCH HYBRID ADHESIVE MATERIALS

Patent #:	7253117	Issue Dt:	08/07/2007	Application #:	10408542	Filing Dt:	04/07/2003
Publication #:	US20030211754	Pub Dt:	11/13/2003
Title:	METHODS FOR USE OF PULSED VOLTAGE IN A PLASMA REACTOR

Patent #:	6720666	Issue Dt:	04/13/2004	Application #:	10408972	Filing Dt:	04/08/2003
Publication #:	US20030211659	Pub Dt:	11/13/2003
Title:	BOC BGA PACKAGE FOR DIE WITH I-SHAPED BOND PAD LAYOUT

Patent #:	7112048	Issue Dt:	09/26/2006	Application #:	10408990	Filing Dt:	04/08/2003
Publication #:	US20030211660	Pub Dt:	11/13/2003
Title:	BOC BGA PACKAGE FOR DIE WITH I-SHAPED BOND PAD LAYOUT

Patent #:	7193306	Issue Dt:	03/20/2007	Application #:	10409008	Filing Dt:	04/08/2003
Publication #:	US20030209791	Pub Dt:	11/13/2003
Title:	SEMICONDUCTOR STRUCTURE HAVING STACKED SEMICONDUCTOR DEVICES

Patent #:	7408577	Issue Dt:	08/05/2008	Application #:	10409108	Filing Dt:	04/09/2003
Publication #:	US20040201550	Pub Dt:	10/14/2004
Title:	BIASING SCHEME FOR LARGE FORMAT CMOS ACTIVE PIXEL SENSORS

Patent #:	6921953	Issue Dt:	07/26/2005	Application #:	10409127	Filing Dt:	04/09/2003
Publication #:	US20040201070	Pub Dt:	10/14/2004
Title:	SELF-ALIGNED, LOW-RESISTANCE, EFFICIENT MRAM READ/WRITE CONDUCTORS

Patent #:	6765250	Issue Dt:	07/20/2004	Application #:	10409145	Filing Dt:	04/09/2003
Publication #:	US20030215961	Pub Dt:	11/20/2003
Title:	SELF-ALIGNED, TRENCHLESS MANGETORESITIVE RANDOM-ACCESS MEMORY (MRAM) STRUCTURE WITH SIDEWALL CONTAINMENT OF MRAM STRUCTURE

Patent #:	6937794	Issue Dt:	08/30/2005	Application #:	10409287	Filing Dt:	04/08/2003
Publication #:	US20040202419	Pub Dt:	10/14/2004
Title:	USING A TRANSVERSAL FILTER TO COMPENSATE FOR DISPERSION

Patent #:	6958661	Issue Dt:	10/25/2005	Application #:	10409460	Filing Dt:	04/08/2003
Publication #:	US20030206075	Pub Dt:	11/06/2003
Title:	VARIABLE RESISTANCE CIRCUIT

Patent #:	7189634	Issue Dt:	03/13/2007	Application #:	10409724	Filing Dt:	04/08/2003
Publication #:	US20040023441	Pub Dt:	02/05/2004
Title:	EDGE INTENSIVE ANTIFUSE

Patent #:	7102217	Issue Dt:	09/05/2006	Application #:	10409804	Filing Dt:	04/09/2003
Publication #:	US20040201111	Pub Dt:	10/14/2004
Title:	INTERPOSER SUBSTRATES WITH REINFORCED INTERCONNECT SLOTS, AND SEMICONDUCTOR DIE PACKAGES INCLUDING SAME

Patent #:	6812539	Issue Dt:	11/02/2004	Application #:	10410191	Filing Dt:	04/10/2003
Publication #:	US20040201072	Pub Dt:	10/14/2004
Title:	IMAGER LIGHT SHIELD

Patent #:	7373005	Issue Dt:	05/13/2008	Application #:	10410192	Filing Dt:	04/10/2003
Publication #:	US20040202374	Pub Dt:	10/14/2004
Title:	COMPRESSION SYSTEM FOR INTEGRATED SENSOR DEVICES

Patent #:	7093062	Issue Dt:	08/15/2006	Application #:	10411422	Filing Dt:	04/10/2003
Publication #:	US20040202028	Pub Dt:	10/14/2004
Title:	FLASH MEMORY DATA BUS FOR SYNCHRONOUS BURST READ PAGE

100

Patent #:	6881607	Issue Dt:	04/19/2005	Application #:	10411800	Filing Dt:	04/11/2003
Publication #:	US20030209837	Pub Dt:	11/13/2003
Title:	UNDERFILL AND ENCAPSULATION OF CARRIER SUBSTRATE-MOUNTED FLIP-CHIP COMPONENTS USING STEREOLITHOGRAPHY

Assignor

MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT

Exec Dt:

07/31/2019

Assignee

MICRON TECHNOLOGY, INC.

8000 S FEDERAL WAY

BOISE, IDAHO 83707

Correspondence name and address
	WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
	ONE MARKET, SPEAR TOWER, SUITE 3300
	SAN FRANCISCO, CA 94105

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