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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:051028/0001   Pages: 834
Recorded: 11/12/2019
Attorney Dkt #:4816.244
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
08/14/2001
Application #:
09469849
Filing Dt:
12/21/1999
Title:
METHOD FOR MANUFACTURING ELECTRONIC DEVICES, COMPRISING NON-SALICIDED NON-VOLATILE MEMORY CELLS, NON-SALICIDED HV TRANSISTORS, AND LV TRANSISTORS WITH SALICIDED JUNCTIONS WITH FEW MASKS
2
Patent #:
Issue Dt:
11/11/2003
Application #:
09470189
Filing Dt:
12/22/1999
Title:
MULTI-LINK EXTENSIONS AND BUNDLE SKEW MANAGEMENT
3
Patent #:
Issue Dt:
11/18/2003
Application #:
09470574
Filing Dt:
12/22/1999
Title:
METHOD AND APPARATUS FOR SWITCHING AN OPTICAL BEAM
4
Patent #:
Issue Dt:
01/15/2008
Application #:
09470875
Filing Dt:
12/22/1999
Title:
METHOD AND APPARATUS FOR PERFORMING DISTRIBUTED SIMULATION UTILIZING A SIMULATION BACKPLANE
5
Patent #:
Issue Dt:
12/05/2000
Application #:
09471215
Filing Dt:
12/23/1999
Title:
METHOD OF PATTERNING A SEMICONDUCTOR DEVICE
6
Patent #:
Issue Dt:
05/27/2003
Application #:
09471279
Filing Dt:
12/23/1999
Title:
LARGE GRAIN SINGLE CRYSTAL VERTICAL THIN FILM POLYSILICON MOSFETS
7
Patent #:
Issue Dt:
08/14/2001
Application #:
09472496
Filing Dt:
12/27/1999
Title:
PULSE GENERATOR CIRCUIT, PARTICULARLY FOR NON-VOLATILE MEMORIES
8
Patent #:
Issue Dt:
03/26/2002
Application #:
09472728
Filing Dt:
12/27/1999
Title:
METHOD AND APPARATUS FOR BIASING A CIRCUIT BOARD INTO ENGAGEMENT WITH A COMPUTER CHASSIS
9
Patent #:
Issue Dt:
09/30/2003
Application #:
09472839
Filing Dt:
12/28/1999
Title:
TECHNIQUE FOR SYNCHRONIZING FAULTS IN A PROCESSOR HAVING A REPLAY SYSTEM
10
Patent #:
Issue Dt:
04/30/2002
Application #:
09473232
Filing Dt:
12/24/1999
Title:
BUMPED SEMICONDUCTOR COMPONENT HAVING TEST PADS, AND METHOD AND SYSTEM FOR TESTING BUMPED SEMICONDUCTOR COMPONENTS
11
Patent #:
Issue Dt:
06/26/2001
Application #:
09473368
Filing Dt:
12/28/1999
Title:
METHOD FOR FORMING CONTACTLESS MOS TRANSISTORS AND RESULTING DEVICES, ESPECIALLY FOR USE IN NON-VOLATILE MEMORY ARRAYS
12
Patent #:
Issue Dt:
05/06/2003
Application #:
09474183
Filing Dt:
12/29/1999
Title:
FIELD FRAME MOTION DESIGN FOR DIGITAL VIDEO DECODER
13
Patent #:
Issue Dt:
05/14/2002
Application #:
09474566
Filing Dt:
12/29/1999
Title:
VOLTAGE TOLERANT HIGH DRIVE PULL-UP DRIVER FOR AN I/O BUFFER
14
Patent #:
Issue Dt:
03/02/2004
Application #:
09474746
Filing Dt:
12/29/1999
Title:
PARTIAL UNDERFILL FOR FLIP-CHIP ELECTRONIC PACKAGES
15
Patent #:
Issue Dt:
12/23/2003
Application #:
09474750
Filing Dt:
12/29/1999
Title:
SHIFTING AN INPUT SIGNAL FROM A HIGH-SPEED DOMAIN TO A LOWER-SPEED DOMAIN
16
Patent #:
Issue Dt:
11/05/2002
Application #:
09474932
Filing Dt:
12/29/1999
Title:
METHOD FOR READING A MEMORY, PARTICULARLY A NON-VOLATILE MEMORY
17
Patent #:
Issue Dt:
12/16/2003
Application #:
09475029
Filing Dt:
12/30/1999
Title:
INTERFACE TO A MEMORY SYSTEM FOR A PROCESSOR HAVING A REPLAY SYSTEM
18
Patent #:
Issue Dt:
04/30/2002
Application #:
09475164
Filing Dt:
12/30/1999
Title:
PUMP AREA REDUCTION THROUGH THE USE OF PASSIVE RC-FILTERS OR ACTIVE FILTERS
19
Patent #:
Issue Dt:
04/16/2002
Application #:
09475459
Filing Dt:
12/30/1999
Publication #:
Pub Dt:
01/03/2002
Title:
VOLTAGE BLOCKING METHOD AND APPARATUS FOR A CHARGE PUMP WITH DIODE CONNECTED PULL-UP AND PULL-DOWN ON BOOT NODES
20
Patent #:
Issue Dt:
08/28/2001
Application #:
09476036
Filing Dt:
12/31/1999
Title:
REFERENCE VOLTAGE ASJUSTMENT
21
Patent #:
Issue Dt:
07/16/2002
Application #:
09477407
Filing Dt:
01/04/2000
Title:
COUPLED MULTILAYER SOFT MAGNETIC FILMS FOR HIGH FREQUENCY MICROTRANSFORMER FOR SYSTEM-ON-CHIP POWER SUPPLY
22
Patent #:
Issue Dt:
04/02/2002
Application #:
09478745
Filing Dt:
01/06/2000
Title:
Method of fabricating semiconductor devices utilizing in situ passivation of dielectric thin films
23
Patent #:
Issue Dt:
04/16/2002
Application #:
09478975
Filing Dt:
01/06/2000
Publication #:
Pub Dt:
02/14/2002
Title:
METHODS OF FORMING SEMICONDUCTOR STRUCTURES
24
Patent #:
Issue Dt:
06/10/2003
Application #:
09480072
Filing Dt:
01/10/2000
Title:
SEMICONDUCTOR PROCESSING METHODS, METHODS OF FORMING ELECTRONIC COMPONENTS,AND TRANSISTORS
25
Patent #:
Issue Dt:
05/08/2001
Application #:
09480086
Filing Dt:
01/10/2000
Title:
Semiconductor Package Having Downset Leadframe For Reducing Package Bow
26
Patent #:
Issue Dt:
07/01/2003
Application #:
09480905
Filing Dt:
01/11/2000
Publication #:
Pub Dt:
09/19/2002
Title:
SEMICONDUCTOR STRUCTURES FORMED USING REDEPOSITION OF AN ETCHABLE LAYER
27
Patent #:
Issue Dt:
02/06/2001
Application #:
09481947
Filing Dt:
01/12/2000
Title:
Semiconductor die backside surface and method of fabrication
28
Patent #:
Issue Dt:
04/17/2001
Application #:
09482575
Filing Dt:
01/13/2000
Title:
Multiplexed noisy-quiet power busing for improved area efficiencies and pause performance in DRAM memories
29
Patent #:
Issue Dt:
10/08/2002
Application #:
09483656
Filing Dt:
01/14/2000
Title:
CHIP OUTLINE BAND (COB) STRUCTURE FOR INTEGRATED CIRCUITS
30
Patent #:
Issue Dt:
07/16/2002
Application #:
09483869
Filing Dt:
01/18/2000
Title:
STRUCTURES AND METHODS TO ENHANCE COPPER METALLIZATION
31
Patent #:
Issue Dt:
05/01/2007
Application #:
09483881
Filing Dt:
01/18/2000
Title:
SELECTIVE ELECTROLESS-PLATED COPPER METALLIZATION
32
Patent #:
Issue Dt:
04/23/2002
Application #:
09484002
Filing Dt:
01/18/2000
Title:
PROCESS FOR PROVIDING SEED LAYERS FOR USING ALUMINUM, COPPER, GOLD AND SILVER METALLURGY PROCESS FOR PROVIDING SEED LAYERS FOR USING ALUMINUM, COPPER, GOLD AND SILVER METALLURGY
33
Patent #:
Issue Dt:
08/28/2007
Application #:
09484303
Filing Dt:
01/18/2000
Title:
METHODS FOR MAKING INTEGRATED-CIRCUIT WIRING FROM COPPER, SILVER, GOLD, AND OTHER METALS
34
Patent #:
Issue Dt:
06/05/2001
Application #:
09484440
Filing Dt:
01/18/2000
Title:
Digital voltage translator and its method of operation
35
Patent #:
Issue Dt:
08/27/2002
Application #:
09488947
Filing Dt:
01/18/2000
Title:
SEMICONDUCTOR PROCESSING METHODS OF TRANSFERRING PATTERNS FROM PATTERNED PHOTORESISTS TO MATERIALS, AND STRUCTURES COMPRISING SILICON NITRIDE
36
Patent #:
Issue Dt:
07/09/2002
Application #:
09488949
Filing Dt:
01/21/2000
Title:
METHODS OF FORMING A FIELD EFFECT TRANSISTOR GATE CONSTRUCTION
37
Patent #:
Issue Dt:
08/21/2001
Application #:
09489113
Filing Dt:
01/21/2000
Title:
Leadframe alteration to direct compound flow into package
38
Patent #:
Issue Dt:
06/10/2003
Application #:
09489998
Filing Dt:
01/21/2000
Title:
ALIGNMENT AND ORIENTATION FEATURES FOR A SEMICONDUCTOR PACKAGE
39
Patent #:
Issue Dt:
04/17/2001
Application #:
09490727
Filing Dt:
01/25/2000
Title:
DIFFERENTIAL VOLTAGE REGULATOR
40
Patent #:
Issue Dt:
07/08/2003
Application #:
09490771
Filing Dt:
01/24/2000
Title:
COMPUTER SYSTEM HAVING REDUCED NUMBER OF BUS BRIDGE TERMINALS
41
Patent #:
Issue Dt:
03/20/2001
Application #:
09490803
Filing Dt:
01/26/2000
Title:
Method and circuit for sending a signal in a semiconductor device during a setup time
42
Patent #:
Issue Dt:
07/10/2001
Application #:
09491475
Filing Dt:
01/19/2000
Title:
Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories
43
Patent #:
Issue Dt:
07/10/2001
Application #:
09491476
Filing Dt:
01/19/2000
Title:
Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories
44
Patent #:
Issue Dt:
07/10/2001
Application #:
09491590
Filing Dt:
01/25/2000
Title:
Direct liquid injection system with on-line cleaning
45
Patent #:
Issue Dt:
12/10/2002
Application #:
09492738
Filing Dt:
01/27/2000
Title:
PLASMA ETCHING METHODS
46
Patent #:
Issue Dt:
11/25/2003
Application #:
09493441
Filing Dt:
01/18/2000
Title:
METHOD OF INITIALIZING A PROCESSOR AND COMPUTER SYSTEM
47
Patent #:
Issue Dt:
10/25/2005
Application #:
09493630
Filing Dt:
01/28/2000
Title:
VARIABLE DELAY LINE
48
Patent #:
Issue Dt:
09/06/2005
Application #:
09493663
Filing Dt:
01/28/2000
Title:
PATTERN RECOGNITION WITH THE USE OF MULTIPLE IMAGES
49
Patent #:
Issue Dt:
01/16/2001
Application #:
09494492
Filing Dt:
01/31/2000
Title:
Trap and delay pulse generator for a high speed clock
50
Patent #:
Issue Dt:
10/22/2002
Application #:
09494546
Filing Dt:
01/31/2000
Title:
RETICLE FOR CREATING RESIST-FILLED VIAS IN A DUAL DAMASCENE PROCESS
51
Patent #:
Issue Dt:
10/01/2002
Application #:
09495055
Filing Dt:
01/31/2000
Title:
CIRCUITS AND METHODS FOR TESTING MEMORY CELLS ALONG A PERIPHERY OF A MEMORY ARRAY
52
Patent #:
Issue Dt:
05/18/2004
Application #:
09497080
Filing Dt:
02/02/2000
Title:
METHODS OF FORMING SILICON DIOXIDE LAYERS, AND METHODS OF FORMING TRENCH ISOLATION REGIONS
53
Patent #:
Issue Dt:
01/09/2001
Application #:
09497295
Filing Dt:
02/03/2000
Title:
Memory device with a sense amplifier
54
Patent #:
Issue Dt:
05/18/2004
Application #:
09499594
Filing Dt:
02/07/2000
Title:
METHOD OF FABRICATING A SEMICONDUCTOR WORK OBJECT
55
Patent #:
Issue Dt:
07/08/2003
Application #:
09499726
Filing Dt:
02/08/2000
Title:
STRUCTURES AND METHODS FOR IMPROVED CAPACITOR CELLS IN INTEGRATED CIRCUITS
56
Patent #:
Issue Dt:
04/16/2002
Application #:
09499799
Filing Dt:
02/08/2000
Title:
Priority determining circuit for non-volatile memory
57
Patent #:
Issue Dt:
09/05/2006
Application #:
09500755
Filing Dt:
02/08/2000
Title:
ENHANCED COMPACT FLASH MEMORY CARD
58
Patent #:
Issue Dt:
09/18/2001
Application #:
09501034
Filing Dt:
02/09/2000
Title:
Method of manufacturing an interposer
59
Patent #:
Issue Dt:
09/24/2002
Application #:
09501131
Filing Dt:
02/09/2000
Title:
Nonvolatile multilevel memory and reading method therefor
60
Patent #:
Issue Dt:
05/28/2002
Application #:
09502070
Filing Dt:
02/10/2000
Title:
SEMICONDUCTOR DEVICE WITH IMPROVED INTERCONNECTIONS BETWEEN THE CHIP AND THE TERMINALS, AND PROCESS FOR ITS MANUFACTURE
61
Patent #:
Issue Dt:
08/06/2002
Application #:
09502788
Filing Dt:
02/11/2000
Title:
SETPOINT SILICON CONTROLLED RECTIFIER (SCR) ELECTROSTATIC DISCHARGE (ESD) CORE CLAMP
62
Patent #:
Issue Dt:
09/16/2003
Application #:
09502793
Filing Dt:
02/11/2000
Title:
COMPUTER NETWORK WITH SWAPPABLE COMPONENTS
63
Patent #:
Issue Dt:
03/20/2001
Application #:
09502822
Filing Dt:
02/11/2000
Title:
Dram array with gridded sense amplifier power source for enhanced column repair
64
Patent #:
Issue Dt:
08/06/2002
Application #:
09502827
Filing Dt:
02/11/2000
Title:
EFFICIENT CMOS DC-DC CONVERTERS BASED ON SWITCHED CAPACITOR POWER SUPPLIES WITH INDUCTIVE CURRENT LIMITERS
65
Patent #:
Issue Dt:
05/23/2006
Application #:
09502994
Filing Dt:
02/11/2000
Title:
3-D RENDERING TEXTURE CACHING SCHEME
66
Patent #:
Issue Dt:
12/10/2002
Application #:
09503105
Filing Dt:
02/11/2000
Title:
LOW TEMPERATURE NITRIDE USED AS CU BARRIER LAYER
67
Patent #:
Issue Dt:
07/02/2002
Application #:
09503278
Filing Dt:
02/14/2000
Publication #:
Pub Dt:
02/14/2002
Title:
Low dielectric constant shallow trench isolation
68
Patent #:
Issue Dt:
11/11/2003
Application #:
09503879
Filing Dt:
02/14/2000
Title:
METHOD AND APPARATUS FOR BRANCH TRACE MESSAGE SCHEME
69
Patent #:
Issue Dt:
04/10/2001
Application #:
09504191
Filing Dt:
02/15/2000
Title:
Chemical-mechanical polishing slurry
70
Patent #:
Issue Dt:
03/23/2004
Application #:
09505018
Filing Dt:
02/16/2000
Title:
AN ADHESIVE LAYER FOR AN ELECTRONIC APPARATUS HAVING MULTIPLE SEMICONDUCTOR DEVICES
71
Patent #:
Issue Dt:
09/17/2002
Application #:
09505599
Filing Dt:
02/16/2000
Title:
COMPUTER HOUSING WITH EXPANSION BAY COVER AND METHODS FOR OPERATING EXPANSION BAY COVERS
72
Patent #:
Issue Dt:
06/08/2004
Application #:
09507399
Filing Dt:
02/18/2000
Title:
METHOD OF QUANTIZING SIGNAL SAMPLES OF AN IMAGE DURING SAME
73
Patent #:
Issue Dt:
04/02/2002
Application #:
09507777
Filing Dt:
02/18/2000
Title:
Process for manufacturing semicondutor integrated memory devices with cells matrix having virtual ground
74
Patent #:
Issue Dt:
06/18/2002
Application #:
09510817
Filing Dt:
02/23/2000
Title:
MULTI-CHIP DEVICE UTILIZING A FLIP CHIP AND WIRE BOND ASSEMBLY
75
Patent #:
Issue Dt:
09/17/2002
Application #:
09510890
Filing Dt:
02/23/2000
Title:
METHODOLOGY OF REMOVING MISPLACED ENCAPSULANT FOR ATTACHMENT OF HEAT SINKS IN A CHIP ON BOARD PACKAGE
76
Patent #:
Issue Dt:
05/08/2001
Application #:
09510894
Filing Dt:
02/23/2000
Title:
CHIP ON BOARD WITH HEAT SINK ATTACHMENT
77
Patent #:
Issue Dt:
07/20/2004
Application #:
09511092
Filing Dt:
02/23/2000
Title:
METHOD AND SYSTEM FOR AUTHENTICATING A USER OF A COMPUTER SYSTEM
78
Patent #:
Issue Dt:
09/04/2001
Application #:
09511577
Filing Dt:
02/23/2000
Title:
High-voltage charge pump circuit
79
Patent #:
Issue Dt:
07/22/2003
Application #:
09511609
Filing Dt:
02/23/2000
Title:
CHIP ON BOARD AND HEAT SINK ATTACHMENT METHODS
80
Patent #:
Issue Dt:
09/30/2003
Application #:
09511692
Filing Dt:
02/23/2000
Title:
METHOD OF MAKING AN ELECTRICAL CONTACT DEVICE
81
Patent #:
Issue Dt:
10/09/2001
Application #:
09512900
Filing Dt:
02/25/2000
Title:
Process for manufacturing semiconductor integrated memory devices with cells matrix having virtual ground
82
Patent #:
Issue Dt:
08/31/2004
Application #:
09512978
Filing Dt:
02/24/2000
Publication #:
Pub Dt:
04/24/2003
Title:
METHODS OF FORMING CONTACTS, METHODS OF CONTACTING LINES, METHODS OF OPERATING INTEGRATED CIRCUITRY, AND INTEGRATED CIRCUITS
83
Patent #:
Issue Dt:
07/10/2001
Application #:
09512981
Filing Dt:
02/24/2000
Title:
SEMICONDUCTOR WAFER ALIGNMENT TOOLS
84
Patent #:
Issue Dt:
11/19/2002
Application #:
09513000
Filing Dt:
02/25/2000
Title:
METHOD FOR PROVIDING AN ALIGNMENT DIFFRACTION GRATING FOR PHOTOLITHOGRAPHIC ALIGNMENT DURING SEMICONDUCTOR FABRICATION
85
Patent #:
Issue Dt:
03/04/2003
Application #:
09513286
Filing Dt:
02/24/2000
Title:
METHOD FOR CORRECTION OF ERRORS IN A BINARY WORD STORED IN MULTILEVEL MEMORY CELLS, NOT REQUIRING ADDITIONAL CELLS
86
Patent #:
Issue Dt:
10/09/2001
Application #:
09513598
Filing Dt:
02/25/2000
Title:
Method for reading a multilevel nonvolatile memory and multilevel nonvolatile memory
87
Patent #:
Issue Dt:
12/04/2001
Application #:
09513641
Filing Dt:
02/25/2000
Title:
Full page increment/decrement burst for ddr sdram/sgram
88
Patent #:
Issue Dt:
05/14/2002
Application #:
09513761
Filing Dt:
02/25/2000
Title:
Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device
89
Patent #:
Issue Dt:
08/28/2001
Application #:
09513762
Filing Dt:
02/25/2000
Title:
Latched sense amplifier with tri-state outputs
90
Patent #:
Issue Dt:
05/28/2002
Application #:
09513797
Filing Dt:
02/25/2000
Title:
INTEGRATED CIRCUIT PACKAGING FOR OPTICAL SENSOR DEVICES
91
Patent #:
Issue Dt:
03/06/2001
Application #:
09513936
Filing Dt:
02/28/2000
Title:
Sense amplifier for low voltage memory arrays
92
Patent #:
Issue Dt:
06/19/2001
Application #:
09513938
Filing Dt:
02/28/2000
Title:
Dynamic flash memory cells with ultrathin tunnel oxides
93
Patent #:
Issue Dt:
02/18/2003
Application #:
09513939
Filing Dt:
02/28/2000
Publication #:
Pub Dt:
12/20/2001
Title:
Method for manufacturing improved stencil/screen
94
Patent #:
Issue Dt:
05/08/2001
Application #:
09513940
Filing Dt:
02/28/2000
Title:
Power level detection circuit
95
Patent #:
Issue Dt:
12/24/2002
Application #:
09514578
Filing Dt:
02/28/2000
Title:
PLANARIZING PADS, PLANARIZING MACHINES AND METHODS FOR MAKING AND USING PLANARIZING PADS IN MECHANICAL AND CHEMICAL-MECHANICAL PLANARAZATION OF MICROELECRTRONIC DEVICE SUBSTRATE ASSEMBLIES
96
Patent #:
Issue Dt:
05/07/2002
Application #:
09514627
Filing Dt:
02/28/2000
Title:
P-channel dynamic flash memory cells with ultrathin tunnel oxides
97
Patent #:
Issue Dt:
09/02/2003
Application #:
09515246
Filing Dt:
02/29/2000
Title:
METHOD AND SYSTEM FOR ADDRESSING GRAPHICS DATA FOR EFFICIENT DATA ACCESS
98
Patent #:
Issue Dt:
10/24/2000
Application #:
09515362
Filing Dt:
02/29/2000
Title:
Plasma processing tools, dual-source plasma etchers, dual-source plasma etching methods, and methods of forming planar coil dual-source plasma etchers
99
Patent #:
Issue Dt:
02/25/2003
Application #:
09515579
Filing Dt:
02/29/2000
Title:
METHOD OF PRESSURE CURING FOR REDUCING VOIDS IN A DIE ATTACH BONDLINE AND APPLICATIONS THEREOF
100
Patent #:
Issue Dt:
05/14/2002
Application #:
09516433
Filing Dt:
03/01/2000
Title:
Active pixel sensor with fully-depleted buried photoreceptor
Assignor
1
Exec Dt:
07/31/2019
Assignees
1
8000 S FEDERAL WAY
BOISE, IDAHO 83707
2
8000 S FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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