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Reel/Frame:051028/0001   Pages: 834
Recorded: 11/12/2019
Attorney Dkt #:4816.244
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
09/24/2019
Application #:
15852955
Filing Dt:
12/22/2017
Publication #:
Pub Dt:
06/27/2019
Title:
Conductive Structures and Assemblies Having Vertically-Stacked Memory Cells Over Conductive Structures
2
Patent #:
Issue Dt:
07/16/2019
Application #:
15852989
Filing Dt:
12/22/2017
Publication #:
Pub Dt:
06/27/2019
Title:
Assemblies Having Vertically-Extending Structures
3
Patent #:
Issue Dt:
02/18/2020
Application #:
15853328
Filing Dt:
12/22/2017
Publication #:
Pub Dt:
06/27/2019
Title:
AUTO-REFERENCED MEMORY CELL READ TECHNIQUES
4
Patent #:
Issue Dt:
10/01/2019
Application #:
15853364
Filing Dt:
12/22/2017
Publication #:
Pub Dt:
06/27/2019
Title:
AUTO-REFERENCED MEMORY CELL READ TECHNIQUES
5
Patent #:
Issue Dt:
12/10/2019
Application #:
15853423
Filing Dt:
12/22/2017
Publication #:
Pub Dt:
05/10/2018
Title:
SYSTEMS, METHODS AND DEVICES FOR PROGRAMMING A MULTILEVEL RESISTIVE MEMORY CELL
6
Patent #:
Issue Dt:
07/14/2020
Application #:
15853498
Filing Dt:
12/22/2017
Publication #:
Pub Dt:
06/27/2019
Title:
PHYSICAL UNCLONABLE FUNCTION USING MESSAGE AUTHENTICATION CODE
7
Patent #:
Issue Dt:
05/21/2019
Application #:
15853512
Filing Dt:
12/22/2017
Title:
INTERCONNECT STRUCTURES FOR PREVENTING SOLDER BRIDGING, AND ASSOCIATED SYSTEMS AND METHODS
8
Patent #:
Issue Dt:
08/27/2019
Application #:
15853514
Filing Dt:
12/22/2017
Publication #:
Pub Dt:
06/27/2019
Title:
APPARATUSES AND METHODS FOR DUTY CYCLE ERROR CORRECTION OF CLOCK SIGNALS
9
Patent #:
Issue Dt:
02/26/2019
Application #:
15853553
Filing Dt:
12/22/2017
Publication #:
Pub Dt:
05/03/2018
Title:
ADJUSTABLE DELAY CIRCUIT FOR OPTIMIZING TIMING MARGIN
10
Patent #:
Issue Dt:
09/24/2019
Application #:
15853803
Filing Dt:
12/24/2017
Publication #:
Pub Dt:
06/27/2019
Title:
MATERIAL IMPLICATION OPERATIONS IN MEMORY
11
Patent #:
Issue Dt:
01/29/2019
Application #:
15854334
Filing Dt:
12/26/2017
Publication #:
Pub Dt:
05/17/2018
Title:
MEMORY CELLS AND SEMICONDUCTOR DEVICES INCLUDING FERROELECTRIC MATERIALS
12
Patent #:
Issue Dt:
07/23/2019
Application #:
15854529
Filing Dt:
12/26/2017
Publication #:
Pub Dt:
05/03/2018
Title:
HALF DENSITY FERROELECTRIC MEMORY AND OPERATION
13
Patent #:
Issue Dt:
06/25/2019
Application #:
15854534
Filing Dt:
12/26/2017
Publication #:
Pub Dt:
05/17/2018
Title:
Memory Arrays and Methods of Forming Memory Arrays
14
Patent #:
Issue Dt:
12/25/2018
Application #:
15854598
Filing Dt:
12/26/2017
Publication #:
Pub Dt:
07/05/2018
Title:
APPARATUS AND METHODS FOR VIA CONNECTION WITH REDUCED VIA CURRENTS
15
Patent #:
Issue Dt:
09/24/2019
Application #:
15854600
Filing Dt:
12/26/2017
Publication #:
Pub Dt:
02/07/2019
Title:
MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE
16
Patent #:
Issue Dt:
08/13/2019
Application #:
15854622
Filing Dt:
12/26/2017
Publication #:
Pub Dt:
05/17/2018
Title:
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY PLANES OF A MEMORY DURING A MEMORY ACCESS OPERATION
17
Patent #:
Issue Dt:
08/04/2020
Application #:
15854656
Filing Dt:
12/26/2017
Publication #:
Pub Dt:
05/17/2018
Title:
THREE-DIMENSIONAL MEMORY APPARATUSES AND METHODS OF USE
18
Patent #:
Issue Dt:
06/05/2018
Application #:
15854916
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
05/03/2018
Title:
METHODS OF PROGRAMMING MEMORIES HAVING A SHARED RESISTANCE VARIABLE MATERIAL
19
Patent #:
Issue Dt:
06/05/2018
Application #:
15854934
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
05/03/2018
Title:
SYSTEMS HAVING A RESISTIVE MEMORY DEVICE
20
Patent #:
Issue Dt:
01/26/2021
Application #:
15855089
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
06/27/2019
Title:
MEMORY CELLS AND MEMORY ARRAYS
21
Patent #:
Issue Dt:
09/10/2019
Application #:
15855152
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
05/17/2018
Title:
TECHNIQUES FOR SENSING LOGIC VALUES STORED IN MEMORY CELLS USING SENSE AMPLIFIERS THAT ARE SELECTIVELY ISOLATED FROM DIGIT LINES
22
Patent #:
Issue Dt:
04/20/2021
Application #:
15855175
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
06/27/2019
Title:
Determination of Reliability of Vehicle Control Commands via Memory Test
23
Patent #:
Issue Dt:
12/25/2018
Application #:
15855326
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
07/05/2018
Title:
GROUND REFERENCE SCHEME FOR A MEMORY CELL
24
Patent #:
Issue Dt:
11/17/2020
Application #:
15855451
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
06/27/2019
Title:
Determination of Reliability of Vehicle Control Commands via Redundancy
25
Patent #:
Issue Dt:
01/15/2019
Application #:
15855485
Filing Dt:
12/27/2017
Title:
MEMORY DEVICE WRITE CIRCUITRY
26
Patent #:
Issue Dt:
09/10/2019
Application #:
15855514
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
06/27/2019
Title:
SYSTEMS AND METHODS FOR PERFORMING ROW HAMMER REFRESH OPERATIONS IN REDUNDANT MEMORY
27
Patent #:
Issue Dt:
10/15/2019
Application #:
15855622
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
06/27/2019
Title:
TEMPORARY CARRIER DEBOND INITIATION, AND ASSOCIATED SYSTEMS AND METHODS
28
Patent #:
Issue Dt:
08/20/2019
Application #:
15855643
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
05/17/2018
Title:
PARALLEL ACCESS TECHNIQUES WITHIN MEMORY SECTIONS THROUGH SECTION INDEPENDENCE
29
Patent #:
Issue Dt:
06/02/2020
Application #:
15855649
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
05/17/2018
Title:
DATA TRANSFER TECHNIQUES FOR MULTIPLE DEVICES ON A SHARED BUS
30
Patent #:
Issue Dt:
10/16/2018
Application #:
15855657
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
05/17/2018
Title:
CONDUCTIVE HARD MASK FOR MEMORY DEVICE FORMATION
31
Patent #:
Issue Dt:
02/04/2020
Application #:
15855665
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
06/27/2019
Title:
Methods Used In Forming At Least A Portion Of At Least One Conductive Capacitor Electrode Of A Capacitor That Comprises A Pair Of Conductive Capacitor Electrodes Having A Capacitor Insulator There-Between And Methods Of Forming A Capacitor
32
Patent #:
Issue Dt:
11/24/2020
Application #:
15855666
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
07/19/2018
Title:
THERMAL INSULATION FOR THREE-DIMENSIONAL MEMORY ARRAYS
33
Patent #:
Issue Dt:
06/02/2020
Application #:
15855669
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
07/19/2018
Title:
THERMAL INSULATION FOR THREE-DIMENSIONAL MEMORY ARRAYS
34
Patent #:
Issue Dt:
02/05/2019
Application #:
15855671
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
05/03/2018
Title:
APPARATUSES AND METHODS FOR SENSING A PHASE-CHANGE TEST CELL AND DETERMINING CHANGES TO THE TEST CELL RESISTANCE DUE TO THERMAL EXPOSURE
35
Patent #:
Issue Dt:
07/06/2021
Application #:
15855712
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
05/03/2018
Title:
APPARATUSES AND METHODS FOR SENSING A PHASE-CHANGE TEST CELL AND DETERMINING CHANGES TO THE TEST CELL RESISTANCE DUE TO THERMAL EXPOSURE
36
Patent #:
Issue Dt:
03/02/2021
Application #:
15855734
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
06/27/2019
Title:
Determination of Reliability of Vehicle Control Commands using a Voting Mechanism
37
Patent #:
Issue Dt:
08/13/2019
Application #:
15855849
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
05/10/2018
Title:
APPARATUSES AND METHODS FOR POWER EFFICIENT DRIVER CIRCUITS
38
Patent #:
Issue Dt:
04/21/2020
Application #:
15855958
Filing Dt:
12/27/2017
Publication #:
Pub Dt:
05/17/2018
Title:
THREE-DIMENSIONAL MEMORY APPARATUS AND METHOD OF MANUFACTURING THE SAME
39
Patent #:
Issue Dt:
03/26/2019
Application #:
15856132
Filing Dt:
12/28/2017
Title:
CHARGE LOSS FAILURE MITIGATION
40
Patent #:
Issue Dt:
10/08/2019
Application #:
15856244
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
05/03/2018
Title:
APPARATUS AND METHOD FOR INSTANT-ON QUADRA-PHASE SIGNAL GENERATOR
41
Patent #:
Issue Dt:
09/08/2020
Application #:
15856373
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
07/04/2019
Title:
COMPONENTS AND SYSTEMS FOR CLEANING A TOOL FOR FORMING A SEMICONDUCTOR DEVICE, AND RELATED METHODS
42
Patent #:
Issue Dt:
02/02/2021
Application #:
15856522
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
07/04/2019
Title:
Security of User Data Stored in Shared Vehicles
43
Patent #:
Issue Dt:
06/18/2019
Application #:
15856806
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
05/24/2018
Title:
VARIABLE RESISTANCE MEMORY STACK WITH TREATED SIDEWALLS
44
Patent #:
Issue Dt:
12/18/2018
Application #:
15856826
Filing Dt:
12/28/2017
Title:
POWER REDUCTION TECHNIQUE DURING READ/WRITE BURSTS
45
Patent #:
Issue Dt:
03/31/2020
Application #:
15856910
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
07/04/2019
Title:
MEMORY CONTROLLER IMPLEMENTED ERROR CORRECTION CODE MEMORY
46
Patent #:
Issue Dt:
05/12/2020
Application #:
15857054
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
07/04/2019
Title:
TECHNIQUES TO UPDATE A TRIM PARAMETER IN NON-VOLATILE MEMORY
47
Patent #:
Issue Dt:
09/03/2019
Application #:
15857091
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
07/04/2019
Title:
TECHNIQUES FOR PRECHARGING A MEMORY CELL
48
Patent #:
Issue Dt:
04/23/2019
Application #:
15857125
Filing Dt:
12/28/2017
Title:
DRIFT MITIGATION WITH EMBEDDED REFRESH
49
Patent #:
Issue Dt:
12/25/2018
Application #:
15857144
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
05/03/2018
Title:
APPARATUSES FOR REDUCING OFF STATE LEAKAGE CURRENTS
50
Patent #:
Issue Dt:
12/25/2018
Application #:
15857157
Filing Dt:
12/28/2017
Title:
JITTER CANCELLATION WITH AUTOMATIC PERFORMANCE ADJUSTMENT
51
Patent #:
Issue Dt:
07/16/2019
Application #:
15857188
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
07/04/2019
Title:
POLARITY-CONDITIONED MEMORY CELL WRITE OPERATIONS
52
Patent #:
Issue Dt:
04/23/2019
Application #:
15857197
Filing Dt:
12/28/2017
Title:
METHODS OF FORMING SEMICONDUCTOR STRUCTURES HAVING STAIR STEP STRUCTURES
53
Patent #:
Issue Dt:
03/31/2020
Application #:
15857327
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
07/04/2019
Title:
APPARATUSES AND METHODS FOR SENSE LINE ARCHITECTURES FOR SEMICONDUCTOR MEMORIES
54
Patent #:
Issue Dt:
12/18/2018
Application #:
15857370
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
05/03/2018
Title:
RESISTIVE RANDOM ACCESS MEMORY HAVING MULTI-CELL MEMORY BITS
55
Patent #:
Issue Dt:
05/28/2019
Application #:
15857402
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
05/03/2018
Title:
METHODS OF STORING AND RETRIEVING INFORMATION FOR RRAM WITH MULTI-CELL MEMORY BITS
56
Patent #:
Issue Dt:
02/15/2022
Application #:
15857422
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
08/02/2018
Title:
Semiconductor Constructions
57
Patent #:
Issue Dt:
03/05/2019
Application #:
15857435
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
05/03/2018
Title:
APPARATUSES AND METHODS FOR PROVIDING DATA TO A CONFIGURABLE STORAGE AREA
58
Patent #:
Issue Dt:
09/04/2018
Application #:
15857448
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
05/03/2018
Title:
Memory Arrays and Methods of Forming Memory Cells
59
Patent #:
Issue Dt:
09/10/2019
Application #:
15857597
Filing Dt:
12/28/2017
Publication #:
Pub Dt:
05/03/2018
Title:
METHODS AND APPARATUSES FOR COMMAND SHIFTER REDUCTION
60
Patent #:
Issue Dt:
07/02/2019
Application #:
15857704
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
TEMPERATURE-BASED MEMORY OPERATIONS
61
Patent #:
Issue Dt:
12/31/2019
Application #:
15857838
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/03/2018
Title:
SEMICONDUCTOR DEVICE AND ERROR CORRECTION METHOD
62
Patent #:
Issue Dt:
05/19/2020
Application #:
15857873
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/03/2018
Title:
SEMICONDUCTOR STRUCTURES INCLUDING MULTI-PORTION LINERS
63
Patent #:
Issue Dt:
03/30/2021
Application #:
15857920
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/24/2018
Title:
METHODS OF FORMING SEMICONDUCTOR DEVICES COMPRISING SILICON NITRIDE ON HIGH ASPECT RATIO FEATURES
64
Patent #:
Issue Dt:
09/10/2019
Application #:
15857974
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
Methods of Forming Integrated Assemblies
65
Patent #:
Issue Dt:
01/26/2021
Application #:
15858021
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
METHODS OF FORMING HIGH ASPECT RATIO OPENINGS AND METHODS OF FORMING HIGH ASPECT RATIO FEATURES
66
Patent #:
Issue Dt:
12/04/2018
Application #:
15858072
Filing Dt:
12/29/2017
Title:
METHODS OF FORMING STAIRCASE STRUCTURES
67
Patent #:
Issue Dt:
07/30/2019
Application #:
15858128
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
SEMICONDUCTOR DEVICES INCLUDING CONTROL LOGIC STRUCTURES, ELECTRONIC SYSTEMS, AND RELATED METHODS
68
Patent #:
NONE
Issue Dt:
Application #:
15858143
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
Distributed Architecture for Enhancing Artificial Neural Network
69
Patent #:
Issue Dt:
05/21/2019
Application #:
15858188
Filing Dt:
12/29/2017
Title:
SEMICONDUCTOR DEVICES, AND RELATED CONTROL LOGIC ASSEMBLIES, CONTROL LOGIC DEVICES, ELECTRONIC SYSTEMS, AND METHODS
70
Patent #:
Issue Dt:
08/27/2019
Application #:
15858201
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/24/2018
Title:
Memory Cells, Memory Systems, and Memory Programming Methods
71
Patent #:
Issue Dt:
07/02/2019
Application #:
15858229
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
SEMICONDUCTOR DEVICES INCLUDING CONTROL LOGIC LEVELS, AND RELATED MEMORY DEVICES, CONTROL LOGIC ASSEMBLIES, ELECTRONIC SYSTEMS, AND METHODS
72
Patent #:
Issue Dt:
06/09/2020
Application #:
15858263
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
Construction Of Integrated Circuitry And A DRAM Construction
73
Patent #:
Issue Dt:
08/06/2019
Application #:
15858383
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
MANAGING PARTIAL SUPERBLOCKS IN A NAND DEVICE
74
Patent #:
Issue Dt:
03/23/2021
Application #:
15858501
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
PILLAR-LAST METHODS FOR FORMING SEMICONDUCTOR DEVICES
75
Patent #:
Issue Dt:
05/10/2022
Application #:
15858505
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
Self-Learning in Distributed Architecture for Enhancing Artificial Neural Network
76
Patent #:
Issue Dt:
08/04/2020
Application #:
15858509
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
MULTI-GATE STRING DRIVERS HAVING SHARED PILLAR STRUCTURE
77
Patent #:
Issue Dt:
10/06/2020
Application #:
15858641
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/04/2019
Title:
SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFERENT SEMICONDUCTOR DIES
78
Patent #:
Issue Dt:
10/01/2019
Application #:
15858728
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/03/2018
Title:
CLAMP ELEMENTS FOR PHASE CHANGE MEMORY ARRAYS
79
Patent #:
Issue Dt:
12/11/2018
Application #:
15858747
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/24/2018
Title:
CELL-BASED REFERENCE VOLTAGE GENERATION
80
Patent #:
Issue Dt:
12/25/2018
Application #:
15858780
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/03/2018
Title:
METHODS, APPARATUSES, AND CIRCUITS FOR PROGRAMMING A MEMORY DEVICE
81
Patent #:
Issue Dt:
12/03/2019
Application #:
15858794
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/24/2018
Title:
METHOD, SYSTEM, AND DEVICE FOR L-SHAPED MEMORY COMPONENT
82
Patent #:
Issue Dt:
07/23/2019
Application #:
15858801
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
07/05/2018
Title:
ACCESSING MEMORY CELLS IN PARALLEL IN A CROSS-POINT ARRAY
83
Patent #:
Issue Dt:
10/08/2019
Application #:
15858811
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/17/2018
Title:
CROSS-POINT MEMORY AND METHODS FOR FABRICATION OF SAME
84
Patent #:
Issue Dt:
12/11/2018
Application #:
15858824
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
06/07/2018
Title:
DYNAMIC ADJUSTMENT OF MEMORY CELL DIGIT LINE CAPACITANCE
85
Patent #:
Issue Dt:
12/11/2018
Application #:
15858831
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/17/2018
Title:
WRITING TO CROSS-POINT NON-VOLATILE MEMORY
86
Patent #:
Issue Dt:
08/27/2019
Application #:
15858837
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/10/2018
Title:
MULTI-LEVEL STORAGE IN FERROELECTRIC MEMORY
87
Patent #:
Issue Dt:
10/01/2019
Application #:
15859029
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/31/2018
Title:
APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY CELLS
88
Patent #:
Issue Dt:
04/30/2019
Application #:
15859106
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/03/2018
Title:
APPARATUSES AND METHODS FOR PHOTONIC COMMUNICATION AND PHOTONIC ADDRESSING
89
Patent #:
Issue Dt:
03/09/2021
Application #:
15859122
Filing Dt:
12/29/2017
Publication #:
Pub Dt:
05/03/2018
Title:
TRANSISTORS, MEMORY CELLS AND SEMICONDUCTOR CONSTRUCTIONS COMPRISING FERROELECTRIC GATE DIELECTRIC
90
Patent #:
Issue Dt:
06/11/2019
Application #:
15860388
Filing Dt:
01/02/2018
Publication #:
Pub Dt:
07/04/2019
Title:
METHODS COMPRISING AN ATOMIC LAYER DEPOSITION SEQUENCE
91
Patent #:
Issue Dt:
02/26/2019
Application #:
15861286
Filing Dt:
01/03/2018
Publication #:
Pub Dt:
05/24/2018
Title:
Memory Cells
92
Patent #:
Issue Dt:
12/25/2018
Application #:
15861374
Filing Dt:
01/03/2018
Publication #:
Pub Dt:
05/10/2018
Title:
NON-VOLATILE MEMORY MODULE ARCHITECTURE TO SUPPORT MEMORY ERROR CORRECTION
93
Patent #:
Issue Dt:
12/31/2019
Application #:
15861442
Filing Dt:
01/03/2018
Publication #:
Pub Dt:
05/24/2018
Title:
METHOD, APPARATUS AND SYSTEM PROVIDING A STORAGE GATE PIXEL WITH HIGH DYNAMIC RANGE
94
Patent #:
Issue Dt:
01/28/2020
Application #:
15862445
Filing Dt:
01/04/2018
Publication #:
Pub Dt:
07/04/2019
Title:
Method for Stress Reduction in Semiconductor Package via Carrier
95
Patent #:
Issue Dt:
01/08/2019
Application #:
15862472
Filing Dt:
01/04/2018
Publication #:
Pub Dt:
05/10/2018
Title:
SYSTEMS AND METHODS FOR PROVIDING FILE INFORMATION IN A MEMORY SYSTEM PROTOCOL
96
Patent #:
Issue Dt:
05/21/2019
Application #:
15863324
Filing Dt:
01/05/2018
Publication #:
Pub Dt:
05/10/2018
Title:
METHODS AND APPARATUSES INCLUDING AN ASYMMETRIC ASSIST DEVICE
97
Patent #:
Issue Dt:
06/18/2019
Application #:
15864069
Filing Dt:
01/08/2018
Publication #:
Pub Dt:
07/11/2019
Title:
I/O BUFFER OFFSET MITIGATION
98
Patent #:
Issue Dt:
07/09/2019
Application #:
15864972
Filing Dt:
01/08/2018
Publication #:
Pub Dt:
07/11/2019
Title:
MEMORY DECISION FEEDBACK EQUALIZER BIAS LEVEL GENERATION
99
Patent #:
Issue Dt:
06/04/2019
Application #:
15864995
Filing Dt:
01/08/2018
Publication #:
Pub Dt:
05/24/2018
Title:
MEMORY AND ELECTRONIC DEVICES WITH REDUCED OPERATIONAL ENERGY IN CHALCOGENIDE MATERIAL
100
Patent #:
Issue Dt:
06/18/2019
Application #:
15865819
Filing Dt:
01/09/2018
Publication #:
Pub Dt:
05/10/2018
Title:
SEMICONDUCTOR DEVICES INCLUDING STAIR-STEP STRUCTURES
Assignor
1
Exec Dt:
07/31/2019
Assignees
1
8000 S FEDERAL WAY
BOISE, IDAHO 83707
2
8000 S FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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