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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:051028/0001   Pages: 834
Recorded: 11/12/2019
Attorney Dkt #:4816.244
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
06/25/2002
Application #:
09812729
Filing Dt:
03/19/2001
Title:
REFERENCE CHARGE GENERATOR, A METHOD FOR PROVIDING A REFERENCE CHARGE FROM A REFERENCE CHARGE GENERATOR, A METHOD OF OPERATING A REFERENCE CHARGE GENERATOR AND A DRAM MEMORY CIRCUIT FORMED USING MEMORY CELLS HAVING AN AREA OF 6F2
2
Patent #:
Issue Dt:
11/11/2003
Application #:
09813130
Filing Dt:
03/19/2001
Publication #:
Pub Dt:
08/23/2001
Title:
APPARATUS AND METHOD FOR DISABLING AND RE-ENABLING ACCESS TO IC TEST FUNCTIONS
3
Patent #:
Issue Dt:
07/02/2002
Application #:
09813274
Filing Dt:
03/20/2001
Publication #:
Pub Dt:
09/06/2001
Title:
USE OF SETUP TIME TO SEND SIGNAL THROUGH DIE
4
Patent #:
Issue Dt:
04/26/2005
Application #:
09813724
Filing Dt:
03/21/2001
Publication #:
Pub Dt:
09/26/2002
Title:
FOLDED INTERPOSER
5
Patent #:
Issue Dt:
02/04/2003
Application #:
09814715
Filing Dt:
04/20/2021
Publication #:
Pub Dt:
09/27/2001
Title:
SIMPLIFIED ETCHING TECHNIQUE FOR PRODUCING MULTIPLE UNDERCUT PROFILES
6
Patent #:
Issue Dt:
12/16/2003
Application #:
09816696
Filing Dt:
03/23/2001
Publication #:
Pub Dt:
09/26/2002
Title:
APPARATUS AND METHOD FOR MASKING DISPLAY ELEMENT DEFECTS IN A DISPLAY DEVICE
7
Patent #:
Issue Dt:
07/02/2002
Application #:
09817363
Filing Dt:
03/20/2001
Publication #:
Pub Dt:
11/08/2001
Title:
STRING PROGRAMMABLE NONVOLATILE MEMORY WITH NOR ARCHITECTURE
8
Patent #:
Issue Dt:
06/17/2003
Application #:
09817804
Filing Dt:
03/26/2001
Publication #:
Pub Dt:
11/01/2001
Title:
LOGIC PARTITIONING OF A NONVOLATILE MEMORY ARRAY
9
Patent #:
Issue Dt:
02/07/2006
Application #:
09818425
Filing Dt:
03/27/2001
Publication #:
Pub Dt:
10/03/2002
Title:
FLASH DEVICE SECURITY METHOD UTILIZING A CHECK REGISTER
10
Patent #:
Issue Dt:
08/20/2002
Application #:
09818426
Filing Dt:
03/27/2001
Title:
NON-VOLATILE MEMORY WITH PEAK CURRENT NOISE REDUCTION
11
Patent #:
Issue Dt:
04/22/2003
Application #:
09818617
Filing Dt:
03/28/2001
Publication #:
Pub Dt:
10/03/2002
Title:
MEMORY DEVICE HAVING PROGRAMMABLE COLUMN SEGMENTATION TO INCREASE FLEXIBILITY IN BIT REPAIR
12
Patent #:
Issue Dt:
04/28/2009
Application #:
09818699
Filing Dt:
03/27/2001
Publication #:
Pub Dt:
10/03/2002
Title:
DATA SECURITY FOR DIGITAL DATA STORAGE
13
Patent #:
Issue Dt:
09/30/2003
Application #:
09818751
Filing Dt:
03/27/2001
Publication #:
Pub Dt:
10/03/2002
Title:
POST-PLANARIZATION CLEAN-UP
14
Patent #:
Issue Dt:
10/15/2002
Application #:
09818957
Filing Dt:
03/27/2001
Publication #:
Pub Dt:
10/03/2002
Title:
METHOD AND APPARATUS FOR TRIMMING NON-VOLATILE MEMORY CELLS
15
Patent #:
Issue Dt:
08/05/2003
Application #:
09819160
Filing Dt:
03/27/2001
Title:
METHOD AND APPARATUS FOR SWITCHING AN OPTICAL BEAM IN A SEMICONDUCTOR SUBSTRATE
16
Patent #:
Issue Dt:
10/29/2002
Application #:
09819259
Filing Dt:
03/27/2001
Publication #:
Pub Dt:
08/23/2001
Title:
NEGATIVE RESISTANCE MEMORY CELL AND METHOD
17
Patent #:
Issue Dt:
12/03/2002
Application #:
09819260
Filing Dt:
03/27/2001
Publication #:
Pub Dt:
09/06/2001
Title:
POLISHING PADS AND PLANARIZING MACHINES FOR MECHANICAL OR CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC-DEVICE SUBSTRATE ASSEMBLIES, AND METHODS FOR MAKING AND USING SUCH PADS AND MACHINES
18
Patent #:
Issue Dt:
05/10/2005
Application #:
09819626
Filing Dt:
03/29/2001
Publication #:
Pub Dt:
10/03/2002
Title:
LOW INJECTION CHARGE PUMP
19
Patent #:
Issue Dt:
08/27/2002
Application #:
09819872
Filing Dt:
03/28/2001
Publication #:
Pub Dt:
09/06/2001
Title:
METHOD OF REDUCING DEFECTS IN ANTI-REFLECTIVE COATINGS AND SEMICONDUCTOR STRUCTURES FABRICATED THEREBY
20
Patent #:
Issue Dt:
07/20/2004
Application #:
09820108
Filing Dt:
03/28/2001
Publication #:
Pub Dt:
10/03/2002
Title:
PYRAMID FILTER
21
Patent #:
Issue Dt:
04/08/2003
Application #:
09821114
Filing Dt:
03/30/2001
Publication #:
Pub Dt:
10/03/2002
Title:
DUAL-SWIPING INTERCONNECTION CLIP, AND HOOK AND SLOT ARRANGEMENT FOR PRINTED CIRCUIT BOARD (PCB) ATTACHMENT
22
Patent #:
Issue Dt:
03/19/2002
Application #:
09821240
Filing Dt:
03/29/2001
Publication #:
Pub Dt:
09/06/2001
Title:
Integrated circuit inductors
23
Patent #:
Issue Dt:
06/25/2002
Application #:
09822249
Filing Dt:
04/02/2001
Publication #:
Pub Dt:
09/27/2001
Title:
STRUCTURE FOR IMPROVING STATIC REFRESH
24
Patent #:
Issue Dt:
05/28/2002
Application #:
09823191
Filing Dt:
03/29/2001
Title:
DIGITAL LEAKAGE COMPENSATION CIRCUIT
25
Patent #:
Issue Dt:
05/03/2005
Application #:
09823212
Filing Dt:
03/30/2001
Publication #:
Pub Dt:
10/31/2002
Title:
TWO-DIMENSIONAL PYRAMID FILTER ARCHITECTURE
26
Patent #:
Issue Dt:
11/21/2006
Application #:
09823215
Filing Dt:
03/30/2001
Publication #:
Pub Dt:
10/03/2002
Title:
METHOD AND APPARATUS FOR INTERSYSTEM CUT/COPY AND PASTE
27
Patent #:
Issue Dt:
01/23/2007
Application #:
09823926
Filing Dt:
03/30/2001
Publication #:
Pub Dt:
02/14/2002
Title:
METHOD AND A DEVICE FOR TESTING ELECTRONIC MEMORY DEVICES
28
Patent #:
Issue Dt:
01/20/2004
Application #:
09824125
Filing Dt:
04/02/2001
Publication #:
Pub Dt:
10/03/2002
Title:
METHOD AND SYSTEM FOR FABRICATING CONTACTS ON SEMICONDUCTOR COMPONENTS
29
Patent #:
Issue Dt:
11/20/2001
Application #:
09824363
Filing Dt:
04/02/2001
Title:
APPARATUS FOR MINIMIZATION OF DATA LINE COUPLING IN A SEMICONDUCTOR MEMORY DEVICE
30
Patent #:
Issue Dt:
11/05/2002
Application #:
09824955
Filing Dt:
04/03/2001
Publication #:
Pub Dt:
10/18/2001
Title:
TRANSVERSE HYBRID LOC PACKAGE
31
Patent #:
Issue Dt:
08/22/2006
Application #:
09825611
Filing Dt:
04/03/2001
Publication #:
Pub Dt:
09/06/2001
Title:
METHOD FOR PECVD DEPOSITION OF SELECTED MATERIAL FILMS
32
Patent #:
Issue Dt:
03/27/2007
Application #:
09825613
Filing Dt:
04/03/2001
Publication #:
Pub Dt:
08/30/2001
Title:
METHOD FOR PECVD DEPOSITION OF SELECTED MATERIAL FILMS
33
Patent #:
Issue Dt:
05/23/2006
Application #:
09826801
Filing Dt:
04/05/2001
Publication #:
Pub Dt:
10/11/2001
Title:
DATA SWITCHING ARBITRATION ARRANGEMENTS
34
Patent #:
Issue Dt:
07/17/2007
Application #:
09827248
Filing Dt:
04/04/2001
Publication #:
Pub Dt:
08/09/2001
Title:
METHODS OF PROCESSING A WORKPIECE, METHODS OF COMMUNICATING SIGNALS WITH RESPECT TO A WAFER, AND METHODS OF COMMUNICATING SIGNALS WITHIN A WORKPIECE PROCESSING APPARATUS
35
Patent #:
Issue Dt:
10/12/2004
Application #:
09827369
Filing Dt:
04/05/2001
Publication #:
Pub Dt:
10/11/2001
Title:
SYNCHRONIZATION CIRCUIT FOR READ PATHS OF AN ELETRONIC MEMORY
36
Patent #:
Issue Dt:
03/11/2003
Application #:
09827752
Filing Dt:
04/06/2001
Publication #:
Pub Dt:
08/16/2001
Title:
MONOLITHIC INTEGRATED CIRCUIT OSCILLATORS, COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) VOLTAGE-CONTROLLED OSCILLATORS, INTEGRATED CIRCUIT OSCILLATORS, OSCILLATOR-FORMING METHODS, AND OSCILLATION METHODS
37
Patent #:
Issue Dt:
01/28/2003
Application #:
09827759
Filing Dt:
04/06/2001
Publication #:
Pub Dt:
10/10/2002
Title:
METHOD OF ETCHING A SUBSTANTIALLY AMORPHOUS TA2O COMPRISING LAYER
38
Patent #:
Issue Dt:
04/09/2002
Application #:
09827973
Filing Dt:
04/05/2001
Publication #:
Pub Dt:
09/13/2001
Title:
SEMICONDUCTOR PROCESSING METHOD OF FORMING A CONDUCTIVE LINE, AND BURIED BIT LINE MEMORY CIRCUITRY
39
Patent #:
Issue Dt:
12/03/2002
Application #:
09828686
Filing Dt:
04/06/2001
Publication #:
Pub Dt:
10/10/2002
Title:
NON-VOLATILE MEMORY DEVICE WITH ERASE REGISTER
40
Patent #:
Issue Dt:
04/15/2003
Application #:
09829140
Filing Dt:
04/09/2001
Publication #:
Pub Dt:
10/10/2002
Title:
DEVICE AND METHOD FOR USING COMPLEMENTARY BITS IN A MEMORY ARRAY
41
Patent #:
Issue Dt:
05/17/2005
Application #:
09829161
Filing Dt:
04/09/2001
Publication #:
Pub Dt:
01/03/2002
Title:
METHODS FOR MAKING METALLIZATION STRUCTURES FOR SEMICONDUCTOR DEVICE INTERCONNECTS
42
Patent #:
Issue Dt:
06/04/2002
Application #:
09829585
Filing Dt:
04/09/2001
Publication #:
Pub Dt:
02/21/2002
Title:
METHOD FOR READ ONLY MEMORY SHADOWING
43
Patent #:
Issue Dt:
02/03/2004
Application #:
09832918
Filing Dt:
04/12/2001
Publication #:
Pub Dt:
10/17/2002
Title:
BURIED DIGIT SPACER-SEPARATED CAPACITOR ARRAY
44
Patent #:
Issue Dt:
08/27/2002
Application #:
09834298
Filing Dt:
04/12/2001
Publication #:
Pub Dt:
11/29/2001
Title:
METHOD AND APPARATUS FOR REDUCING BLEED CURRENTS WITHIN A DRAM ARRAY HAVING ROW-TO-COLUMN SHORTS
45
Patent #:
Issue Dt:
09/16/2003
Application #:
09835200
Filing Dt:
04/13/2001
Publication #:
Pub Dt:
08/23/2001
Title:
METHOD FOR TESTING BUMPED SEMICONDUCTOR COMPONENTS
46
Patent #:
Issue Dt:
03/26/2002
Application #:
09836067
Filing Dt:
04/17/2001
Publication #:
Pub Dt:
09/13/2001
Title:
Low profile multi-IC chip package connector
47
Patent #:
Issue Dt:
12/17/2002
Application #:
09836564
Filing Dt:
04/17/2001
Publication #:
Pub Dt:
10/04/2001
Title:
STRUCTURE AND METHOD FOR AN ELECTRONIC ASSEMBLY
48
Patent #:
Issue Dt:
05/28/2002
Application #:
09836590
Filing Dt:
04/16/2001
Publication #:
Pub Dt:
09/13/2001
Title:
METHOD FOR MANUFACTURING ELECTRONIC DEVICES COMPRISING NON-VOLATILE MEMORY CELLS AND LV TRANSISTORS WITH SALICIDED JUNCTIONS
49
Patent #:
Issue Dt:
07/23/2002
Application #:
09836591
Filing Dt:
04/16/2001
Publication #:
Pub Dt:
08/23/2001
Title:
APPARATUS AND METHODS FOR PROVIDING SUBSTRATE STRUCTURES HAVING METALLIC LAYERS FOR MICROELECTRONICS DEVICES
50
Patent #:
Issue Dt:
10/01/2002
Application #:
09836609
Filing Dt:
04/17/2001
Publication #:
Pub Dt:
08/16/2001
Title:
MULTI CHIP SEMICONDUCTOR PACKAGE AND METHOD OF CONSTRUCTION
51
Patent #:
Issue Dt:
05/07/2002
Application #:
09836947
Filing Dt:
04/17/2001
Publication #:
Pub Dt:
08/09/2001
Title:
Method and apparatus for supplying regulated power to memory device components
52
Patent #:
Issue Dt:
04/16/2002
Application #:
09837137
Filing Dt:
04/17/2001
Publication #:
Pub Dt:
08/09/2001
Title:
Method for improving the effectiveness of ESD protection in circuit structures formed in a semiconductor substrate
53
Patent #:
Issue Dt:
02/04/2003
Application #:
09838335
Filing Dt:
04/20/2001
Publication #:
Pub Dt:
10/24/2002
Title:
METHOD OF FABRICATING A HIGHLY RELIABLE GATE OXIDE
54
Patent #:
Issue Dt:
06/25/2002
Application #:
09838526
Filing Dt:
04/19/2001
Title:
A COMB-SHAPED CAPACITOR FOR USE IN INTEGRATED CIRCUITS
55
Patent #:
Issue Dt:
01/09/2007
Application #:
09838764
Filing Dt:
04/19/2001
Publication #:
Pub Dt:
10/24/2002
Title:
MEMORY WITH ELEMENT REDUNDANCY
56
Patent #:
Issue Dt:
02/18/2003
Application #:
09838820
Filing Dt:
04/19/2001
Publication #:
Pub Dt:
10/24/2002
Title:
SENSE AMPLIFIER FOR REDUCTION OF ACCESS DEVICE LEAKAGE
57
Patent #:
Issue Dt:
06/08/2004
Application #:
09839180
Filing Dt:
04/19/2001
Publication #:
Pub Dt:
10/03/2002
Title:
BALL GRID ARRAY INTERPOSER, PACKAGES AND METHODS
58
Patent #:
Issue Dt:
11/04/2003
Application #:
09839379
Filing Dt:
04/20/2001
Title:
INTEGRATED CIRCUITS HAVING LOW RESISTIVITY CONTACTS AND THE FORMATION THEREOF USING AN IN SITU PLASMA DOPING AND CLEAN
59
Patent #:
Issue Dt:
10/07/2003
Application #:
09839584
Filing Dt:
04/20/2001
Publication #:
Pub Dt:
01/03/2002
Title:
BORON INCORPORATED DIFFUSION BARRIER MATERIAL
60
Patent #:
Issue Dt:
02/25/2003
Application #:
09839804
Filing Dt:
04/19/2001
Publication #:
Pub Dt:
09/27/2001
Title:
UNIFORM DIELECTRIC LAYER AND METHOD TO FORM SAME
61
Patent #:
Issue Dt:
06/03/2003
Application #:
09839848
Filing Dt:
04/20/2001
Title:
DYNAMICALLY RECONFIGURABLE OPTICAL SWITCHING SYSTEM
62
Patent #:
Issue Dt:
08/27/2002
Application #:
09841221
Filing Dt:
04/25/2001
Title:
BOW RESISTANT PLASTIC SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATION
63
Patent #:
Issue Dt:
05/21/2002
Application #:
09841522
Filing Dt:
04/23/2001
Publication #:
Pub Dt:
10/11/2001
Title:
IDENTIFICATION AND VERIFICATION OF A SECTOR WITHIN A BLOCK OF MASS STORAGE FLASH MEMORY
64
Patent #:
Issue Dt:
09/10/2002
Application #:
09841904
Filing Dt:
04/25/2001
Publication #:
Pub Dt:
02/28/2002
Title:
METHOD FOR USING THIN SPACERS AND OXIDATION IN GATE OXIDES
65
Patent #:
Issue Dt:
12/24/2002
Application #:
09842788
Filing Dt:
04/27/2001
Publication #:
Pub Dt:
10/31/2002
Title:
NOVEL DRAM ACCESS TRANSISTOR
66
Patent #:
Issue Dt:
10/21/2003
Application #:
09843119
Filing Dt:
04/26/2001
Publication #:
Pub Dt:
09/27/2001
Title:
INTERPOSER AND METHODS FOR FABRICATING SAME
67
Patent #:
Issue Dt:
03/18/2003
Application #:
09843313
Filing Dt:
04/25/2001
Publication #:
Pub Dt:
12/05/2002
Title:
DATA RECEIVER TECHNOLOGY
68
Patent #:
Issue Dt:
01/14/2003
Application #:
09844134
Filing Dt:
04/30/2001
Title:
SEMICONDUCTOR PACKAGE HAVING STACKED DICE AND LEADFRAMES AND METHOD OF FABRICATION
69
Patent #:
Issue Dt:
07/15/2003
Application #:
09844184
Filing Dt:
04/27/2001
Publication #:
Pub Dt:
10/31/2002
Title:
METHOD OF FORMING A DUAL-GATED SEMICONDUCTOR-ON-INSULATOR DEVICE
70
Patent #:
Issue Dt:
06/18/2002
Application #:
09844952
Filing Dt:
04/27/2001
Publication #:
Pub Dt:
10/04/2001
Title:
INTEGRATED CIRCUIT HAVING AN ON-BOARD REFERENCE GENERATOR
71
Patent #:
Issue Dt:
01/13/2004
Application #:
09844985
Filing Dt:
04/27/2001
Publication #:
Pub Dt:
08/23/2001
Title:
COPPER CHEMICAL-MECHANICAL POLISHING PROCESS USING A FIXED ABRASIVE POLISHING PAD AND A COPPER LAYER CHEMICAL-MECHANICAL POLISHING SOLUTION SPECIFICALLY ADAPTED FOR CHEMICAL-MECHANICAL POLISHING WITH A FIXED ABRASIVE PAD
72
Patent #:
Issue Dt:
05/07/2002
Application #:
09846936
Filing Dt:
05/01/2001
Title:
READ REFERENCE SCHEME FOR NON-VOLATILE MEMORY
73
Patent #:
Issue Dt:
07/23/2002
Application #:
09846981
Filing Dt:
05/01/2001
Title:
SENSE AMPLIFIER WITH DATA LINE PRECHARGE THROUGH A SELF-BIAS CIRCUIT AND A PRECHARGE CIRCUIT
74
Patent #:
Issue Dt:
09/24/2002
Application #:
09847159
Filing Dt:
05/01/2001
Publication #:
Pub Dt:
09/06/2001
Title:
SEMICONDUCTOR WAFER ALIGNMENT METHODS AND SEMICONDUCTOR WAFER ALIGNMENT TOOLS
75
Patent #:
Issue Dt:
12/09/2003
Application #:
09847470
Filing Dt:
05/02/2001
Title:
SEMICONDUCTOR PACKAGE WITH MOLDED FLASH
76
Patent #:
Issue Dt:
03/11/2008
Application #:
09848846
Filing Dt:
05/03/2001
Publication #:
Pub Dt:
08/30/2001
Title:
SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY
77
Patent #:
Issue Dt:
12/03/2002
Application #:
09849037
Filing Dt:
05/04/2001
Publication #:
Pub Dt:
08/30/2001
Title:
GRAVITATIONALLY ASSISTED CONTROL OF SPREAD OF VISCOUS MATERIAL APPLIED TO SEMICONDUCTOR ASSEMBLY COMPONENTS
78
Patent #:
Issue Dt:
12/10/2002
Application #:
09849812
Filing Dt:
05/04/2001
Publication #:
Pub Dt:
08/30/2001
Title:
GRAVITATIONALLY ASSISTED CONTROL OF SPREAD OF VISCOUS MATERIAL APPLIED TO SEMICONDUCTOR ASSEMBLY COMPONENTS
79
Patent #:
Issue Dt:
09/16/2003
Application #:
09850245
Filing Dt:
05/07/2001
Publication #:
Pub Dt:
09/12/2002
Title:
METHOD AND DEVICE FOR OPERATING A RAM MEMORY
80
Patent #:
Issue Dt:
03/21/2006
Application #:
09850320
Filing Dt:
05/07/2001
Publication #:
Pub Dt:
10/03/2002
Title:
DATA SWITCH AND A METHOD FOR CONTROLLING THE DATA SWITCH
81
Patent #:
Issue Dt:
07/13/2004
Application #:
09850573
Filing Dt:
05/07/2001
Publication #:
Pub Dt:
08/30/2001
Title:
INTEGRATED CIRCUIT INDUCTORS
82
Patent #:
Issue Dt:
06/17/2003
Application #:
09850764
Filing Dt:
05/08/2001
Publication #:
Pub Dt:
10/04/2001
Title:
METHOD AND APPARATUS ON (110) SURFACES OF SILICON STRUCTURES WITH CONDUCTION IN THE <110> DIRECTION
83
Patent #:
Issue Dt:
03/18/2003
Application #:
09850792
Filing Dt:
05/08/2001
Publication #:
Pub Dt:
11/14/2002
Title:
FULL STRESS OPEN DIGIT LINE MEMORY DEVICE
84
Patent #:
Issue Dt:
04/09/2002
Application #:
09850902
Filing Dt:
05/07/2001
Publication #:
Pub Dt:
09/06/2001
Title:
Method and apparatus for supporting and cleaning a polishing pad for chemical-mechanical planarization of microelectronic substrates
85
Patent #:
Issue Dt:
07/13/2004
Application #:
09851176
Filing Dt:
05/08/2001
Publication #:
Pub Dt:
11/14/2002
Title:
READ/WRITE TIMING CALIBRATION OF A MEMORY ARRAY USING A ROW OR A REDUNDANT ROW
86
Patent #:
Issue Dt:
12/02/2003
Application #:
09851604
Filing Dt:
05/08/2001
Publication #:
Pub Dt:
06/13/2002
Title:
METHOD AND APPARATUS FOR DISTRIBUTING MOLD MATERIAL IN A MOLD FOR PACKAGING MICROELECTRONIC DEVICES
87
Patent #:
Issue Dt:
03/19/2002
Application #:
09851617
Filing Dt:
05/08/2001
Publication #:
Pub Dt:
09/06/2001
Title:
Method and apparatus for reducing induced switching transients
88
Patent #:
Issue Dt:
05/06/2003
Application #:
09851657
Filing Dt:
05/08/2001
Publication #:
Pub Dt:
11/15/2001
Title:
APPARATUS AND METHODS OF PACKAGING AND TESTING DIE
89
Patent #:
Issue Dt:
09/16/2003
Application #:
09851693
Filing Dt:
05/08/2001
Publication #:
Pub Dt:
10/11/2001
Title:
POLISHING PADS AND PLANARIZING MACHINES FOR MECHANICAL AND/OR CHEMICAL-MECHANICAL PLANARIZATION OF MICROELECTRONIC SUBSTRATE ASSEMBLIES
90
Patent #:
Issue Dt:
03/09/2004
Application #:
09852885
Filing Dt:
05/09/2001
Publication #:
Pub Dt:
10/11/2001
Title:
METHOD AND APPARATUS FOR WIRELESS TRANSFER OF CHEMICAL-MECHANICAL PLANARIZATION MEASUREMENTS
91
Patent #:
Issue Dt:
03/09/2004
Application #:
09853013
Filing Dt:
05/10/2001
Publication #:
Pub Dt:
10/18/2001
Title:
DATA TRANSMISSION DRIVER DEVICE
92
Patent #:
Issue Dt:
09/30/2003
Application #:
09853150
Filing Dt:
05/09/2001
Publication #:
Pub Dt:
09/27/2001
Title:
METHOD AND APPARATUS FOR WIRELESS TRANSFER OF CHEMICAL-MECHANICAL PLANARIZATION MEASUREMENTS
93
Patent #:
Issue Dt:
04/08/2003
Application #:
09853451
Filing Dt:
05/09/2001
Publication #:
Pub Dt:
03/14/2002
Title:
METAL NITRIDE BARRIER LAYER AND ELECTROPLATING SEED LAYER WITH THE SAME METAL AS THE METAL NITRIDE LAYER
94
Patent #:
Issue Dt:
08/13/2002
Application #:
09853664
Filing Dt:
05/11/2001
Publication #:
Pub Dt:
10/18/2001
Title:
CAPACITOR CONSTRUCTIONS
95
Patent #:
Issue Dt:
10/21/2003
Application #:
09854073
Filing Dt:
05/11/2001
Publication #:
Pub Dt:
08/30/2001
Title:
SOLDERMASK OPENING TO PREVENT DELAMINATION
96
Patent #:
Issue Dt:
11/19/2002
Application #:
09854236
Filing Dt:
05/11/2001
Publication #:
Pub Dt:
09/27/2001
Title:
METHOD AND SYSTEM FOR MANAGING COMMUNICATIONS AMONG COMPUTER DEVICES
97
Patent #:
Issue Dt:
10/07/2003
Application #:
09854292
Filing Dt:
05/09/2001
Publication #:
Pub Dt:
08/30/2001
Title:
METHOD FOR ELECTROLESS PLATING A CONTACT PAD
98
Patent #:
Issue Dt:
05/28/2002
Application #:
09854809
Filing Dt:
05/14/2001
Publication #:
Pub Dt:
10/25/2001
Title:
STACKED INTEGRATED CIRCUITS
99
Patent #:
Issue Dt:
07/13/2004
Application #:
09854975
Filing Dt:
05/14/2001
Title:
MODIFIED FACET ETCH TO PREVENT BLOWN GATE OXIDE AND INCREASE ETCH CHAMBER LIFE
100
Patent #:
Issue Dt:
02/24/2004
Application #:
09855217
Filing Dt:
05/14/2001
Publication #:
Pub Dt:
11/14/2002
Title:
DOUBLE SIDED CONTAINER PROCESS USED DURING THE MANUFACTURE OF A SEMICONDUCTOR DEVICE
Assignor
1
Exec Dt:
07/31/2019
Assignees
1
8000 S FEDERAL WAY
BOISE, IDAHO 83707
2
8000 S FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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