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01/08/2004
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12/07/2010
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01/08/2004
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01/08/2004
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12/05/2002
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01/15/2004
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11/21/2002
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03/13/2003
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01/15/2004
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12/05/2002
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09/14/2004
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01/15/2004
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02/06/2003
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10/12/2004
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07/11/2002
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08/24/2004
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07/11/2002
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01/15/2004
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11/28/2002
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06/01/2004
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07/16/2002
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12/05/2002
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12/05/2002
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02/10/2004
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07/15/2002
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11/28/2002
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07/15/2002
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12/05/2002
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07/15/2002
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12/05/2002
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01/22/2004
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01/15/2004
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12/05/2002
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12/05/2002
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12/18/2003
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11/28/2002
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12/05/2002
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02/13/2003
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12/26/2002
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07/29/2002
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12/12/2002
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01/29/2004
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Title:
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METHOD AND APPARATUS FOR REDUCING BLEED CURRENTS WITHIN A DRAM ARRAY HAVING ROW-TO-COLUMN SHORTS
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10206175
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Filing Dt:
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07/25/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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LOW PROFILE MULTI-IC CHIP PACKAGE CONNECTOR
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Patent #:
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Issue Dt:
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04/20/2004
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Application #:
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10206602
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Filing Dt:
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07/26/2002
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Publication #:
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Pub Dt:
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01/29/2004
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Title:
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FIELD ISOLATION STRUCTURES AND METHODS OF FORMING FIELD ISOLATION STRUCTURES
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10207072
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Filing Dt:
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07/30/2002
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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SMALL ANTI-FUSE CIRCUIT TO FACILITATE PARALLEL FUSE BLOWING
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Patent #:
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Issue Dt:
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05/20/2003
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Application #:
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10207572
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Filing Dt:
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07/29/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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LEAD-OVER-CHIP LEADFRAMES
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Patent #:
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Issue Dt:
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04/15/2003
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Application #:
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10208063
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Filing Dt:
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07/30/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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SCHEME FOR DELAY LOCKED LOOP RESET PROTECTION
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Patent #:
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Issue Dt:
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10/28/2003
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Application #:
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10208154
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Filing Dt:
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07/29/2002
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Publication #:
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Pub Dt:
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03/13/2003
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Title:
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CAPACITOR DIELECTRIC HAVING PEROVSKITE- TYPE CRYSTALLINE STRUCTURE
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Patent #:
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Issue Dt:
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03/11/2003
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Application #:
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10208987
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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12/12/2002
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE HAVING STACKED SEMICONDUCTOR DEVICES
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Patent #:
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Issue Dt:
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11/18/2003
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Application #:
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10209504
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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SELECTIVE POLYSILICON STUD GROWTH
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Patent #:
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Issue Dt:
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07/26/2005
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Application #:
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10209581
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Filing Dt:
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07/30/2002
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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ATOMIC LAYER DEPOSITED NANOLAMINATES OF HFO2/ZRO2 FILMS AS GATE DIELECTRICS
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Patent #:
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Issue Dt:
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07/15/2008
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Application #:
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10209753
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
Title:
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BALL GRID ARRAY PACKAGES WITH THERMALLY CONDUCTIVE CONTAINERS
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10209820
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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METHOD OF FORMING INTEGRATED CIRCUITRY, METHOD OF FORMING A CAPACITOR, METHOD OF FORMING DRAM INTEGRATED CIRCUITRY, INTEGRATED CIRCUITRY AND DRAM INTEGRATED CIRCUITRY
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Patent #:
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Issue Dt:
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10/05/2004
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Application #:
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10209823
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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02/05/2004
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Title:
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SEMICONDUCTOR DICE HAVING BACKSIDE REDISTRIBUTION LAYER ACCESSED USING THROUGH-SILICON VIAS, METHODS OF FABRICATION AND ASSEMBLIES
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Patent #:
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Issue Dt:
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06/24/2003
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Application #:
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10209865
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Filing Dt:
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08/02/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
Title:
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METHOD OF FORMING TRENCH ISOLATION REGIONS
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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10210633
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Filing Dt:
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07/31/2002
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
Title:
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FILM ON A SURFACE OF A MOLD USED DURING SEMICONDUCTOR DEVICE FABRICATION
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10210926
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Filing Dt:
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08/02/2002
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Title:
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ELECTRONIC ASSEMBLIES CONTAINING BOW RESISTANT SEMICONDUCTOR PACKAGES
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Patent #:
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Issue Dt:
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03/02/2004
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Application #:
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10211021
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Filing Dt:
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08/02/2002
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Publication #:
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Pub Dt:
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02/05/2004
| | | | |
Title:
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STACKED SEMICONDUCTOR PACKAGE AND METHOD PRODUCING SAME
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Patent #:
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Issue Dt:
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04/03/2007
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Application #:
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10211036
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Filing Dt:
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08/02/2002
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Publication #:
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Pub Dt:
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02/05/2004
| | | | |
Title:
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SYSTEM AND METHOD FOR OPTICALLY INTERCONNECTING MEMORY DEVICES
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Patent #:
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Issue Dt:
|
09/27/2005
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Application #:
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10211465
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Filing Dt:
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08/01/2002
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Publication #:
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Pub Dt:
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02/05/2004
| | | | |
Title:
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DYNAMIC POWER LEVEL CONTROL BASED ON A BOARD LATCH STATE
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Patent #:
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Issue Dt:
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01/27/2004
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Application #:
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10211476
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Filing Dt:
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08/01/2002
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Publication #:
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Pub Dt:
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02/05/2004
| | | | |
Title:
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EDGE INTENSIVE ANTIFUSE DEVICE STRUCTURE
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Patent #:
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Issue Dt:
|
03/30/2004
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Application #:
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10211924
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Filing Dt:
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08/01/2002
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
Title:
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COMPUTER INCLUDING INSTALLABLE AND REMOVABLE CARDS, OPTICAL INTERCONNECTION BETWEEN CARDS, AND METHOD OF ASSEMBLING A COMPUTER
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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10212518
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Filing Dt:
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08/05/2002
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Publication #:
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Pub Dt:
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02/05/2004
| | | | |
Title:
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GLOBAL COLUMN SELECT STRUCTURE FOR ACCESSING A MEMORY
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Patent #:
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Issue Dt:
|
06/07/2005
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Application #:
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10212561
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Filing Dt:
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08/05/2002
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Publication #:
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Pub Dt:
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02/05/2004
| | | | |
Title:
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SILICON RICH BARRIER LAYERS FOR INTEGRATED CIRCUIT DEVICES
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Patent #:
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Issue Dt:
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10/21/2003
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Application #:
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10212625
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Filing Dt:
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08/01/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
Title:
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SOI CMOS DEVICE WITH REDUCED DIBL
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10212630
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Filing Dt:
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08/05/2002
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Publication #:
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Pub Dt:
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02/05/2004
| | | | |
Title:
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REFRESHING MEMORY CELLS OF A PHASE CHANGE MATERIAL MEMORY DEVICE
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Patent #:
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Issue Dt:
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07/22/2003
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Application #:
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10212892
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Filing Dt:
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08/05/2002
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Publication #:
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Pub Dt:
|
12/19/2002
| | | | |
Title:
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METHOD FOR STABILIZING HIGH PRESSURE OXIDATION OF A SEMICONDUCTOR DEVICE
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|
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Patent #:
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|
Issue Dt:
|
07/13/2004
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Application #:
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10212937
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Filing Dt:
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08/05/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
Title:
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NUCLEATION FOR IMPROVED FLASH ERASE CHARACTERISTICS
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Patent #:
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Issue Dt:
|
10/03/2006
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Application #:
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10213038
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Filing Dt:
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08/05/2002
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Publication #:
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Pub Dt:
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02/05/2004
| | | | |
Title:
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MEMORY HUB AND ACCESS METHOD HAVING INTERNAL ROW CACHING
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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10213086
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Filing Dt:
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08/07/2002
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Publication #:
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Pub Dt:
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02/12/2004
| | | | |
Title:
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METHOD TO REMOVE AN OXIDE SEAM ALONG GATE STACK EDGE, WHEN NITRIDE SPACE FORMATION BEGINS WITH AN OXIDE LINER SURROUNDING GATE STACK
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Patent #:
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Issue Dt:
|
09/23/2003
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Application #:
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10213160
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Filing Dt:
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08/06/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
Title:
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METHODS OF ATTACHING A SEMICONDUCTOR CHIP TO A LEADFRAME WITH A FOOTPRINT OF ABOUT THE SAME SIZE AS THE CHIP
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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10213295
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Filing Dt:
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08/06/2002
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
Title:
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METHOD FOR PROVIDING AN ALIGNMENT DIFFRACTION GRATING FOR PHOTOLITHOGRAPHIC ALIGNMENT DURING SEMICONDUCTOR FABRICATION
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Patent #:
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Issue Dt:
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04/19/2005
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Application #:
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10214167
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Filing Dt:
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08/08/2002
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Publication #:
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Pub Dt:
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03/25/2004
| | | | |
Title:
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STACKED COLUMNAR RESISTIVE MEMORY STRUCTURE AND ITS METHOD OF FORMATION AND OPERATION
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Patent #:
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Issue Dt:
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08/24/2004
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Application #:
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10214169
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Filing Dt:
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08/08/2002
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Publication #:
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Pub Dt:
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12/12/2002
| | | | |
Title:
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INTERCONNECT LINE SELECTIVELY ISOLATED FROM AN UNDERLYING CONTACT PLUG
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Patent #:
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Issue Dt:
|
04/25/2006
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Application #:
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10214630
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Filing Dt:
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08/07/2002
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Publication #:
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Pub Dt:
|
02/12/2004
| | | | |
Title:
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PRACTICAL CODING AND METRIC CALCULATION FOR THE LATTICE INTERFERED CHANNEL
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Patent #:
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Issue Dt:
|
08/03/2004
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Application #:
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10214805
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Filing Dt:
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08/07/2002
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Publication #:
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Pub Dt:
|
02/12/2004
| | | | |
Title:
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MAGNETORESISTIVE MEMORY AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
|
08/01/2006
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Application #:
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10215214
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Filing Dt:
|
08/08/2002
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Publication #:
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Pub Dt:
|
02/12/2004
| | | | |
Title:
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PHOTOLITHOGRAPHIC TECHNIQUES FOR PRODUCING ANGLED LINES
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Patent #:
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Issue Dt:
|
05/06/2008
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Application #:
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10215462
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Filing Dt:
|
08/09/2002
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Publication #:
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|
Pub Dt:
|
12/19/2002
| | | | |
Title:
|
LOW LEAKAGE MIM CAPACITOR
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|
|
Patent #:
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|
Issue Dt:
|
08/07/2007
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Application #:
|
10215505
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Filing Dt:
|
08/09/2002
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Publication #:
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Pub Dt:
|
02/12/2004
| | | | |
Title:
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SYSTEM AND METHOD FOR MULTIPLE BIT OPTICAL DATA TRANSMISSION IN MEMORY SYSTEMS
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|
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Patent #:
|
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Issue Dt:
|
04/06/2004
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Application #:
|
10215519
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Filing Dt:
|
08/09/2002
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Publication #:
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Pub Dt:
|
02/12/2004
| | | | |
Title:
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METHODS FOR FORMING DUAL GATE OXIDES
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|
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Patent #:
|
|
Issue Dt:
|
03/08/2011
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Application #:
|
10215549
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Filing Dt:
|
08/08/2002
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Publication #:
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Pub Dt:
|
02/12/2004
| | | | |
Title:
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EXECUTING APPLICATIONS FROM A SEMICONDUCTOR NONVOLATILE MEMORY
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Patent #:
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Issue Dt:
|
06/17/2003
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Application #:
|
10215571
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Filing Dt:
|
08/08/2002
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Publication #:
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Pub Dt:
|
12/12/2002
| | | | |
Title:
|
COUPLING SPACED BOND PADS TO A CONTACT
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|
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Patent #:
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Issue Dt:
|
02/27/2007
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Application #:
|
10215732
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Filing Dt:
|
08/09/2002
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Publication #:
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Pub Dt:
|
02/12/2004
| | | | |
Title:
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MULTI-FUNCTIONAL SOLDER AND ARTICLES MADE THEREWITH, SUCH AS MICROELECTRONIC COMPONENTS
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|