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12/28/2004
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10215898
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08/08/2002
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02/12/2004
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Title:
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04/12/2005
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10215915
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08/08/2002
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02/12/2004
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CONDUCTIVE STRUCTURE FOR MICROELECTRONIC DEVICES AND METHODS OF FABRICATING SUCH STRUCTURES
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09/07/2004
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10215991
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08/09/2002
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12/12/2002
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PROCESS FOR THE FORMATION OF RUSIXOY-CONTAINING BARRIER LAYERS FOR HIGH-K DIELECTRICS
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05/31/2005
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10216080
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08/07/2002
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09/25/2003
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MEMORY DEVICE WITH MULTI-LEVEL STORAGE CELLS AND APPARATUSES, SYSTEMS AND METHODS INCLUDING SAME
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07/18/2006
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10216439
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08/12/2002
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02/12/2004
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METHOD AND APPARATUS USING PARASITIC CAPACITANCE FOR SYNCHRONIZING SIGNALS A DEVICE
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12/13/2005
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10216580
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08/08/2002
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02/12/2004
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ELECTRONIC DEVICES INCORPORATING ELECTRICAL INTERCONNECTIONS WITH IMPROVED RELIABILITY AND METHODS OF FABRICATING SAME
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09/28/2004
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10216698
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08/08/2002
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02/12/2004
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Title:
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08/10/2004
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10216804
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08/13/2002
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02/19/2004
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Title:
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CAPACITOR LAYOUT TECHNIQUE FOR REDUCTION OF FIXED PATTERN NOISE IN A CMOS SENSOR
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01/13/2004
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10216990
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08/12/2002
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12/19/2002
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Title:
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ROW DECODED BIASING OF SENSE AMPLIFIER FOR IMPROVED ONE'S MARGIN
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07/22/2003
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10217562
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08/12/2002
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04/10/2003
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METHODS OF FORMING A FIELD EFFECT TRANSISTORS
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04/26/2005
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10217600
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08/13/2002
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02/19/2004
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CLOSED FLUX MAGNETIC MEMORY
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01/29/2008
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10217644
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08/14/2002
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02/19/2004
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DATA PACKET HEADER CONVERSION
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03/01/2005
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10217665
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08/12/2002
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02/12/2004
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APPARATUS AND METHODS FOR REGULATED VOLTAGE
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07/29/2008
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10217667
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08/12/2002
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12/19/2002
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METHOD AND APPARATUS FOR REMOVING ENCAPSULATING MATERIAL FROM A PACKAGED MICROELECTRONIC DEVICE
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10/07/2003
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10217719
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08/13/2002
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12/19/2002
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SELF-ALIGNED PECVD ETCH MASK
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06/02/2009
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10218047
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08/13/2002
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02/19/2004
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METHODS FOR FORMING OPENINGS IN DOPED SILICON DIOXIDE
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08/12/2003
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10218258
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08/13/2002
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01/02/2003
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GATE COUPLED VOLTAGE SUPPORT FOR AN OUTPUT DRIVER CIRCUIT
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07/15/2003
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10218268
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08/13/2002
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Title:
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SELECTIVE PASSIVATION OF EXPOSED SILICON
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05/03/2005
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10218273
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08/13/2002
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12/19/2002
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Title:
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METHOD FOR USING THIN SPACERS AND OXIDATION IN GATE OXIDES
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01/06/2004
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10218275
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08/13/2002
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12/12/2002
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Title:
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MULTI CHIP SEMICONDUCTOR PACKAGE AND METHOD OF CONSTRUCTION
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11/11/2003
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10218511
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08/15/2002
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12/19/2002
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CLOCKED PASS TRANSISTOR AND COMPLEMENTARY PASS TRANSISTOR LOGIC CIRCUITS
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02/15/2005
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10218586
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08/15/2002
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02/19/2004
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PROGRAMMABLE EMBEDDED DRAM CURRENT MONITOR
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11/23/2004
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10218677
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08/14/2002
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03/13/2003
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FAST SENSING SCHEME FOR FLOATING-GATE MEMORY CELLS
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07/20/2004
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10219118
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08/14/2002
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12/12/2002
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IC PACKAGE WITH DUAL HEAT SPREADERS
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03/13/2007
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10219543
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08/16/2002
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02/19/2004
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CMOS IMAGER DECODER STRUCTURE
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11/15/2005
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10219604
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08/15/2002
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02/19/2004
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SEMICONDUCTOR DICE PACKAGES EMPLOYING AT LEAST ONE REDISTRIBUTION LAYER AND METHODS OF FABRICATION
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07/01/2003
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10219721
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08/15/2002
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12/26/2002
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ELECTRONIC DEVICE WITH LOCALLY REDUCED EFFECTS ON ANALOG SIGNALS
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04/26/2005
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10219870
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08/15/2002
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02/19/2004
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LANTHANIDE DOPED TIOX DIELECTRIC FILMS BY PLASMA OXIDATION
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09/14/2004
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10219878
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08/15/2002
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02/19/2004
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LANTHANIDE DOPED TIOX DIELECTRIC FILMS
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06/22/2004
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10222067
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08/16/2002
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12/26/2002
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TRANSVERSE HYBRID LOC PACKAGE
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07/08/2003
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10222113
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08/16/2002
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01/30/2003
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APPARATUS FOR DISABLING AND RE-ENABLING ACCESS TO IC TEST FUNCTIONS
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04/26/2005
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10222238
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08/16/2002
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02/19/2004
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METHODS AND SYSTEMS FOR PLANARIZING MICROELECTRONIC DEVICES WITH GE-SE-AG LAYERS
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05/03/2005
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10222290
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08/15/2002
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05/06/2004
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GAS DELIVERY SYSTEM FOR PULSED-TYPE DEPOSITION PROCESSES USED IN THE MANUFACTURING OF MICRO-DEVICES
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03/15/2005
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10222305
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08/15/2002
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04/17/2003
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INTEGRATED CIRCUITRY
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04/13/2004
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10222330
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08/15/2002
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03/06/2003
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METHODS OF FORMING CAPACITOR CONSTRUCTIONS
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02/01/2005
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10222456
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08/16/2002
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02/19/2004
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LATENCY REDUCTION USING NEGATIVE CLOCK EDGE AND READ FLAGS
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04/04/2006
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10222827
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08/19/2002
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02/19/2004
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CMOS IMAGER HAVING ON-CHIP ROM
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05/15/2007
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08/19/2002
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08/19/2004
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METHOD OF FORMING VERTICAL SUB-MICRON CMOS TRANSISTORS ON (110), (111), (311), (511), AND HIGHER ORDER SURFACES OF BULK, SOI AND THIN FILM STRUCTURES
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12/30/2003
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08/15/2002
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DIFFERENTIAL BUFFER HAVING BIAS CURRENT GATED BY ASSOCIATED SIGNAL
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01/27/2004
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08/19/2002
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01/02/2003
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CHEMICAL VAPOR DEPOSITION SYSTEMS INCLUDING METAL COMPLEXES WITH CHELATING O- AND/OR N-DONOR LIGANDS
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01/27/2004
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10223869
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08/20/2002
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03/13/2003
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VOLTAGE CONTROLLED OSCILLATORS
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11/09/2004
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10224102
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08/20/2002
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01/02/2003
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METHOD AND APPARATUS FOR PCB ARRAY WITH COMPENSATED SIGNAL PROPAGATION
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05/31/2005
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10224341
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08/21/2002
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02/26/2004
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BURIED TRANSISTORS FOR SILICON ON INSULATOR TECHNOLOGY
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08/31/2004
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10224451
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08/21/2002
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02/26/2004
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HIGH SPEED WORDLINE DECODER FOR DRIVING A LONG WORDLINE
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12/02/2003
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10224702
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08/21/2002
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VERTICAL FLASH MEMORY CELL WITH BURIED SOURCE RAIL
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11/30/2004
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10224771
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08/21/2002
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02/26/2004
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NICKEL BONDING CAP OVER COPPER METALIZED BONDPADS
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07/13/2004
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10224915
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08/21/2002
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02/26/2004
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HIGH COUPLING FLOATING GATE TRANSISTOR
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03/28/2006
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10225190
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08/22/2002
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02/26/2004
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METHOD OF MANUFACTURE OF A RESISTANCE VARIABLE MEMORY CELL
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08/05/2003
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10225315
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08/20/2002
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04/03/2003
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PROCESS FOR MANUFACTURING ELECTRONIC DEVICES COMPRISING NONVOLATILE MEMORY CELLS OF REDUCED DIMENSIONS
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02/03/2004
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10225513
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08/20/2002
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04/10/2003
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EEPROM FLASH MEMORY ERASABLE LINE BY LINE
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06/15/2004
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10225570
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08/20/2002
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09/25/2003
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MAGNETIC TUNNELING JUNCTION ANTIFUSE DEVICE
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05/25/2004
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10225575
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08/21/2002
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02/26/2004
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PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR ASSEMBLING MICROELECTRONIC DEVICES
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02/24/2004
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10225584
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08/21/2002
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02/26/2004
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DUAL-DAMASCENE BIT LINE STRUCTURES FOR MICROELECTRONIC DEVICES AND METHODS OF FABRICATING MICROELECTRONIC DEVICES
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09/28/2004
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10225907
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08/21/2002
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04/10/2003
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CIRCUIT BOARDS CONTAINING VIAS AND METHODS FOR PRODUCING SAME
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08/09/2005
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10226070
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08/22/2002
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02/26/2004
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MULTI-DIE SEMICONDUCTOR PACKAGE
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12/06/2005
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08/23/2002
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02/26/2004
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RESET VOLTAGE GENERATION CIRCUIT FOR CMOS IMAGERS
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05/10/2005
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10226472
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08/23/2002
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02/26/2004
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SEMICONDUCTOR COMPONENT WITH ON BOARD CAPACITOR AND METHOD OF FABRICATION
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04/06/2004
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10226488
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08/22/2002
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02/26/2004
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PROCESS VARIATION RESISTANT SELF ALIGNED CONTACT ETCH
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01/25/2005
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10226509
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08/22/2002
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02/26/2004
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APPARATUS AND METHOD FOR DEPOSITING AND REFLOWING SOLDER PASTE ON A MICROELECTRONIC WORKPIECE
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10226782
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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02/26/2004
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Title:
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CONTROLLING A DELAY LOCK LOOP CIRCUIT
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Patent #:
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Issue Dt:
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07/08/2003
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Application #:
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10226849
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Filing Dt:
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08/22/2002
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Title:
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DEPOSITION AND CHAMBER TREATMENT METHODS
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Patent #:
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Issue Dt:
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09/14/2004
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Application #:
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10227240
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Filing Dt:
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08/26/2002
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Publication #:
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Pub Dt:
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02/26/2004
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Title:
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POWER REDUCTION IN CMOS IMAGERS BY TRIMMING OF MASTER CURRENT REFERENCE
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10227317
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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METHOD AND APPARATUS FOR MARKING A BARE SEMICONDUCTOR DIE
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Patent #:
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Issue Dt:
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02/24/2004
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Application #:
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10227329
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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02/26/2004
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Title:
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STRESS BALANCED SEMICONDUCTOR PACKAGES, METHOD OF FABRICATION AND MODIFIED MOLD SEGMENT
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Patent #:
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Issue Dt:
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08/05/2003
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Application #:
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10227369
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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METHOD FOR GRAVITATION-ASSISTED CONTROL OF SPREAD OF VISCOUS MATERIAL APPLIED TO A SUBSTRATE
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Patent #:
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Issue Dt:
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05/03/2005
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Application #:
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10227608
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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12/25/2003
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Title:
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VOLTAGE LEVEL SHIFTING CIRCUIT WITH IMPROVED SWITCHING SPEED
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Patent #:
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Issue Dt:
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08/19/2003
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Application #:
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10227699
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Filing Dt:
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08/26/2002
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Publication #:
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Pub Dt:
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01/02/2003
| | | | |
Title:
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FORMATION OF METAL OXIDE GATE DIELECTRIC
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Patent #:
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Issue Dt:
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02/22/2005
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Application #:
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10227734
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Filing Dt:
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08/26/2002
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Publication #:
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Pub Dt:
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02/26/2004
| | | | |
Title:
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PRECONDITIONING GLOBAL BITLINES
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10227965
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Filing Dt:
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08/26/2002
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Publication #:
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Pub Dt:
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02/26/2004
| | | | |
Title:
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HIGH SPEED LOW VOLTAGE DRIVER
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Patent #:
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Issue Dt:
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01/13/2004
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Application #:
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10228062
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Filing Dt:
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08/27/2002
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Title:
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MRAM MEMORY ELEMENT
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10228597
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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METHOD AND APPARATUS FOR ERASING MEMORY
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Patent #:
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Issue Dt:
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03/17/2009
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Application #:
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10228617
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Filing Dt:
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08/26/2002
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Publication #:
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Pub Dt:
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10/21/2004
| | | | |
Title:
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METHOD FOR PACKAGING A TAPE SUBSTRATE
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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10228619
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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MAGNETIC NON-VOLATILE MEMORY COIL LAYOUT ARCHITECTURE AND PROCESS INTEGRATION SCHEME
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Patent #:
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Issue Dt:
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05/17/2005
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Application #:
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10228695
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Filing Dt:
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08/26/2002
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Publication #:
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Pub Dt:
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02/20/2003
| | | | |
Title:
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FIELD CORRECTION OF OVERLAY ERROR
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Patent #:
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Issue Dt:
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12/06/2005
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Application #:
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10228703
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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PSEUDO CMOS DYNAMIC LOGIC WITH DELAYED CLOCKS
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Patent #:
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Issue Dt:
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05/25/2004
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Application #:
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10228704
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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DIFFERENTIAL AMPLIFIER COMMON MODE NOISE COMPENSATION
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10228823
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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03/27/2003
| | | | |
Title:
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METAL-POLY INTEGRATED CAPACITOR STRUCTURE
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10228824
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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03/20/2003
| | | | |
Title:
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FLASH MEMORY ARRAY ARCHITECTURE
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Patent #:
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Issue Dt:
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01/23/2007
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Application #:
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10228839
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Filing Dt:
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08/26/2002
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Publication #:
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Pub Dt:
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02/26/2004
| | | | |
Title:
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CROSS DIFFUSION BARRIER LAYER IN POLYSILICON
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Patent #:
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Issue Dt:
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09/19/2006
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Application #:
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10228947
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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AUTOMATIC COLOR CONSTANCY FOR IMAGE SENSORS
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10229136
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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SINGLE SUBSTRATE ANNEALING OF MAGNETORESISTIVE STRUCTURE
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Patent #:
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Issue Dt:
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04/19/2005
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Application #:
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10229139
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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DEVICE HAVING REDUCED DIFFUSION THROUGH FERROMAGNETIC MATERIALS
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Patent #:
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Issue Dt:
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06/29/2004
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Application #:
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10229336
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Filing Dt:
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08/26/2002
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Publication #:
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Pub Dt:
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02/26/2004
| | | | |
Title:
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SEMICONDUCTOR CONSTRUCTIONS
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|
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Patent #:
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|
Issue Dt:
|
02/24/2004
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Application #:
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10229364
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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03/27/2003
| | | | |
Title:
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TEMPERATURE AND VOLTAGE COMPENSATED REFERENCE CURRENT GENERATOR
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Patent #:
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|
Issue Dt:
|
12/30/2003
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Application #:
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10229399
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
|
03/27/2003
| | | | |
Title:
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HIGH VOLTAGE LOW POWER SENSING DEVICE FOR FLASH MEMORY
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Patent #:
|
|
Issue Dt:
|
01/20/2004
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Application #:
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10229476
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Filing Dt:
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08/28/2002
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Title:
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VERTICAL FLOATING GATE TRANSISTOR
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Patent #:
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Issue Dt:
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10/25/2005
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Application #:
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10229627
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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SYSTEMS AND METHODS FOR FORMING METAL OXIDES USING METAL ORGANO-AMINES AND METAL ORGANO-OXIDES
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10229653
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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SYSTEMS AND METHODS FOR FORMING REFRACTORY METAL OXIDE LAYERS
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Patent #:
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Issue Dt:
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05/30/2006
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Application #:
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10229702
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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OUTPUT DATA COMPRESSION SCHEME USING TRI-STATE
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Patent #:
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Issue Dt:
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09/26/2006
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Application #:
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10229779
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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07/28/2005
| | | | |
Title:
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SYSTEMS AND METHODS FOR FORMING ZIRCONIUM AND/OR HAFNIUM-CONTAINING LAYERS
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10229824
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/04/2004
| | | | |
Title:
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VERTICALLY INTEGRATED FLASH MEMORY CELL AND METHOD OF FABRICATING A VERTICALLY INTEGRATED FLASH MEMORY CELL
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Patent #:
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Issue Dt:
|
06/14/2005
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Application #:
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10229837
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
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01/09/2003
| | | | |
Title:
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THIN FLIP-CHIP METHOD
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Patent #:
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Issue Dt:
|
11/23/2004
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Application #:
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10229865
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
|
01/09/2003
| | | | |
Title:
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INTEGRATED CIRCUITRY
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Patent #:
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Issue Dt:
|
12/04/2007
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Application #:
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10229866
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
|
03/04/2004
| | | | |
Title:
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METHOD AND SYSTEM FOR TRANSFERRING DATA TO AN ELECTRONIC TOY OR OTHER ELECTRONIC DEVICE
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Patent #:
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Issue Dt:
|
11/16/2004
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Application #:
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10229886
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Filing Dt:
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08/27/2002
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Publication #:
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|
Pub Dt:
|
07/24/2003
| | | | |
Title:
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SEMICONDUCTOR CONSTRUCTIONS
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Patent #:
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Issue Dt:
|
01/06/2004
|
Application #:
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10229887
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Filing Dt:
|
08/27/2002
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Title:
|
ATOMIC LAYER DEPOSITION METHODS
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|
Patent #:
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|
Issue Dt:
|
05/24/2005
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Application #:
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10229901
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Filing Dt:
|
08/28/2002
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Publication #:
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|
Pub Dt:
|
05/15/2003
| | | | |
Title:
|
VOLTAGE CLAMP CIRCUIT
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|
|
Patent #:
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|
Issue Dt:
|
01/17/2006
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Application #:
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10229908
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Filing Dt:
|
08/27/2002
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Publication #:
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|
Pub Dt:
|
03/04/2004
| | | | |
Title:
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MULTIPLE CHIP SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SAME
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|
|
Patent #:
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Issue Dt:
|
11/15/2005
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Application #:
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10229914
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Filing Dt:
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08/27/2002
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Publication #:
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Pub Dt:
|
03/04/2004
| | | | |
Title:
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MULTI-CHIP WAFER LEVEL SYSTEM PACKAGES AND METHODS OF FORMING SAME
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Patent #:
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Issue Dt:
|
08/02/2005
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Application #:
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10229920
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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03/27/2003
| | | | |
Title:
|
CONDITIONED AND ROBUST ULTRA-LOW POWER POWER-ON RESET SEQUENCER FOR INTEGRATED CIRCUITS
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|