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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:051028/0001   Pages: 834
Recorded: 11/12/2019
Attorney Dkt #:4816.244
Conveyance: RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS).
1
Patent #:
Issue Dt:
11/13/2007
Application #:
11215665
Filing Dt:
08/29/2005
Publication #:
Pub Dt:
03/01/2007
Title:
TIME DELAY OSCILLATOR FOR INTEGRATED CIRCUITS
2
Patent #:
Issue Dt:
03/11/2008
Application #:
11215671
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
01/05/2006
Title:
MASKING STRUCTURE HAVING MULTIPLE LAYERS INCLUDING AN AMORPHOUS CARBON LAYER
3
Patent #:
Issue Dt:
08/03/2010
Application #:
11215778
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
01/05/2006
Title:
POLYMER-BASED FERROELECTRIC MEMORY
4
Patent #:
Issue Dt:
10/05/2010
Application #:
11215780
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHODS FOR WAFER-LEVEL PACKAGING OF MICROFEATURE DEVICES AND MICROFEATURE DEVICES FORMED USING SUCH METHODS
5
Patent #:
Issue Dt:
10/02/2007
Application #:
11215836
Filing Dt:
08/29/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHOD AND APPARATUS FOR GENERATING TEMPERATURE-COMPENSATED READ AND VERIFY OPERATIONS IN FLASH MEMORIES
6
Patent #:
Issue Dt:
08/28/2007
Application #:
11215854
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/19/2006
Title:
OPEN PATTERN INDUCTOR
7
Patent #:
Issue Dt:
12/19/2006
Application #:
11215880
Filing Dt:
08/30/2005
Title:
LONG RETENTION TIME SINGLE TRANSISTOR VERTICAL MEMORY GAIN CELL
8
Patent #:
Issue Dt:
07/22/2008
Application #:
11215902
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/12/2006
Title:
MEMORY CELLS AND SELECT GATES OF NAND MEMORY ARRAYS
9
Patent #:
Issue Dt:
09/18/2007
Application #:
11215922
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
01/19/2006
Title:
STUD ELECTRODE AND PROCESS FOR MAKING SAME
10
Patent #:
Issue Dt:
11/06/2007
Application #:
11215933
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
PROGRAMMING METHOD FOR NAND EEPROM
11
Patent #:
Issue Dt:
04/10/2007
Application #:
11215963
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
METHODS FOR ERASING FLASH MEMORY
12
Patent #:
Issue Dt:
10/02/2007
Application #:
11215969
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
METHODS FOR ERASING FLASH MEMORY
13
Patent #:
Issue Dt:
11/09/2010
Application #:
11215982
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHOD OF FORMING PITCH MULTIPLED CONTACTS
14
Patent #:
Issue Dt:
02/26/2008
Application #:
11215987
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
DELAY LOCK CIRCUIT HAVING SELF-CALIBRATING LOOP
15
Patent #:
Issue Dt:
07/14/2009
Application #:
11215989
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MEMORY DEVICE TRANSISTORS
16
Patent #:
Issue Dt:
07/06/2010
Application #:
11215990
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
03/01/2007
Title:
NAND MEMORY DEVICE AND PROGRAMMING METHODS
17
Patent #:
Issue Dt:
04/22/2008
Application #:
11215993
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
03/01/2007
Title:
NON-VOLATILE MEMORY COPY BACK
18
Patent #:
Issue Dt:
12/25/2007
Application #:
11216199
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
CMOS CIRCUITS WITH REDUCED CROWBAR CURRENT
19
Patent #:
Issue Dt:
03/13/2007
Application #:
11216208
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
BIOS LOCK ENCODE/DECODE DRIVER
20
Patent #:
Issue Dt:
04/07/2009
Application #:
11216332
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/12/2006
Title:
SELECTIVE EPITAXY IN VERTICAL INTEGRATED CIRCUIT
21
Patent #:
Issue Dt:
05/01/2007
Application #:
11216375
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/11/2007
Title:
SELF ALIGNED METAL GATES ON HIGH-K DIELECTRICS
22
Patent #:
Issue Dt:
08/21/2007
Application #:
11216416
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
12/29/2005
Title:
APPARATUS AND METHOD FOR SUPPRESSING JITTER WITHIN A CLOCK SIGNAL GENERATOR
23
Patent #:
Issue Dt:
08/12/2008
Application #:
11216474
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
LANTHANUM ALUMINUM OXYNITRIDE DIELECTRIC FILMS
24
Patent #:
Issue Dt:
11/03/2009
Application #:
11216477
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
09/28/2006
Title:
INTEGRATED CIRCUIT FABRICATION
25
Patent #:
Issue Dt:
06/17/2008
Application #:
11216486
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
PACKAGING OF ELECTRONIC CHIPS WITH AIR-BRIDGE STRUCTURES
26
Patent #:
Issue Dt:
04/17/2007
Application #:
11216488
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
INTERCONNECT ALLOYS AND METHODS AND APPARATUS USING SAME
27
Patent #:
Issue Dt:
02/07/2012
Application #:
11216542
Filing Dt:
08/30/2005
Publication #:
Pub Dt:
03/01/2007
Title:
GRADED DIELECTRIC LAYERS
28
Patent #:
Issue Dt:
06/14/2011
Application #:
11216617
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/05/2006
Title:
SUPPORT STRUCTURE FOR USE IN THINNING SEMICONDUCTOR SUBSTRATES AND FOR SUPPORTING THINNED SEMICONDUCTOR SUBSTRATES
29
Patent #:
Issue Dt:
03/31/2009
Application #:
11216644
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
VOLTAGE-CONTROLLED SEMICONDUCTOR INDUCTOR AND METHOD
30
Patent #:
Issue Dt:
11/04/2008
Application #:
11216676
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/05/2006
Title:
MULTI-COMPONENT INTEGRATED CIRCUIT CONTACTS
31
Patent #:
Issue Dt:
06/17/2008
Application #:
11216739
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
NAND MEMORY DEVICE AND PROGRAMMING METHODS
32
Patent #:
Issue Dt:
03/18/2008
Application #:
11216742
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
SELECTIVE THRESHOLD VOLTAGE VERIFICATION AND COMPACTION
33
Patent #:
Issue Dt:
07/01/2008
Application #:
11216755
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MULTIPLE SELECT GATE ARCHITECTURE
34
Patent #:
Issue Dt:
02/03/2009
Application #:
11216814
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/12/2006
Title:
ELECTRONIC DEVICE PACKAGE
35
Patent #:
Issue Dt:
11/13/2007
Application #:
11216915
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
TRANSISTOR ASSEMBLIES
36
Patent #:
Issue Dt:
10/02/2007
Application #:
11216956
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
METHODS FOR ERASING FLASH MEMORY
37
Patent #:
Issue Dt:
12/06/2011
Application #:
11216958
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
COBALT TITANIUM OXIDE DIELECTRIC FILMS
38
Patent #:
Issue Dt:
11/07/2006
Application #:
11216959
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/05/2006
Title:
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS USING CONDUCTIVE LAYER AND GROOVES
39
Patent #:
Issue Dt:
03/11/2008
Application #:
11216970
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
FLASH MEMORY WITH RECESSED FLOATING GATE
40
Patent #:
Issue Dt:
12/08/2009
Application #:
11217030
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
BAND ENGINEERED NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE UTILIZING ENHANCED GATE INJECTION
41
Patent #:
Issue Dt:
11/06/2007
Application #:
11217033
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
A Transistor Assembly
42
Patent #:
Issue Dt:
02/08/2011
Application #:
11217095
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHOD AND APPARATUS TO SORT NANOTUBES
43
Patent #:
Issue Dt:
11/13/2012
Application #:
11217149
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MICROFEATURE WORKPIECES HAVING ALLOYED CONDUCTIVE STRUCTURES, AND ASSOCIATED METHODS
44
Patent #:
Issue Dt:
02/05/2008
Application #:
11217151
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
RETAINING RINGS, AND ASSOCIATED PLANARIZING APPARATUSES, AND RELATED METHODS FOR PLANARIZING MICRO-DEVICE WORKPIECES
45
Patent #:
Issue Dt:
02/05/2008
Application #:
11217152
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
INTERCONNECTING SUBSTRATES FOR MICROELECTRONIC DIES, METHODS FOR FORMING VIAS IN SUCH SUBSTRATES, AND METHODS FOR PACKAGING MICROELECTRONIC DEVICES
46
Patent #:
Issue Dt:
01/04/2011
Application #:
11217169
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES
47
Patent #:
Issue Dt:
09/21/2010
Application #:
11217170
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHODS AND APPARATUS FOR SORTING AND/OR DEPOSITING NANOTUBES
48
Patent #:
Issue Dt:
10/21/2008
Application #:
11217269
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
APPARATUS AND METHOD FOR REMOVING MATERIAL FROM MICROFEATURE WORKPIECES
49
Patent #:
Issue Dt:
08/11/2009
Application #:
11217270
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHODS FOR FORMING ARRAYS OF SMALL, CLOSELY SPACED FEATURES
50
Patent #:
Issue Dt:
12/12/2006
Application #:
11217539
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
01/12/2006
Title:
METHODS OF FORMING BURIED BIT LINE DRAM CIRCUITRY
51
Patent #:
Issue Dt:
03/13/2007
Application #:
11217618
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
METHOD AND APPARATUS FOR DATA COMPRESSION IN MEMORY DEVICES
52
Patent #:
Issue Dt:
07/07/2009
Application #:
11217627
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
53
Patent #:
Issue Dt:
06/29/2010
Application #:
11217629
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MICROELECTRONIC DEVICES HAVING INTERMEDIATE CONTACTS FOR CONNECTION TO INTERPOSER SUBSTRATES, AND ASSOCIATED METHODS OF PACKAGING MICROELECTRONIC DEVICES WITH INTERMEDIATE CONTACTS
54
Patent #:
Issue Dt:
02/03/2009
Application #:
11217749
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
55
Patent #:
Issue Dt:
09/01/2009
Application #:
11217771
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/12/2006
Title:
MEMORY UTILIZING OXIDE-CONDUCTOR NANOLAMINATES
56
Patent #:
Issue Dt:
11/27/2007
Application #:
11217776
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/12/2006
Title:
CONTROLLING DIFFUSION IN DOPED SEMICONDUCTOR REGIONS
57
Patent #:
Issue Dt:
08/29/2006
Application #:
11217813
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
01/12/2006
Title:
METHODS FOR NEUTRALIZING HOLES IN TUNNEL OXIDES OF FLOATING-GATE MEMORY CELLS AND DEVICES
58
Patent #:
Issue Dt:
04/03/2007
Application #:
11217820
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
01/12/2006
Title:
FLASH MEMORY
59
Patent #:
Issue Dt:
10/02/2007
Application #:
11217828
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
01/12/2006
Title:
METHODS FOR NEUTRALIZING HOLES IN TUNNEL OXIDES OF FLOATING-GATE MEMORY CELLS AND DEVICES
60
Patent #:
Issue Dt:
02/04/2014
Application #:
11217882
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
SYSTEMS AND METHODS FOR PLASMA DOPING MICROFEATURE WORKPIECES
61
Patent #:
Issue Dt:
10/04/2011
Application #:
11217888
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
SYSTEMS AND METHODS FOR IMPLEMENTING AND MANUFACTURING RETICLES FOR USE IN PHOTOLITHOGRAPHY TOOLS
62
Patent #:
Issue Dt:
11/20/2007
Application #:
11217894
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHODS FOR ETCHING DOPED OXIDES IN THE MANUFACTURE OF MICROFEATURE DEVICES
63
Patent #:
Issue Dt:
09/02/2008
Application #:
11217905
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHODS OF FORMING OPENINGS INTO DIELECTRIC MATERIAL
64
Patent #:
Issue Dt:
09/18/2007
Application #:
11217920
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/30/2006
Title:
FLASH MEMORY
65
Patent #:
Issue Dt:
04/14/2009
Application #:
11217946
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
01/12/2006
Title:
METHOD FOR FORMING AN ARRAY WITH POLYSILICON LOCAL INTERCONNECTS
66
Patent #:
Issue Dt:
10/09/2007
Application #:
11217952
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
01/12/2006
Title:
METHODS FOR NEUTRALIZING HOLES IN TUNNEL OXIDES OF FLOATING-GATE MEMORY CELLS AND DEVICES
67
Patent #:
Issue Dt:
07/15/2008
Application #:
11217980
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
DISPOSABLE PILLARS FOR CONTACT FORMATION
68
Patent #:
Issue Dt:
09/23/2008
Application #:
11217982
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
POROUS ORGANOSILICATE LAYERS, AND VAPOR DEPOSITION SYSTEMS AND METHODS FOR PREPARING SAME
69
Patent #:
Issue Dt:
03/17/2009
Application #:
11218028
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
70
Patent #:
Issue Dt:
07/24/2007
Application #:
11218031
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
LEADFRAME ALTERATION TO DIRECT COMPOUND FLOW INTO PACKAGE
71
Patent #:
Issue Dt:
11/14/2006
Application #:
11218038
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
METHOD AND APPARATUS FOR DATA COMPRESSION IN MEMORY DEVICES
72
Patent #:
Issue Dt:
07/14/2009
Application #:
11218092
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/23/2006
Title:
APPARATUS AND METHOD FOR HIGH DENSITY MULTI-CHIP STRUCTURES
73
Patent #:
Issue Dt:
12/04/2007
Application #:
11218123
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHOD AND APPARATUS FOR DIGITAL PHASE GENERATION FOR HIGH FREQUENCY CLOCK APPLICATIONS
74
Patent #:
Issue Dt:
04/13/2010
Application #:
11218184
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
03/08/2007
Title:
SEMICONDUCTOR MEMORY DEVICE
75
Patent #:
Issue Dt:
04/15/2008
Application #:
11218185
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
01/05/2006
Title:
METHODS OF FORMING TRANSISTOR DEVICES ASSOCIATED WITH SEMICONDUCTOR-ON-INSULATOR CONSTRUCTIONS
76
Patent #:
Issue Dt:
05/08/2007
Application #:
11218194
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHOD AND APPARATUS FOR SYNCHRONIZING DATA FROM MEMORY ARRAYS
77
Patent #:
Issue Dt:
09/25/2007
Application #:
11218201
Filing Dt:
08/31/2005
Publication #:
Pub Dt:
12/29/2005
Title:
METHODS OF FORMING SEMICONDUCTOR-ON-INSULATOR CONSTRUCTIONS
78
Patent #:
Issue Dt:
08/10/2010
Application #:
11218231
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
SEMICONDUCTOR CONSTRUCTIONS
79
Patent #:
Issue Dt:
08/28/2007
Application #:
11218233
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHODS OF FORMING LAYERS
80
Patent #:
Issue Dt:
11/13/2007
Application #:
11218239
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHOD AND APPARATUS FOR REMOVING MATERIAL FROM MICROFEATURE WORKPIECES
81
Patent #:
Issue Dt:
08/28/2007
Application #:
11218243
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES
82
Patent #:
Issue Dt:
09/18/2007
Application #:
11218254
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MICROFEATURE WORKPIECES AND METHODS OF FORMING A REDISTRIBUTION LAYER ON MICROFEATURE WORKPIECES
83
Patent #:
Issue Dt:
05/08/2012
Application #:
11218256
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MICROELECTRONIC DEVICES AND MICROELECTRONIC SUPPORT DEVICES, AND ASSOCIATED ASSEMBLIES AND METHODS
84
Patent #:
Issue Dt:
09/01/2009
Application #:
11218347
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHOD OF SELECTIVELY DEPOSITING MATERIALS ON A SUBSTRATE USING A SUPERCRITICAL FLUID
85
Patent #:
Issue Dt:
11/24/2009
Application #:
11218352
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
MICROFEATURE WORKPIECE SUBSTRATES HAVING THROUGH-SUBSTRATE VIAS, AND ASSOCIATED METHODS OF FORMATION
86
Patent #:
Issue Dt:
11/03/2009
Application #:
11218371
Filing Dt:
09/02/2005
Publication #:
Pub Dt:
03/08/2007
Title:
POWER LOSS RECOVERY IN NON-VOLATILE MEMORY
87
Patent #:
Issue Dt:
08/10/2010
Application #:
11218705
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHODS FOR FORMING THROUGH-WAFER INTERCONNECTS, INTERMEDIATE STRUCTURES SO FORMED, AND DEVICES AND SYSTEMS HAVING AT LEAST ONE SOLDER DAM STRUCTURE
88
Patent #:
Issue Dt:
04/12/2011
Application #:
11218773
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
04/06/2006
Title:
METHOD AND SYSTEM FOR BINDING HALIDE-BASED CONTAMINANTS
89
Patent #:
Issue Dt:
08/21/2007
Application #:
11218848
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
OPERATION OF MULTIPLE SELECT GATE ARCHITECTURE
90
Patent #:
Issue Dt:
09/30/2008
Application #:
11218849
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
HIGH PERFORMANCE MULTI-LEVEL NON-VOLATILE MEMORY DEVICE
91
Patent #:
Issue Dt:
08/25/2009
Application #:
11218851
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
PROGRAM AND READ TRIM SETTING
92
Patent #:
Issue Dt:
08/07/2007
Application #:
11218988
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
OUTPUT DRIVER ROBUST TO DATA DEPENDENT NOISE
93
Patent #:
Issue Dt:
08/19/2008
Application #:
11218990
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
01/12/2006
Title:
VERTICAL TUNNELING TRANSISTOR
94
Patent #:
Issue Dt:
02/19/2008
Application #:
11218992
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
TECHNIQUES FOR GENERATING TEST PATTERNS IN HIGH SPEED MEMORY DEVICES
95
Patent #:
NONE
Issue Dt:
Application #:
11218994
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
Techniques for dynamically selecting an input buffer
96
Patent #:
Issue Dt:
08/21/2007
Application #:
11219020
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
01/12/2006
Title:
FLASH MEMORY
97
Patent #:
Issue Dt:
07/20/2010
Application #:
11219067
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
METHOD OF FORMING ISOLATED FEATURES USING PITCH MULTIPLICATION
98
Patent #:
Issue Dt:
01/11/2011
Application #:
11219077
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
TRANSISTOR GATE FORMING METHODS AND TRANSISTOR STRUCTURES
99
Patent #:
Issue Dt:
05/26/2009
Application #:
11219079
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
TRANSISTOR GATE FORMING METHODS AND INTEGRATED CIRCUITS
100
Patent #:
Issue Dt:
11/04/2008
Application #:
11219085
Filing Dt:
09/01/2005
Publication #:
Pub Dt:
03/01/2007
Title:
DRAM TUNNELING ACCESS TRANSISTOR
Assignor
1
Exec Dt:
07/31/2019
Assignees
1
8000 S FEDERAL WAY
BOISE, IDAHO 83707
2
8000 S FEDERAL WAY
BOISE, IDAHO 83707
Correspondence name and address
WSGR, C/O QUI LU FLOOD, SENIOR PARALEGAL
ONE MARKET, SPEAR TOWER, SUITE 3300
SAN FRANCISCO, CA 94105

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