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Patent #:
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|
Issue Dt:
|
11/13/2007
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Application #:
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11215665
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Filing Dt:
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08/29/2005
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Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
TIME DELAY OSCILLATOR FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
|
03/11/2008
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Application #:
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11215671
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Filing Dt:
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08/30/2005
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Publication #:
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|
Pub Dt:
|
01/05/2006
| | | | |
Title:
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MASKING STRUCTURE HAVING MULTIPLE LAYERS INCLUDING AN AMORPHOUS CARBON LAYER
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Patent #:
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Issue Dt:
|
08/03/2010
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Application #:
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11215778
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Filing Dt:
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08/30/2005
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Publication #:
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Pub Dt:
|
01/05/2006
| | | | |
Title:
|
POLYMER-BASED FERROELECTRIC MEMORY
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Patent #:
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Issue Dt:
|
10/05/2010
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Application #:
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11215780
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Filing Dt:
|
08/30/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHODS FOR WAFER-LEVEL PACKAGING OF MICROFEATURE DEVICES AND MICROFEATURE DEVICES FORMED USING SUCH METHODS
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Patent #:
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|
Issue Dt:
|
10/02/2007
|
Application #:
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11215836
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Filing Dt:
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08/29/2005
|
Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR GENERATING TEMPERATURE-COMPENSATED READ AND VERIFY OPERATIONS IN FLASH MEMORIES
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Patent #:
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Issue Dt:
|
08/28/2007
|
Application #:
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11215854
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Filing Dt:
|
08/31/2005
|
Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
|
OPEN PATTERN INDUCTOR
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|
Patent #:
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Issue Dt:
|
12/19/2006
|
Application #:
|
11215880
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Filing Dt:
|
08/30/2005
|
Title:
|
LONG RETENTION TIME SINGLE TRANSISTOR VERTICAL MEMORY GAIN CELL
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Patent #:
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Issue Dt:
|
07/22/2008
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Application #:
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11215902
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Filing Dt:
|
08/31/2005
|
Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
|
MEMORY CELLS AND SELECT GATES OF NAND MEMORY ARRAYS
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Patent #:
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Issue Dt:
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09/18/2007
|
Application #:
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11215922
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Filing Dt:
|
08/30/2005
|
Publication #:
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Pub Dt:
|
01/19/2006
| | | | |
Title:
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STUD ELECTRODE AND PROCESS FOR MAKING SAME
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|
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Patent #:
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Issue Dt:
|
11/06/2007
|
Application #:
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11215933
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Filing Dt:
|
08/31/2005
|
Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
|
PROGRAMMING METHOD FOR NAND EEPROM
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Patent #:
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Issue Dt:
|
04/10/2007
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Application #:
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11215963
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Filing Dt:
|
08/31/2005
|
Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
Title:
|
METHODS FOR ERASING FLASH MEMORY
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Patent #:
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|
Issue Dt:
|
10/02/2007
|
Application #:
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11215969
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Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
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METHODS FOR ERASING FLASH MEMORY
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|
Patent #:
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|
Issue Dt:
|
11/09/2010
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Application #:
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11215982
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Filing Dt:
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08/31/2005
|
Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
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METHOD OF FORMING PITCH MULTIPLED CONTACTS
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Patent #:
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Issue Dt:
|
02/26/2008
|
Application #:
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11215987
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Filing Dt:
|
08/31/2005
|
Publication #:
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Pub Dt:
|
12/29/2005
| | | | |
Title:
|
DELAY LOCK CIRCUIT HAVING SELF-CALIBRATING LOOP
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|
Patent #:
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|
Issue Dt:
|
07/14/2009
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Application #:
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11215989
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Filing Dt:
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08/30/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MEMORY DEVICE TRANSISTORS
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|
Patent #:
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Issue Dt:
|
07/06/2010
|
Application #:
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11215990
|
Filing Dt:
|
08/30/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
NAND MEMORY DEVICE AND PROGRAMMING METHODS
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|
|
Patent #:
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|
Issue Dt:
|
04/22/2008
|
Application #:
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11215993
|
Filing Dt:
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08/30/2005
|
Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
|
NON-VOLATILE MEMORY COPY BACK
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|
|
Patent #:
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|
Issue Dt:
|
12/25/2007
|
Application #:
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11216199
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
CMOS CIRCUITS WITH REDUCED CROWBAR CURRENT
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|
|
Patent #:
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|
Issue Dt:
|
03/13/2007
|
Application #:
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11216208
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
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BIOS LOCK ENCODE/DECODE DRIVER
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|
|
Patent #:
|
|
Issue Dt:
|
04/07/2009
|
Application #:
|
11216332
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
SELECTIVE EPITAXY IN VERTICAL INTEGRATED CIRCUIT
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|
|
Patent #:
|
|
Issue Dt:
|
05/01/2007
|
Application #:
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11216375
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
01/11/2007
| | | | |
Title:
|
SELF ALIGNED METAL GATES ON HIGH-K DIELECTRICS
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|
|
Patent #:
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|
Issue Dt:
|
08/21/2007
|
Application #:
|
11216416
|
Filing Dt:
|
08/30/2005
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
APPARATUS AND METHOD FOR SUPPRESSING JITTER WITHIN A CLOCK SIGNAL GENERATOR
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|
|
Patent #:
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|
Issue Dt:
|
08/12/2008
|
Application #:
|
11216474
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
LANTHANUM ALUMINUM OXYNITRIDE DIELECTRIC FILMS
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|
|
Patent #:
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|
Issue Dt:
|
11/03/2009
|
Application #:
|
11216477
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
09/28/2006
| | | | |
Title:
|
INTEGRATED CIRCUIT FABRICATION
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|
|
Patent #:
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|
Issue Dt:
|
06/17/2008
|
Application #:
|
11216486
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
PACKAGING OF ELECTRONIC CHIPS WITH AIR-BRIDGE STRUCTURES
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|
|
Patent #:
|
|
Issue Dt:
|
04/17/2007
|
Application #:
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11216488
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
INTERCONNECT ALLOYS AND METHODS AND APPARATUS USING SAME
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|
Patent #:
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|
Issue Dt:
|
02/07/2012
|
Application #:
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11216542
|
Filing Dt:
|
08/30/2005
|
Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
|
GRADED DIELECTRIC LAYERS
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|
|
Patent #:
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|
Issue Dt:
|
06/14/2011
|
Application #:
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11216617
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
SUPPORT STRUCTURE FOR USE IN THINNING SEMICONDUCTOR SUBSTRATES AND FOR SUPPORTING THINNED SEMICONDUCTOR SUBSTRATES
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|
|
Patent #:
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|
Issue Dt:
|
03/31/2009
|
Application #:
|
11216644
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
VOLTAGE-CONTROLLED SEMICONDUCTOR INDUCTOR AND METHOD
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|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11216676
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
MULTI-COMPONENT INTEGRATED CIRCUIT CONTACTS
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|
|
Patent #:
|
|
Issue Dt:
|
06/17/2008
|
Application #:
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11216739
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
NAND MEMORY DEVICE AND PROGRAMMING METHODS
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|
|
Patent #:
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|
Issue Dt:
|
03/18/2008
|
Application #:
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11216742
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
SELECTIVE THRESHOLD VOLTAGE VERIFICATION AND COMPACTION
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|
Patent #:
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|
Issue Dt:
|
07/01/2008
|
Application #:
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11216755
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MULTIPLE SELECT GATE ARCHITECTURE
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|
|
Patent #:
|
|
Issue Dt:
|
02/03/2009
|
Application #:
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11216814
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
ELECTRONIC DEVICE PACKAGE
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|
|
Patent #:
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|
Issue Dt:
|
11/13/2007
|
Application #:
|
11216915
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
TRANSISTOR ASSEMBLIES
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|
|
Patent #:
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|
Issue Dt:
|
10/02/2007
|
Application #:
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11216956
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
METHODS FOR ERASING FLASH MEMORY
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|
Patent #:
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|
Issue Dt:
|
12/06/2011
|
Application #:
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11216958
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
COBALT TITANIUM OXIDE DIELECTRIC FILMS
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|
Patent #:
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|
Issue Dt:
|
11/07/2006
|
Application #:
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11216959
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
METHOD FOR FABRICATING SEMICONDUCTOR COMPONENTS USING CONDUCTIVE LAYER AND GROOVES
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|
Patent #:
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Issue Dt:
|
03/11/2008
|
Application #:
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11216970
|
Filing Dt:
|
08/31/2005
|
Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
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FLASH MEMORY WITH RECESSED FLOATING GATE
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|
|
Patent #:
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|
Issue Dt:
|
12/08/2009
|
Application #:
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11217030
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
BAND ENGINEERED NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE UTILIZING ENHANCED GATE INJECTION
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|
Patent #:
|
|
Issue Dt:
|
11/06/2007
|
Application #:
|
11217033
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
A Transistor Assembly
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|
|
Patent #:
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|
Issue Dt:
|
02/08/2011
|
Application #:
|
11217095
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHOD AND APPARATUS TO SORT NANOTUBES
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|
|
Patent #:
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|
Issue Dt:
|
11/13/2012
|
Application #:
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11217149
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MICROFEATURE WORKPIECES HAVING ALLOYED CONDUCTIVE STRUCTURES, AND ASSOCIATED METHODS
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|
Patent #:
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|
Issue Dt:
|
02/05/2008
|
Application #:
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11217151
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
RETAINING RINGS, AND ASSOCIATED PLANARIZING APPARATUSES, AND RELATED METHODS FOR PLANARIZING MICRO-DEVICE WORKPIECES
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|
|
Patent #:
|
|
Issue Dt:
|
02/05/2008
|
Application #:
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11217152
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
INTERCONNECTING SUBSTRATES FOR MICROELECTRONIC DIES, METHODS FOR FORMING VIAS IN SUCH SUBSTRATES, AND METHODS FOR PACKAGING MICROELECTRONIC DEVICES
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|
|
Patent #:
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|
Issue Dt:
|
01/04/2011
|
Application #:
|
11217169
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES
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|
Patent #:
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|
Issue Dt:
|
09/21/2010
|
Application #:
|
11217170
|
Filing Dt:
|
09/01/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHODS AND APPARATUS FOR SORTING AND/OR DEPOSITING NANOTUBES
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|
|
Patent #:
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|
Issue Dt:
|
10/21/2008
|
Application #:
|
11217269
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
APPARATUS AND METHOD FOR REMOVING MATERIAL FROM MICROFEATURE WORKPIECES
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|
|
Patent #:
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|
Issue Dt:
|
08/11/2009
|
Application #:
|
11217270
|
Filing Dt:
|
09/01/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHODS FOR FORMING ARRAYS OF SMALL, CLOSELY SPACED FEATURES
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|
|
Patent #:
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|
Issue Dt:
|
12/12/2006
|
Application #:
|
11217539
|
Filing Dt:
|
09/01/2005
|
Publication #:
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|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
METHODS OF FORMING BURIED BIT LINE DRAM CIRCUITRY
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|
|
Patent #:
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|
Issue Dt:
|
03/13/2007
|
Application #:
|
11217618
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR DATA COMPRESSION IN MEMORY DEVICES
|
|
|
Patent #:
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|
Issue Dt:
|
07/07/2009
|
Application #:
|
11217627
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
06/29/2010
|
Application #:
|
11217629
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MICROELECTRONIC DEVICES HAVING INTERMEDIATE CONTACTS FOR CONNECTION TO INTERPOSER SUBSTRATES, AND ASSOCIATED METHODS OF PACKAGING MICROELECTRONIC DEVICES WITH INTERMEDIATE CONTACTS
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|
Patent #:
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|
Issue Dt:
|
02/03/2009
|
Application #:
|
11217749
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
STACKED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
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|
Patent #:
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|
Issue Dt:
|
09/01/2009
|
Application #:
|
11217771
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
MEMORY UTILIZING OXIDE-CONDUCTOR NANOLAMINATES
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|
|
Patent #:
|
|
Issue Dt:
|
11/27/2007
|
Application #:
|
11217776
|
Filing Dt:
|
08/31/2005
|
Publication #:
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|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
CONTROLLING DIFFUSION IN DOPED SEMICONDUCTOR REGIONS
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|
|
Patent #:
|
|
Issue Dt:
|
08/29/2006
|
Application #:
|
11217813
|
Filing Dt:
|
09/01/2005
|
Publication #:
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|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
METHODS FOR NEUTRALIZING HOLES IN TUNNEL OXIDES OF FLOATING-GATE MEMORY CELLS AND DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
04/03/2007
|
Application #:
|
11217820
|
Filing Dt:
|
09/01/2005
|
Publication #:
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|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
10/02/2007
|
Application #:
|
11217828
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
METHODS FOR NEUTRALIZING HOLES IN TUNNEL OXIDES OF FLOATING-GATE MEMORY CELLS AND DEVICES
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|
|
Patent #:
|
|
Issue Dt:
|
02/04/2014
|
Application #:
|
11217882
|
Filing Dt:
|
09/01/2005
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Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
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SYSTEMS AND METHODS FOR PLASMA DOPING MICROFEATURE WORKPIECES
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Patent #:
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|
Issue Dt:
|
10/04/2011
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Application #:
|
11217888
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Filing Dt:
|
09/01/2005
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Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
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SYSTEMS AND METHODS FOR IMPLEMENTING AND MANUFACTURING RETICLES FOR USE IN PHOTOLITHOGRAPHY TOOLS
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Patent #:
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Issue Dt:
|
11/20/2007
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Application #:
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11217894
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Filing Dt:
|
09/01/2005
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Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHODS FOR ETCHING DOPED OXIDES IN THE MANUFACTURE OF MICROFEATURE DEVICES
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Patent #:
|
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Issue Dt:
|
09/02/2008
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Application #:
|
11217905
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Filing Dt:
|
09/01/2005
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Publication #:
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Pub Dt:
|
03/01/2007
| | | | |
Title:
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METHODS OF FORMING OPENINGS INTO DIELECTRIC MATERIAL
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Patent #:
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Issue Dt:
|
09/18/2007
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Application #:
|
11217920
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Filing Dt:
|
09/01/2005
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Publication #:
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Pub Dt:
|
03/30/2006
| | | | |
Title:
|
FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/2009
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Application #:
|
11217946
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Filing Dt:
|
09/01/2005
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Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
|
METHOD FOR FORMING AN ARRAY WITH POLYSILICON LOCAL INTERCONNECTS
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|
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Patent #:
|
|
Issue Dt:
|
10/09/2007
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Application #:
|
11217952
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Filing Dt:
|
09/01/2005
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Publication #:
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Pub Dt:
|
01/12/2006
| | | | |
Title:
|
METHODS FOR NEUTRALIZING HOLES IN TUNNEL OXIDES OF FLOATING-GATE MEMORY CELLS AND DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2008
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Application #:
|
11217980
|
Filing Dt:
|
09/01/2005
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Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
DISPOSABLE PILLARS FOR CONTACT FORMATION
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|
|
Patent #:
|
|
Issue Dt:
|
09/23/2008
|
Application #:
|
11217982
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Filing Dt:
|
09/01/2005
|
Publication #:
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|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
POROUS ORGANOSILICATE LAYERS, AND VAPOR DEPOSITION SYSTEMS AND METHODS FOR PREPARING SAME
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|
|
Patent #:
|
|
Issue Dt:
|
03/17/2009
|
Application #:
|
11218028
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2007
|
Application #:
|
11218031
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
LEADFRAME ALTERATION TO DIRECT COMPOUND FLOW INTO PACKAGE
|
|
|
Patent #:
|
|
Issue Dt:
|
11/14/2006
|
Application #:
|
11218038
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
METHOD AND APPARATUS FOR DATA COMPRESSION IN MEMORY DEVICES
|
|
|
Patent #:
|
|
Issue Dt:
|
07/14/2009
|
Application #:
|
11218092
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
03/23/2006
| | | | |
Title:
|
APPARATUS AND METHOD FOR HIGH DENSITY MULTI-CHIP STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2007
|
Application #:
|
11218123
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR DIGITAL PHASE GENERATION FOR HIGH FREQUENCY CLOCK APPLICATIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
04/13/2010
|
Application #:
|
11218184
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/15/2008
|
Application #:
|
11218185
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
01/05/2006
| | | | |
Title:
|
METHODS OF FORMING TRANSISTOR DEVICES ASSOCIATED WITH SEMICONDUCTOR-ON-INSULATOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2007
|
Application #:
|
11218194
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR SYNCHRONIZING DATA FROM MEMORY ARRAYS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/2007
|
Application #:
|
11218201
|
Filing Dt:
|
08/31/2005
|
Publication #:
|
|
Pub Dt:
|
12/29/2005
| | | | |
Title:
|
METHODS OF FORMING SEMICONDUCTOR-ON-INSULATOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11218231
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
SEMICONDUCTOR CONSTRUCTIONS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
11218233
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHODS OF FORMING LAYERS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/13/2007
|
Application #:
|
11218239
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHOD AND APPARATUS FOR REMOVING MATERIAL FROM MICROFEATURE WORKPIECES
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/2007
|
Application #:
|
11218243
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2007
|
Application #:
|
11218254
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MICROFEATURE WORKPIECES AND METHODS OF FORMING A REDISTRIBUTION LAYER ON MICROFEATURE WORKPIECES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2012
|
Application #:
|
11218256
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MICROELECTRONIC DEVICES AND MICROELECTRONIC SUPPORT DEVICES, AND ASSOCIATED ASSEMBLIES AND METHODS
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/2009
|
Application #:
|
11218347
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHOD OF SELECTIVELY DEPOSITING MATERIALS ON A SUBSTRATE USING A SUPERCRITICAL FLUID
|
|
|
Patent #:
|
|
Issue Dt:
|
11/24/2009
|
Application #:
|
11218352
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
MICROFEATURE WORKPIECE SUBSTRATES HAVING THROUGH-SUBSTRATE VIAS, AND ASSOCIATED METHODS OF FORMATION
|
|
|
Patent #:
|
|
Issue Dt:
|
11/03/2009
|
Application #:
|
11218371
|
Filing Dt:
|
09/02/2005
|
Publication #:
|
|
Pub Dt:
|
03/08/2007
| | | | |
Title:
|
POWER LOSS RECOVERY IN NON-VOLATILE MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
08/10/2010
|
Application #:
|
11218705
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHODS FOR FORMING THROUGH-WAFER INTERCONNECTS, INTERMEDIATE STRUCTURES SO FORMED, AND DEVICES AND SYSTEMS HAVING AT LEAST ONE SOLDER DAM STRUCTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
04/12/2011
|
Application #:
|
11218773
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
04/06/2006
| | | | |
Title:
|
METHOD AND SYSTEM FOR BINDING HALIDE-BASED CONTAMINANTS
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
11218848
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
OPERATION OF MULTIPLE SELECT GATE ARCHITECTURE
|
|
|
Patent #:
|
|
Issue Dt:
|
09/30/2008
|
Application #:
|
11218849
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
HIGH PERFORMANCE MULTI-LEVEL NON-VOLATILE MEMORY DEVICE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2009
|
Application #:
|
11218851
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
PROGRAM AND READ TRIM SETTING
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2007
|
Application #:
|
11218988
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
OUTPUT DRIVER ROBUST TO DATA DEPENDENT NOISE
|
|
|
Patent #:
|
|
Issue Dt:
|
08/19/2008
|
Application #:
|
11218990
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
VERTICAL TUNNELING TRANSISTOR
|
|
|
Patent #:
|
|
Issue Dt:
|
02/19/2008
|
Application #:
|
11218992
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
TECHNIQUES FOR GENERATING TEST PATTERNS IN HIGH SPEED MEMORY DEVICES
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
11218994
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
Techniques for dynamically selecting an input buffer
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2007
|
Application #:
|
11219020
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
01/12/2006
| | | | |
Title:
|
FLASH MEMORY
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/2010
|
Application #:
|
11219067
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
METHOD OF FORMING ISOLATED FEATURES USING PITCH MULTIPLICATION
|
|
|
Patent #:
|
|
Issue Dt:
|
01/11/2011
|
Application #:
|
11219077
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
TRANSISTOR GATE FORMING METHODS AND TRANSISTOR STRUCTURES
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2009
|
Application #:
|
11219079
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
TRANSISTOR GATE FORMING METHODS AND INTEGRATED CIRCUITS
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2008
|
Application #:
|
11219085
|
Filing Dt:
|
09/01/2005
|
Publication #:
|
|
Pub Dt:
|
03/01/2007
| | | | |
Title:
|
DRAM TUNNELING ACCESS TRANSISTOR
|
|