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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:051464/0389   Pages: 14
Recorded: 01/03/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 60
1
Patent #:
Issue Dt:
11/05/2002
Application #:
09495043
Filing Dt:
01/31/2000
Title:
BRIDGE STATE-MACHINE PROGRESSION FOR DATA TRANSFERS REQUESTED BY A HOST BUS AND RESPONDED TO BY AN EXTERNAL BUS
2
Patent #:
Issue Dt:
02/17/2004
Application #:
09512783
Filing Dt:
02/25/2000
Title:
PROGRAMMABLE LOGIC ARRAY EMBEDDED IN MASK-PROGRAMMED ASIC
3
Patent #:
Issue Dt:
09/10/2002
Application #:
09548726
Filing Dt:
04/13/2000
Title:
ACCURATE POWER DETECTION CIRCUIT FOR USE IN A POWER AMPLIFIER
4
Patent #:
Issue Dt:
11/12/2002
Application #:
09563233
Filing Dt:
05/02/2000
Title:
METHOD AND SYSTEM FOR PROACTIVELY DEBUGGING FITTING PROBLEMS IN PROGRAMMABLE LOGIC DEVICES
5
Patent #:
Issue Dt:
11/05/2002
Application #:
09604992
Filing Dt:
06/28/2000
Title:
PROGRAMMABLE NUMBER OF METAL LINES AND EFFECTIVE METAL WIDTH ALONG CRITICAL PATHS IN A PROGRAMMABLE LOGIC DEVICE
6
Patent #:
Issue Dt:
12/31/2002
Application #:
09607697
Filing Dt:
06/30/2000
Title:
LOADABLE DIVIDE-BY-N WITH FIXED DUTY CYCLE
7
Patent #:
Issue Dt:
08/27/2002
Application #:
09736907
Filing Dt:
12/14/2000
Title:
LOW NOISE SWITCHING REGULATOR
8
Patent #:
Issue Dt:
03/04/2003
Application #:
09742758
Filing Dt:
12/20/2000
Title:
LOW NOISE, REDUCED SWING DIFFERENTIAL OUTPUT BUFFER DESIGN
9
Patent #:
Issue Dt:
10/15/2002
Application #:
09792021
Filing Dt:
02/23/2001
Title:
LASER FORMATION OF A METAL CAPACITOR AND INTEGRATED COAXIAL LINE
10
Patent #:
Issue Dt:
01/07/2003
Application #:
09813572
Filing Dt:
03/21/2001
Title:
BUFFER IMPROVEMENT
11
Patent #:
Issue Dt:
05/30/2006
Application #:
09827015
Filing Dt:
04/05/2001
Publication #:
Pub Dt:
05/16/2002
Title:
DEPOPULATED PROGRAMMABLE LOGIC ARRAY
12
Patent #:
Issue Dt:
04/01/2003
Application #:
09836994
Filing Dt:
04/17/2001
Publication #:
Pub Dt:
10/17/2002
Title:
ACTIVE TERMINATION CIRCUIT WITH AN ENABLE/DISABLE
13
Patent #:
Issue Dt:
07/27/2004
Application #:
09877170
Filing Dt:
06/08/2001
Publication #:
Pub Dt:
01/24/2002
Title:
PROGRAMMABLE LOGIC ARRAY EMBEDDED IN MASK-PROGRAMMED ASIC
14
Patent #:
Issue Dt:
02/24/2004
Application #:
10020469
Filing Dt:
10/30/2001
Title:
FUNCTION BLOCK ARCHITECTURE WITH VARIABLE DRIVE STRENGTHS
15
Patent #:
Issue Dt:
06/08/2004
Application #:
10267511
Filing Dt:
10/08/2002
Publication #:
Pub Dt:
01/08/2004
Title:
FIELD PROGRAMMABLE GATE ARRAY WITH CONVERTIBILITY TO APPLICATION SPECIFIC INTEGRATED CIRCUIT
16
Patent #:
Issue Dt:
02/15/2005
Application #:
10413809
Filing Dt:
04/14/2003
Publication #:
Pub Dt:
01/08/2004
Title:
SEMICONDUCTOR SWITCHING DEVICES
17
Patent #:
Issue Dt:
12/07/2004
Application #:
10413810
Filing Dt:
04/14/2003
Publication #:
Pub Dt:
01/08/2004
Title:
SEMICONDUCTOR LATCHES AND SRAM DEVICES
18
Patent #:
Issue Dt:
10/12/2004
Application #:
10458892
Filing Dt:
06/10/2003
Publication #:
Pub Dt:
11/13/2003
Title:
DEPOPULATED PROGRAMMABLE LOGIC ARRAY
19
Patent #:
Issue Dt:
05/09/2006
Application #:
10640171
Filing Dt:
08/12/2003
Publication #:
Pub Dt:
03/11/2004
Title:
IMPLEMENTING PROGRAMMABLE LOGIC ARRAY EMBEDDED IN MASK - PROGRAMMED ASIC
20
Patent #:
Issue Dt:
03/28/2006
Application #:
10762627
Filing Dt:
01/23/2004
Publication #:
Pub Dt:
08/05/2004
Title:
INSULATED-GATE FIELD-EFFECT THIN FILM TRANSISTORS
21
Patent #:
Issue Dt:
02/15/2005
Application #:
10764048
Filing Dt:
01/26/2004
Publication #:
Pub Dt:
08/05/2004
Title:
SEMICONDUCTOR LATCHES AND SRAM DEVICES
22
Patent #:
Issue Dt:
01/31/2006
Application #:
10825194
Filing Dt:
04/16/2004
Publication #:
Pub Dt:
10/07/2004
Title:
PROGRAMMABLE DEVICES WITH CONVERTIBILITY TO CUSTOMIZABLE DEVICES
23
Patent #:
Issue Dt:
02/01/2005
Application #:
10838745
Filing Dt:
05/05/2004
Publication #:
Pub Dt:
10/21/2004
Title:
SEMICONDUCTOR LATCHES AND SRAM DEVICES
24
Patent #:
Issue Dt:
06/20/2006
Application #:
10846698
Filing Dt:
05/17/2004
Publication #:
Pub Dt:
10/28/2004
Title:
METHODS FOR FABRICATING THREE DIMENSIONAL INTEGRATED CIRCUITS
25
Patent #:
Issue Dt:
09/26/2006
Application #:
10846699
Filing Dt:
05/17/2004
Publication #:
Pub Dt:
10/28/2004
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
26
Patent #:
Issue Dt:
02/14/2006
Application #:
10851752
Filing Dt:
05/24/2004
Publication #:
Pub Dt:
10/28/2004
Title:
SEMICONDUCTOR LATCHES AND SRAM DEVICES
27
Patent #:
Issue Dt:
04/17/2007
Application #:
10864092
Filing Dt:
06/08/2004
Publication #:
Pub Dt:
05/05/2005
Title:
SEMICONDUCTOR DEVICES FABRICATED WITH DIFFERENT PROCESSING OPTIONS
28
Patent #:
Issue Dt:
06/20/2006
Application #:
10872594
Filing Dt:
06/22/2004
Publication #:
Pub Dt:
11/11/2004
Title:
ALTERABLE APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC)
29
Patent #:
Issue Dt:
04/18/2006
Application #:
10912697
Filing Dt:
08/06/2004
Publication #:
Pub Dt:
01/13/2005
Title:
SEMICONDUCTOR SWITCHING DEVICES
30
Patent #:
Issue Dt:
08/17/2010
Application #:
10937828
Filing Dt:
09/10/2004
Publication #:
Pub Dt:
02/10/2005
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
31
Patent #:
Issue Dt:
09/04/2007
Application #:
10979024
Filing Dt:
11/02/2004
Publication #:
Pub Dt:
06/09/2005
Title:
INSULATED-GATE FIELD-EFFECT THIN FILM TRANSISTORS
32
Patent #:
Issue Dt:
09/11/2007
Application #:
10988396
Filing Dt:
11/15/2004
Publication #:
Pub Dt:
05/12/2005
Title:
CONFIGURATION CIRCUITS FOR THREE DIMENSIONAL PROGRAMMABLE LOGIC DEVICES
33
Patent #:
Issue Dt:
12/25/2007
Application #:
11102855
Filing Dt:
04/11/2005
Publication #:
Pub Dt:
08/18/2005
Title:
METHODS FOR FABRICATING FUSE PROGRAMMABLE THREE DIMENSIONAL INTEGRATED CIRCUITS
34
Patent #:
Issue Dt:
10/23/2007
Application #:
11357145
Filing Dt:
02/21/2006
Publication #:
Pub Dt:
07/13/2006
Title:
CONFIGURATION CIRCUIT FOR PROGRAMMABLE LOGIC DEVICES
35
Patent #:
Issue Dt:
04/23/2013
Application #:
11363304
Filing Dt:
02/27/2006
Publication #:
Pub Dt:
07/06/2006
Title:
Three dimensional integrated circuits
36
Patent #:
Issue Dt:
10/23/2007
Application #:
11365031
Filing Dt:
03/02/2006
Publication #:
Pub Dt:
07/13/2006
Title:
CONFIGURATION CIRCUITS FOR PROGRAMMABLE LOGIC DEVICES
37
Patent #:
Issue Dt:
04/08/2008
Application #:
11384116
Filing Dt:
03/20/2006
Publication #:
Pub Dt:
07/20/2006
Title:
TIMING EXACT DESIGN CONVERSIONS FROM FPGA TO ASIC
38
Patent #:
Issue Dt:
03/18/2008
Application #:
11400122
Filing Dt:
04/10/2006
Publication #:
Pub Dt:
08/10/2006
Title:
ALTERABLE APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC)
39
Patent #:
Issue Dt:
12/01/2009
Application #:
11645313
Filing Dt:
12/26/2006
Publication #:
Pub Dt:
05/10/2007
Title:
BIT STREAM COMPATIBLE FPGA TO MPGA DESIGN CONVERSIONS
40
Patent #:
Issue Dt:
07/20/2010
Application #:
11801738
Filing Dt:
05/11/2007
Publication #:
Pub Dt:
09/13/2007
Title:
SEMICONDUCTOR DEVICES FABRICATED WITH DIFFERENT PROCESSING OPTIONS
41
Patent #:
Issue Dt:
04/22/2008
Application #:
11801739
Filing Dt:
05/11/2007
Publication #:
Pub Dt:
09/13/2007
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
42
Patent #:
Issue Dt:
11/04/2008
Application #:
11985822
Filing Dt:
11/19/2007
Publication #:
Pub Dt:
03/27/2008
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
43
Patent #:
Issue Dt:
02/04/2014
Application #:
11986023
Filing Dt:
11/19/2007
Publication #:
Pub Dt:
06/11/2009
Title:
PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
44
Patent #:
Issue Dt:
12/09/2008
Application #:
12045635
Filing Dt:
03/10/2008
Publication #:
Pub Dt:
06/26/2008
Title:
ALTERABLE APPLICATION SPECIFIC INTEGRATED CIRCUIT (ASIC)
45
Patent #:
Issue Dt:
07/30/2013
Application #:
12104377
Filing Dt:
04/16/2008
Publication #:
Pub Dt:
09/11/2008
Title:
Timing Exact Design Conversions from FPGA to ASIC
46
Patent #:
Issue Dt:
05/26/2009
Application #:
12105259
Filing Dt:
04/17/2008
Publication #:
Pub Dt:
08/14/2008
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
47
Patent #:
Issue Dt:
02/02/2010
Application #:
12254629
Filing Dt:
10/20/2008
Publication #:
Pub Dt:
02/12/2009
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
48
Patent #:
Issue Dt:
09/09/2014
Application #:
12834077
Filing Dt:
07/12/2010
Publication #:
Pub Dt:
05/05/2011
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
49
Patent #:
Issue Dt:
09/02/2014
Application #:
13411486
Filing Dt:
03/02/2012
Title:
MPGA PRODUCTS BASED ON A PROTOTYPE FPGA
50
Patent #:
Issue Dt:
10/07/2014
Application #:
13609108
Filing Dt:
09/10/2012
Publication #:
Pub Dt:
01/03/2013
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
51
Patent #:
Issue Dt:
01/17/2017
Application #:
13953666
Filing Dt:
07/29/2013
Publication #:
Pub Dt:
11/21/2013
Title:
TIMING EXACT DESIGN CONVERSIONS FROM FPGA TO ASIC
52
Patent #:
Issue Dt:
06/30/2015
Application #:
14147881
Filing Dt:
01/06/2014
Publication #:
Pub Dt:
05/01/2014
Title:
PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
53
Patent #:
Issue Dt:
01/19/2016
Application #:
14458939
Filing Dt:
08/13/2014
Publication #:
Pub Dt:
11/27/2014
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
54
Patent #:
Issue Dt:
06/13/2017
Application #:
14715375
Filing Dt:
05/18/2015
Publication #:
Pub Dt:
01/14/2016
Title:
PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
55
Patent #:
Issue Dt:
03/06/2018
Application #:
14949679
Filing Dt:
11/23/2015
Publication #:
Pub Dt:
05/12/2016
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
56
Patent #:
Issue Dt:
07/02/2019
Application #:
15407242
Filing Dt:
01/16/2017
Publication #:
Pub Dt:
05/04/2017
Title:
TIMING EXACT DESIGN CONVERSIONS FROM FPGA TO ASIC
57
Patent #:
Issue Dt:
05/22/2018
Application #:
15620142
Filing Dt:
06/12/2017
Publication #:
Pub Dt:
09/28/2017
Title:
PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
58
Patent #:
Issue Dt:
10/15/2019
Application #:
15893537
Filing Dt:
02/09/2018
Publication #:
Pub Dt:
06/14/2018
Title:
THREE DIMENSIONAL INTEGRATED CIRCUITS
59
Patent #:
Issue Dt:
05/28/2019
Application #:
15985590
Filing Dt:
05/21/2018
Publication #:
Pub Dt:
09/27/2018
Title:
PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
60
Patent #:
NONE
Issue Dt:
Application #:
16422942
Filing Dt:
05/24/2019
Publication #:
Pub Dt:
09/12/2019
Title:
PADS AND PIN-OUTS IN THREE DIMENSIONAL INTEGRATED CIRCUITS
Assignor
1
Exec Dt:
12/23/2019
Assignee
1
251 LITTLE FALLS DRIVE
WILMINGTON, DELAWARE 19808
Correspondence name and address
INTELLECTUAL VENTURES MANAGEMENT- IP LEGAL
3150 139TH AVENUE SE
BUILDING 4, FLOOR 3
BELLEVUE, WA 98005

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