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Reel/Frame:051489/0324   Pages: 17
Recorded: 01/06/2020
Attorney Dkt #:IBM5-TESSERA_US-APPS
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 79
1
Patent #:
NONE
Issue Dt:
Application #:
11855211
Filing Dt:
09/14/2007
Publication #:
US20090072409
Pub Dt:
03/19/2009
Title:
Interconnect Structures Incorporating Air-Gap Spacers
2
Patent #:
NONE
Issue Dt:
Application #:
11855280
Filing Dt:
09/14/2007
Publication #:
US20090075470
Pub Dt:
03/19/2009
Title:
Method for Manufacturing Interconnect Structures Incorporating Air-Gap Spacers
3
Patent #:
NONE
Issue Dt:
Application #:
13096757
Filing Dt:
04/28/2011
Publication #:
US20110237075
Pub Dt:
09/29/2011
Title:
Method for Manufacturing Interconnect Structures Incorporating Air-Gap Spacers
4
Patent #:
NONE
Issue Dt:
Application #:
13618656
Filing Dt:
09/14/2012
Publication #:
US20130011968
Pub Dt:
01/10/2013
Title:
HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS
5
Patent #:
NONE
Issue Dt:
Application #:
14547181
Filing Dt:
11/19/2014
Publication #:
US20160141360
Pub Dt:
05/19/2016
Title:
III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION
6
Patent #:
NONE
Issue Dt:
Application #:
14817783
Filing Dt:
08/04/2015
Publication #:
US20170040257
Pub Dt:
02/09/2017
Title:
HYBRID SUBTRACTIVE ETCH/METAL FILL PROCESS FOR FABRICATING INTERCONNECTS
7
Patent #:
NONE
Issue Dt:
Application #:
14828551
Filing Dt:
08/18/2015
Publication #:
US20150357328
Pub Dt:
12/10/2015
Title:
STI REGION FOR SMALL FIN PITCH IN FINFET DEVICES
8
Patent #:
NONE
Issue Dt:
Application #:
15222151
Filing Dt:
07/28/2016
Publication #:
US20170148890
Pub Dt:
05/25/2017
Title:
STABLE WORK FUNCTION FOR NARROW-PITCH DEVICES
9
Patent #:
NONE
Issue Dt:
Application #:
15345574
Filing Dt:
11/08/2016
Publication #:
US20170117181
Pub Dt:
04/27/2017
Title:
LOW RESISTANCE CONTACT STRUCTURES INCLUDING A COPPER FILL FOR TRENCH STRUCTURES
10
Patent #:
10553581
Issue Dt:
02/04/2020
Application #:
15371350
Filing Dt:
12/07/2016
Publication #:
US20170352657
Pub Dt:
12/07/2017
Title:
AIR GAP SPACER FOR METAL GATES
11
Patent #:
10607890
Issue Dt:
03/31/2020
Application #:
15450829
Filing Dt:
03/06/2017
Publication #:
US20170178960
Pub Dt:
06/22/2017
Title:
SELECTIVE REMOVAL OF SEMICONDUCTOR FINS
12
Patent #:
10804193
Issue Dt:
10/13/2020
Application #:
15609672
Filing Dt:
05/31/2017
Publication #:
US20170294382
Pub Dt:
10/12/2017
Title:
SEMICONDUCTOR INTERCONNECT STRUCTURE WITH DOUBLE CONDUCTORS
13
Patent #:
10593802
Issue Dt:
03/17/2020
Application #:
15629280
Filing Dt:
06/21/2017
Publication #:
US20180090606
Pub Dt:
03/29/2018
Title:
FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
14
Patent #:
10559670
Issue Dt:
02/11/2020
Application #:
15797648
Filing Dt:
10/30/2017
Publication #:
US20180219083
Pub Dt:
08/02/2018
Title:
NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS
15
Patent #:
10573528
Issue Dt:
02/25/2020
Application #:
15842841
Filing Dt:
12/14/2017
Publication #:
US20190189457
Pub Dt:
06/20/2019
Title:
TWO-COLOR SELF-ALIGNED DOUBLE PATTERNING (SADP) TO YIELD STATIC RANDOM ACCESS MEMORY (SRAM) AND DENSE LOGIC
16
Patent #:
10593616
Issue Dt:
03/17/2020
Application #:
15850446
Filing Dt:
12/21/2017
Publication #:
US20180294214
Pub Dt:
10/11/2018
Title:
REDUCTION OF STRESS IN VIA STRUCTURE
17
Patent #:
10985056
Issue Dt:
04/20/2021
Application #:
15852151
Filing Dt:
12/22/2017
Publication #:
US20180122691
Pub Dt:
05/03/2018
Title:
STRUCTURE AND METHOD TO IMPROVE FAV RIE PROCESS MARGIN AND ELECTROMIGRATION
18
Patent #:
10957584
Issue Dt:
03/23/2021
Application #:
15852176
Filing Dt:
12/22/2017
Publication #:
US20180122692
Pub Dt:
05/03/2018
Title:
STRUCTURE AND METHOD TO IMPROVE FAV RIE PROCESS MARGIN AND ELECTROMIGRATION
19
Patent #:
10553483
Issue Dt:
02/04/2020
Application #:
15897526
Filing Dt:
02/15/2018
Publication #:
US20180174903
Pub Dt:
06/21/2018
Title:
SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE
20
Patent #:
NONE
Issue Dt:
Application #:
16000371
Filing Dt:
06/05/2018
Publication #:
US20180286958
Pub Dt:
10/04/2018
Title:
LOW RESISTANCE CONTACT STRUCTURES FOR TRENCH STRUCTURES
21
Patent #:
10559467
Issue Dt:
02/11/2020
Application #:
16001426
Filing Dt:
06/06/2018
Publication #:
US20180286682
Pub Dt:
10/04/2018
Title:
SELECTIVE GAS ETCHING FOR SELF-ALIGNED PATTERN TRANSFER
22
Patent #:
NONE
Issue Dt:
Application #:
16002479
Filing Dt:
06/07/2018
Publication #:
US20180294339
Pub Dt:
10/11/2018
Title:
LOW RESISTANCE CONTACT STRUCTURES FOR TRENCH STRUCTURES
23
Patent #:
10607991
Issue Dt:
03/31/2020
Application #:
16002590
Filing Dt:
06/07/2018
Publication #:
US20180294263
Pub Dt:
10/11/2018
Title:
AIR GAP SPACER FOR METAL GATES
24
Patent #:
10636706
Issue Dt:
04/28/2020
Application #:
16014020
Filing Dt:
06/21/2018
Publication #:
US20180315653
Pub Dt:
11/01/2018
Title:
SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
25
Patent #:
10832952
Issue Dt:
11/10/2020
Application #:
16014025
Filing Dt:
06/21/2018
Publication #:
US20180315654
Pub Dt:
11/01/2018
Title:
SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
26
Patent #:
10847639
Issue Dt:
11/24/2020
Application #:
16014676
Filing Dt:
06/21/2018
Publication #:
US20180315841
Pub Dt:
11/01/2018
Title:
METHOD AND STRUCTURE FOR FORMING DIELECTRIC ISOLATED FINFET WITH IMPROVED SOURCE/DRAIN EPITAXY
27
Patent #:
10566454
Issue Dt:
02/18/2020
Application #:
16032213
Filing Dt:
07/11/2018
Publication #:
US20180331039
Pub Dt:
11/15/2018
Title:
SELF-ALIGNED CONTACT PROCESS ENABLED BY LOW TEMPERATURE
28
Patent #:
10825689
Issue Dt:
11/03/2020
Application #:
16040093
Filing Dt:
07/19/2018
Publication #:
US20180323073
Pub Dt:
11/08/2018
Title:
Method of Fabricating Semiconductor Fins by Enhancing Oxidation of Sacrificial Mandrels Sidewalls through Angled Ion Beam Exposure
29
Patent #:
10658461
Issue Dt:
05/19/2020
Application #:
16042388
Filing Dt:
07/23/2018
Publication #:
US20180331180
Pub Dt:
11/15/2018
Title:
NANOWIRE WITH SACRIFICIAL TOP WIRE
30
Patent #:
11004933
Issue Dt:
05/11/2021
Application #:
16042498
Filing Dt:
07/23/2018
Publication #:
US20180350909
Pub Dt:
12/06/2018
Title:
Field effect transistor structures
31
Patent #:
10580772
Issue Dt:
03/03/2020
Application #:
16051820
Filing Dt:
08/01/2018
Publication #:
US20180342510
Pub Dt:
11/29/2018
Title:
Two Dimension Material Fin Sidewall
32
Patent #:
10651266
Issue Dt:
05/12/2020
Application #:
16052161
Filing Dt:
08/01/2018
Publication #:
US20180350896
Pub Dt:
12/06/2018
Title:
EFFICIENT METAL-INSULATOR-METAL CAPACITOR
33
Patent #:
10559564
Issue Dt:
02/11/2020
Application #:
16052526
Filing Dt:
08/01/2018
Publication #:
US20180342511
Pub Dt:
11/29/2018
Title:
Two Dimension Material Fin Sidewall
34
Patent #:
10580773
Issue Dt:
03/03/2020
Application #:
16054394
Filing Dt:
08/03/2018
Publication #:
US20180342512
Pub Dt:
11/29/2018
Title:
GATE CUT WITH INTEGRATED ETCH STOP LAYER
35
Patent #:
10665589
Issue Dt:
05/26/2020
Application #:
16054417
Filing Dt:
08/03/2018
Publication #:
US20180350810
Pub Dt:
12/06/2018
Title:
GATE CUT WITH INTEGRATED ETCH STOP LAYER
36
Patent #:
10629709
Issue Dt:
04/21/2020
Application #:
16056940
Filing Dt:
08/07/2018
Publication #:
US20180350959
Pub Dt:
12/06/2018
Title:
PUNCH THROUGH STOPPER IN BULK FINFET DEVICE
37
Patent #:
10615074
Issue Dt:
04/07/2020
Application #:
16057056
Filing Dt:
08/07/2018
Publication #:
US20180342419
Pub Dt:
11/29/2018
Title:
ADVANCED COPPER INTERCONNECTS WITH HYBRID MICROSTRUCTURE
38
Patent #:
10580652
Issue Dt:
03/03/2020
Application #:
16058088
Filing Dt:
08/08/2018
Publication #:
US20180350600
Pub Dt:
12/06/2018
Title:
ALTERNATING HARDMASKS FOR TIGHT-PITCH LINE FORMATION
39
Patent #:
10529569
Issue Dt:
01/07/2020
Application #:
16058232
Filing Dt:
08/08/2018
Publication #:
US20180350599
Pub Dt:
12/06/2018
Title:
SELF ALIGNED PATTERN FORMATION POST SPACER ETCHBACK IN TIGHT PITCH CONFIGURATIONS
40
Patent #:
10629680
Issue Dt:
04/21/2020
Application #:
16103085
Filing Dt:
08/14/2018
Publication #:
US20190006463
Pub Dt:
01/03/2019
Title:
SIDEWALL IMAGE TRANSFER NANOSHEET
41
Patent #:
10615269
Issue Dt:
04/07/2020
Application #:
16106359
Filing Dt:
08/21/2018
Publication #:
US20180374930
Pub Dt:
12/27/2018
Title:
NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION
42
Patent #:
10741449
Issue Dt:
08/11/2020
Application #:
16114816
Filing Dt:
08/28/2018
Publication #:
US20190013244
Pub Dt:
01/10/2019
Title:
STACKED TRANSISTORS WITH DIFFERENT CHANNEL WIDTHS
43
Patent #:
10593591
Issue Dt:
03/17/2020
Application #:
16118998
Filing Dt:
08/31/2018
Publication #:
US20180374748
Pub Dt:
12/27/2018
Title:
INTERCONNECT STRUCTURE
44
Patent #:
NONE
Issue Dt:
Application #:
16213618
Filing Dt:
12/07/2018
Publication #:
US20190221477
Pub Dt:
07/18/2019
Title:
LOW-RESISTIVITY METALLIC INTERCONNECT STRUCTURES WITH SELF-FORMING DIFFUSION BARRIER LAYERS
45
Patent #:
10600693
Issue Dt:
03/24/2020
Application #:
16227733
Filing Dt:
12/20/2018
Publication #:
US20190131179
Pub Dt:
05/02/2019
Title:
FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS
46
Patent #:
10998240
Issue Dt:
05/04/2021
Application #:
16234974
Filing Dt:
12/28/2018
Publication #:
US20190139832
Pub Dt:
05/09/2019
Title:
FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REDUCED DIMENSIONAL VARIATIONS
47
Patent #:
10854753
Issue Dt:
12/01/2020
Application #:
16238193
Filing Dt:
01/02/2019
Publication #:
US20190140090
Pub Dt:
05/09/2019
Title:
UNIFORM FIN DIMENSIONS USING FIN CUT HARDMASK
48
Patent #:
10600868
Issue Dt:
03/24/2020
Application #:
16244493
Filing Dt:
01/10/2019
Publication #:
US20190189517
Pub Dt:
06/20/2019
Title:
FINFET GATE CUT AFTER DUMMY GATE REMOVAL
49
Patent #:
10672707
Issue Dt:
06/02/2020
Application #:
16250351
Filing Dt:
01/17/2019
Publication #:
US20190148296
Pub Dt:
05/16/2019
Title:
LOW ASPECT RATIO INTERCONNECT
50
Patent #:
10763166
Issue Dt:
09/01/2020
Application #:
16250561
Filing Dt:
01/17/2019
Publication #:
US20190157146
Pub Dt:
05/23/2019
Title:
SELF-FORMING BARRIER FOR USE IN AIR GAP FORMATION
51
Patent #:
10727315
Issue Dt:
07/28/2020
Application #:
16252663
Filing Dt:
01/20/2019
Publication #:
US20190157420
Pub Dt:
05/23/2019
Title:
NANOSHEET TRANSISTOR
52
Patent #:
10930553
Issue Dt:
02/23/2021
Application #:
16257221
Filing Dt:
01/25/2019
Publication #:
US20190172748
Pub Dt:
06/06/2019
Title:
FORMING SELF-ALIGNED VIAS AND AIR-GAPS IN SEMICONDUCTOR FABRICATION
53
Patent #:
10763326
Issue Dt:
09/01/2020
Application #:
16261305
Filing Dt:
01/29/2019
Publication #:
US20190157388
Pub Dt:
05/23/2019
Title:
MIDDLE-OF-LINE (MOL) CAPACITANCE REDUCTION FOR SELF-ALIGNED CONTACT IN GATE STACK
54
Patent #:
10699962
Issue Dt:
06/30/2020
Application #:
16265110
Filing Dt:
02/01/2019
Publication #:
US20190181049
Pub Dt:
06/13/2019
Title:
FINFET DEVICES
55
Patent #:
10700195
Issue Dt:
06/30/2020
Application #:
16276118
Filing Dt:
02/14/2019
Publication #:
US20190181263
Pub Dt:
06/13/2019
Title:
REDUCED RESISTANCE SOURCE AND DRAIN EXTENSIONS IN VERTICAL FIELD EFFECT TRANSISTORS
56
Patent #:
10923471
Issue Dt:
02/16/2021
Application #:
16296433
Filing Dt:
03/08/2019
Publication #:
US20190206865
Pub Dt:
07/04/2019
Title:
MINIMIZING SHORTING BETWEEN FINFET EPITAXIAL REGIONS
57
Patent #:
NONE
Issue Dt:
Application #:
16352946
Filing Dt:
03/14/2019
Publication #:
US20190214339
Pub Dt:
07/11/2019
Title:
REDUCTION OF STRESS IN VIA STRUCTURE
58
Patent #:
11121233
Issue Dt:
09/14/2021
Application #:
16391622
Filing Dt:
04/23/2019
Publication #:
US20190252516
Pub Dt:
08/15/2019
Title:
FORMING NANOSHEET TRANSISTOR USING SACRIFICIAL SPACER AND INNER SPACERS
59
Patent #:
10937861
Issue Dt:
03/02/2021
Application #:
16399845
Filing Dt:
04/30/2019
Publication #:
US20190259831
Pub Dt:
08/22/2019
Title:
SEMICONDUCTOR STRUCTURES INCLUDING MIDDLE-OF-LINE (MOL) CAPACITANCE REDUCTION FOR SELF-ALIGNED CONTACT IN GATE STACK
60
Patent #:
10546926
Issue Dt:
01/28/2020
Application #:
16402267
Filing Dt:
05/03/2019
Publication #:
US20190259834
Pub Dt:
08/22/2019
Title:
III-V SEMICONDUCTOR DEVICES WITH SELECTIVE OXIDATION
61
Patent #:
10651078
Issue Dt:
05/12/2020
Application #:
16406115
Filing Dt:
05/08/2019
Publication #:
US20190267278
Pub Dt:
08/29/2019
Title:
SELECTIVE ILD DEPOSITION FOR FULLY ALIGNED VIA WITH AIRGAP
62
Patent #:
11658062
Issue Dt:
05/23/2023
Application #:
16410178
Filing Dt:
05/13/2019
Publication #:
US20190267279
Pub Dt:
08/29/2019
Title:
AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES
63
Patent #:
10629529
Issue Dt:
04/21/2020
Application #:
16421587
Filing Dt:
05/24/2019
Publication #:
US20190279931
Pub Dt:
09/12/2019
Title:
Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
64
Patent #:
10734492
Issue Dt:
08/04/2020
Application #:
16440106
Filing Dt:
06/13/2019
Publication #:
US20190296120
Pub Dt:
09/26/2019
Title:
ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE
65
Patent #:
11456354
Issue Dt:
09/27/2022
Application #:
16452251
Filing Dt:
06/25/2019
Publication #:
US20190312104
Pub Dt:
10/10/2019
Title:
Bulk Nanosheet with Dielectric Isolation
66
Patent #:
NONE
Issue Dt:
Application #:
16454178
Filing Dt:
06/27/2019
Publication #:
US20190318966
Pub Dt:
10/17/2019
Title:
HIGH K METAL GATE STACK WITH SINGLE WORK-FUNCTION METAL
67
Patent #:
10818759
Issue Dt:
10/27/2020
Application #:
16459685
Filing Dt:
07/02/2019
Publication #:
US20190326406
Pub Dt:
10/24/2019
Title:
SELF ALIGNED REPLACEMENT METAL SOURCE/DRAIN FINFET
68
Patent #:
11342230
Issue Dt:
05/24/2022
Application #:
16505063
Filing Dt:
07/08/2019
Publication #:
US20190333824
Pub Dt:
10/31/2019
Title:
HOMOGENEOUS DENSIFICATION OF FILL LAYERS FOR CONTROLLED REVEAL OF VERTICAL FINS
69
Patent #:
11031248
Issue Dt:
06/08/2021
Application #:
16508691
Filing Dt:
07/11/2019
Publication #:
US20190333774
Pub Dt:
10/31/2019
Title:
ALTERNATING HARDMASKS FOR TIGHT-PITCH LINE FORMATION
70
Patent #:
10770347
Issue Dt:
09/08/2020
Application #:
16657169
Filing Dt:
10/18/2019
Publication #:
US20200051854
Pub Dt:
02/13/2020
Title:
INTERCONNECT STRUCTURE
71
Patent #:
11380589
Issue Dt:
07/05/2022
Application #:
16662845
Filing Dt:
10/24/2019
Publication #:
US20200058554
Pub Dt:
02/20/2020
Title:
SELECTIVE REMOVAL OF SEMICONDUCTOR FINS
72
Patent #:
11018007
Issue Dt:
05/25/2021
Application #:
16675630
Filing Dt:
11/06/2019
Publication #:
US20200075336
Pub Dt:
03/05/2020
Title:
SELF ALIGNED PATTERN FORMATION POST SPACER ETCHBACK IN TIGHT PITCH CONFIGURATIONS
73
Patent #:
11276612
Issue Dt:
03/15/2022
Application #:
16681347
Filing Dt:
11/12/2019
Publication #:
US20200098642
Pub Dt:
03/26/2020
Title:
HYBRID-CHANNEL NANO-SHEET FETS
74
Patent #:
10930504
Issue Dt:
02/23/2021
Application #:
16682588
Filing Dt:
11/13/2019
Publication #:
US20200083045
Pub Dt:
03/12/2020
Title:
SELECTIVE GAS ETCHING FOR SELF-ALIGNED PATTERN TRANSFER
75
Patent #:
11342446
Issue Dt:
05/24/2022
Application #:
16684115
Filing Dt:
11/14/2019
Publication #:
US20200098893
Pub Dt:
03/26/2020
Title:
NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS
76
Patent #:
11189729
Issue Dt:
11/30/2021
Application #:
16685229
Filing Dt:
11/15/2019
Publication #:
US20200083364
Pub Dt:
03/12/2020
Title:
FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
77
Patent #:
11094824
Issue Dt:
08/17/2021
Application #:
16685329
Filing Dt:
11/15/2019
Publication #:
US20200091336
Pub Dt:
03/19/2020
Title:
FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
78
Patent #:
10804147
Issue Dt:
10/13/2020
Application #:
16689142
Filing Dt:
11/20/2019
Publication #:
US20200090993
Pub Dt:
03/19/2020
Title:
SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE
79
Patent #:
11222815
Issue Dt:
01/11/2022
Application #:
16689223
Filing Dt:
11/20/2019
Publication #:
US20200090994
Pub Dt:
03/19/2020
Title:
SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE
Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
12/27/2019
Assignee
1
TESSERA, INC.
3025 ORCHARD PARKWAY
SAN JOSE, CALIFORNIA 95134
Correspondence name and address
TESSERA, INC.
3025 ORCHARD PARKWAY
SAN JOSE, CA 95134

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