|
Total properties:
83
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Patent #:
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|
Issue Dt:
|
05/27/2003
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Application #:
|
09562700
|
Filing Dt:
|
04/28/2000
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Title:
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SEMICONDUCTOR DEVICE FABRICATION USING A PHOTOMASK DESIGNED USING MODELING AND EMPIRICAL TESTING
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Patent #:
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Issue Dt:
|
07/02/2002
|
Application #:
|
09636522
|
Filing Dt:
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08/10/2000
|
|
Title:
|
METHOD FOR FABRICATING A MICROTECHNICAL STRUCTURE
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Patent #:
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|
Issue Dt:
|
05/06/2003
|
Application #:
|
09663569
|
Filing Dt:
|
09/15/2000
|
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Title:
|
PATTERNING OF CONTACT AREAS IN MULTILAYER METALIZATION CONFIGURATIONS OF SEMICONDUCTOR COMPONENTS
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Patent #:
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Issue Dt:
|
04/27/2004
|
Application #:
|
09767393
|
Filing Dt:
|
01/23/2001
|
|
Publication #:
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|
Pub Dt:
|
08/09/2001
| | | | |
|
Title:
|
INTEGRATED CIRCUIT HAVING A SELF-TEST DEVICE FOR CARRYING OUT A SELF-TEST OF THE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
12/31/2002
|
Application #:
|
09784768
|
Filing Dt:
|
02/15/2001
|
|
Publication #:
|
|
Pub Dt:
|
10/11/2001
| | | | |
|
Title:
|
FUSE CONFIGURATION FOR A SEMICONDUCTOR APPARATUS
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|
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|
Patent #:
|
|
Issue Dt:
|
11/12/2002
|
Application #:
|
09794055
|
Filing Dt:
|
02/28/2001
|
|
Title:
|
DRY POLYMER AND OXIDE VEIL REMOVAL FOR POST ETCH CLEANING
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Patent #:
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Issue Dt:
|
08/27/2002
|
Application #:
|
09824596
|
Filing Dt:
|
04/02/2001
|
|
Publication #:
|
|
Pub Dt:
|
07/25/2002
| | | | |
|
Title:
|
METAL HARD MASK FOR ILD RIE PROCESSING OF SEMICONDUCTOR MEMORY DEVICES TO PREVENT OXIDATION OF CONDUCTIVE LINES
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Patent #:
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|
Issue Dt:
|
04/08/2003
|
Application #:
|
09833008
|
Filing Dt:
|
04/11/2001
|
|
Publication #:
|
|
Pub Dt:
|
11/01/2001
| | | | |
|
Title:
|
INTEGRATED SEMICONDUCTOR CIRCUIT, IN PARTICULAR A SEMICONDUCTOR MEMORY CONFIGURATION, AND METHOD FOR ITS OPERATION
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|
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|
Patent #:
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Issue Dt:
|
01/20/2004
|
Application #:
|
09853474
|
Filing Dt:
|
05/11/2001
|
|
Publication #:
|
|
Pub Dt:
|
11/15/2001
| | | | |
|
Title:
|
FIELD-EFFECT TRANSISTOR STRUCTURE WITH AN INSULATED GATE
|
|
|
|
|
Patent #:
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|
Issue Dt:
|
04/08/2003
|
Application #:
|
09867257
|
Filing Dt:
|
05/29/2001
|
|
Publication #:
|
|
Pub Dt:
|
12/27/2001
| | | | |
|
Title:
|
FUSE CIRCUIT CONFIGURATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2002
|
Application #:
|
09867486
|
Filing Dt:
|
05/30/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/10/2002
| | | | |
|
Title:
|
SEMICONDUCTOR CONFIGURATION HAVING AN OPTICAL FUSE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/2004
|
Application #:
|
09882289
|
Filing Dt:
|
06/15/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2002
| | | | |
|
Title:
|
METHOD FOR FABRICATING A BARRIER LAYER
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|
Patent #:
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|
Issue Dt:
|
04/13/2004
|
Application #:
|
09883822
|
Filing Dt:
|
06/18/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/24/2002
| | | | |
|
Title:
|
INTEGRATED CIRCUIT WITH TEST MODE, AND TEST CONFIGURATION FOR TESTING AN INTEGRATED CIRCUIT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/06/2002
|
Application #:
|
09888034
|
Filing Dt:
|
06/22/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/17/2002
| | | | |
|
Title:
|
CONNECTION ELEMENT
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|
|
|
|
Patent #:
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|
Issue Dt:
|
09/24/2002
|
Application #:
|
09898233
|
Filing Dt:
|
07/03/2001
|
|
Publication #:
|
|
Pub Dt:
|
05/09/2002
| | | | |
|
Title:
|
CIRCUIT CONFIGURATION FOR SWITCHING OVER A RECEIVER CIRCUIT IN PARTICULAR IN DRAM MEMORIES AND DRAM MEMORY HAVING THE CIRCUIT CONFIGURATION
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Patent #:
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Issue Dt:
|
12/17/2002
|
Application #:
|
09898261
|
Filing Dt:
|
07/03/2001
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|
Publication #:
|
|
Pub Dt:
|
02/21/2002
| | | | |
|
Title:
|
CHIP ID REGISTER CONFIGURATION
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|
Patent #:
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Issue Dt:
|
03/11/2003
|
Application #:
|
09904799
|
Filing Dt:
|
07/13/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/16/2003
| | | | |
|
Title:
|
METHOD FOR HIGH ASPECT RATIO GAP FILL USING SEQUENTIAL HDP-CVD
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|
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|
Patent #:
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|
Issue Dt:
|
07/22/2003
|
Application #:
|
09932899
|
Filing Dt:
|
08/20/2001
|
|
Publication #:
|
|
Pub Dt:
|
02/21/2002
| | | | |
|
Title:
|
METHOD AND DEVICE FOR PRODUCING A METAL/METAL CONTACT IN A MULTILAYER METALLIZATION OF AN INTEGRATED CIRCUIT
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|
|
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Patent #:
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|
Issue Dt:
|
03/23/2004
|
Application #:
|
09941955
|
Filing Dt:
|
08/28/2001
|
|
Publication #:
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|
Pub Dt:
|
03/21/2002
| | | | |
|
Title:
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METHOD FOR PRODUCING AN ELECTRICALLY CONDUCTING CONNECTION
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|
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Patent #:
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|
Issue Dt:
|
10/15/2002
|
Application #:
|
09966332
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Filing Dt:
|
09/28/2001
|
|
Title:
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METHOD OF FORMING A SELF-ALIGNED ANTIFUSE LINK
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|
|
|
|
Patent #:
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|
Issue Dt:
|
08/05/2003
|
Application #:
|
09978398
|
Filing Dt:
|
10/16/2001
|
|
Publication #:
|
|
Pub Dt:
|
04/18/2002
| | | | |
|
Title:
|
CONFIGURATION FOR FUSE INITIALIZATION
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|
|
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|
Patent #:
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|
Issue Dt:
|
02/03/2004
|
Application #:
|
10010977
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Filing Dt:
|
12/06/2001
|
|
Publication #:
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|
Pub Dt:
|
06/12/2003
| | | | |
|
Title:
|
SYSTEM AND METHOD FOR STORING PARITY INFORMATION IN FUSES
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|
|
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|
Patent #:
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Issue Dt:
|
11/04/2003
|
Application #:
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10017036
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Filing Dt:
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12/14/2001
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|
Publication #:
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|
Pub Dt:
|
06/19/2003
| | | | |
|
Title:
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SELF-TERMINATING BLOW PROCESS OF ELECTRICAL ANTI-FUSES
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Patent #:
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Issue Dt:
|
04/01/2003
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Application #:
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10052201
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Filing Dt:
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01/17/2002
|
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Title:
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PROCESS FOR IMPLEMENTATION OF A HARDMASK
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Patent #:
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Issue Dt:
|
03/09/2004
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Application #:
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10053983
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Filing Dt:
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01/22/2002
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|
Publication #:
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|
Pub Dt:
|
07/25/2002
| | | | |
|
Title:
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METHOD AND CIRCUIT CONFIGURATION FOR IDENTIFYING AN OPERATING PROPERTY OF AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
|
08/10/2004
|
Application #:
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10134152
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Filing Dt:
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04/29/2002
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|
Publication #:
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|
Pub Dt:
|
10/31/2002
| | | | |
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Title:
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CIRCUIT FOR SYNCHRONIZING SIGNALS DURING THE EXCHANGE OF INFORMATION BETWEEN CIRCUITS
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Patent #:
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Issue Dt:
|
02/22/2005
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Application #:
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10151990
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Filing Dt:
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05/21/2002
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Publication #:
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Pub Dt:
|
03/27/2003
| | | | |
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Title:
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METHOD FOR TESTING SEMICONDUCTOR CHIPS
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10196698
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Filing Dt:
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07/16/2002
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Publication #:
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Pub Dt:
|
01/16/2003
| | | | |
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Title:
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PROCESS FOR DEPOSITING WSIX LAYERS ON A HIGH TOPOGRAPHY WITH A DEFINED STOICHIOMETRY
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Patent #:
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Issue Dt:
|
05/24/2005
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Application #:
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10232070
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Filing Dt:
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08/30/2002
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Publication #:
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Pub Dt:
|
03/06/2003
| | | | |
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Title:
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METHOD FOR TESTING CIRCUIT UNITS TO BE TESTED WITH INCREASED DATA COMPRESSION FOR BURN-IN
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10234078
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Filing Dt:
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09/03/2002
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Publication #:
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Pub Dt:
|
03/13/2003
| | | | |
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Title:
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ELECTRONIC CIRCUIT FOR GENERATING AN OUTPUT VOLTAGE HAVING A DEFINED TEMPERATURE DEPENDENCE
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Patent #:
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Issue Dt:
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09/07/2004
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Application #:
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10247574
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Filing Dt:
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09/19/2002
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Publication #:
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Pub Dt:
|
04/10/2003
| | | | |
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Title:
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WAFER WITH ADDITIONAL CIRCUIT PARTS IN THE KERF AREA FOR TESTING INTEGRATED CIRCUITS ON THE WAFER
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10254467
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Filing Dt:
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09/24/2002
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Publication #:
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Pub Dt:
|
03/25/2004
| | | | |
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Title:
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SYSTEM AND METHOD FOR ENABLING A VENDOR MODE ON AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/06/2004
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Application #:
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10284995
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Filing Dt:
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10/31/2002
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Publication #:
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Pub Dt:
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05/06/2004
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Title:
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METHOD AND CIRCUIT FOR CONTROLLING FUSE BLOW
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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10292866
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Filing Dt:
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11/12/2002
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Publication #:
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Pub Dt:
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05/15/2003
| | | | |
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Title:
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REFLECTION MASK FOR EUV-LITHOGRAPHY AND METHOD FOR FABRICATING THE REFLECTION MASK
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Patent #:
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Issue Dt:
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06/21/2005
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10294329
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Filing Dt:
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11/14/2002
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Publication #:
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Pub Dt:
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05/20/2004
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Title:
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HIGH DENSITY DRAM WITH REDUCED PERIPHERAL DEVICE AREA AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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02/28/2006
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Application #:
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10370857
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Filing Dt:
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02/20/2003
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Publication #:
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Pub Dt:
|
08/21/2003
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Title:
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METHOD FOR FORMING A HARD MASK IN A LAYER ON A PLANAR DEVICE
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10378244
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Filing Dt:
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03/03/2003
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Publication #:
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Pub Dt:
|
09/04/2003
| | | | |
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Title:
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METHOD FOR FILLING DEPRESSIONS ON A SEMICONDUCTOR WAFER
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Patent #:
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Issue Dt:
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03/08/2005
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Application #:
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10454518
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Filing Dt:
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06/04/2003
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Publication #:
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Pub Dt:
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11/06/2003
| | | | |
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Title:
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SEMICONDUCTOR CONFIGURATION AND PROCESS FOR ETCHING A LAYER OF THE SEMICONDUCTOR CONFIGURATION USING A SILICON-CONTAINING ETCHING MASK
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Patent #:
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Issue Dt:
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07/19/2005
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Application #:
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10477620
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Filing Dt:
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11/14/2003
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Publication #:
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Pub Dt:
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07/29/2004
| | | | |
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Title:
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PRODUCTION METHOD FOR A SEMICONDUCTOR COMPONENT
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Patent #:
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Issue Dt:
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11/18/2008
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Application #:
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10479733
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Filing Dt:
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06/02/2004
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Publication #:
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Pub Dt:
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10/21/2004
| | | | |
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Title:
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METHOD FOR THE FORMATION OF CONTACT HOLES FOR A NUMBER OF CONTACT REGIONS FOR COMPONENTS INTEGRATED IN A SUBSTRATE
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Patent #:
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Issue Dt:
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05/06/2008
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Application #:
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10494063
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Filing Dt:
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01/07/2005
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Publication #:
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Pub Dt:
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05/26/2005
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Title:
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PHOTOLITHOGRAPHIC PATTERNING PROCESS USING A CARBON HARD MASK LAYER OF DIAMOND-LIKE HARDNESS PRODUCED BY A PLASMA-ENHANCED DEPOSITION PROCESS
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Issue Dt:
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07/08/2008
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10519741
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Filing Dt:
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11/04/2005
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Publication #:
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Pub Dt:
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05/04/2006
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Title:
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METHOD FOR CONTACTING PARTS OF A COMPONENT INTEGRATED INTO A SEMICONDUCTOR SUBSTRATE
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Patent #:
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Issue Dt:
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07/27/2004
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Application #:
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10600408
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Filing Dt:
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06/20/2003
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Publication #:
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Pub Dt:
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02/26/2004
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Title:
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CIRCUIT CONFIGURATION FOR DRIVING A PROGRAMMABLE LINK
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Patent #:
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Issue Dt:
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11/02/2004
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Application #:
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10627841
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Filing Dt:
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07/25/2003
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Publication #:
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Pub Dt:
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08/12/2004
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Title:
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CIRCUIT CONFIGURATION FOR READING OUT A PROGRAMMABLE LINK
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Issue Dt:
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06/29/2004
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10647614
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08/25/2003
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Pub Dt:
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02/26/2004
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Title:
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METHOD FOR ETCHING A HARD MASK LAYER AND A METAL LAYER
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10663448
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Filing Dt:
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09/16/2003
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Publication #:
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Pub Dt:
|
07/01/2004
| | | | |
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Title:
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SEMICONDUCTOR DEVICE TESTING APPARATUS, SEMICONDUCTOR DEVICE TESTING SYSTEM, AND SEMICONDUCTOR DEVICE TESTING METHOD FOR MEASURING AND TRIMMING THE OUTPUT IMPEDANCE OF DRIVER DEVICES
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Issue Dt:
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11/20/2007
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10743105
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12/23/2003
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Publication #:
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Pub Dt:
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07/15/2004
| | | | |
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Title:
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METHOD FOR FORMING A STRUCTURE ELEMENT ON A WAFER BY MEANS OF A MASK AND A TRIMMING MASK ASSIGNED HERETO
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01/30/2007
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10808190
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03/24/2004
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09/29/2005
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Title:
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TEMPERATURE SENSOR SCHEME
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01/13/2009
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10831001
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04/23/2004
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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INPUT RECEIVER CIRCUIT
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Issue Dt:
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03/20/2007
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Application #:
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10870100
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Filing Dt:
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06/17/2004
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Publication #:
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Pub Dt:
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12/22/2005
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Title:
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INPUT RETURN PATH BASED ON VDDQ/VSSQ
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Patent #:
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Issue Dt:
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10/24/2006
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Application #:
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10886017
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Filing Dt:
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07/07/2004
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Publication #:
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Pub Dt:
|
04/07/2005
| | | | |
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Title:
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INTEGRATED SEMICONDUCTOR CIRCUIT WITH AN ELECTRICALLY PROGRAMMABLE SWITCHING ELEMENT
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Patent #:
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Issue Dt:
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09/02/2008
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Application #:
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10940382
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Filing Dt:
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09/14/2004
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Publication #:
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Pub Dt:
|
02/10/2005
| | | | |
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Title:
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SYSTEM AND METHOD FOR ENABLING A VENDOR MODE ON AN INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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07/24/2007
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Application #:
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10946024
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Filing Dt:
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09/21/2004
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Publication #:
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Pub Dt:
|
03/23/2006
| | | | |
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Title:
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SEMICONDUCTOR DEVICE WITH TEST CIRCUIT DISCONNECTED FROM POWER SUPPLY CONNECTION
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Patent #:
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Issue Dt:
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12/26/2006
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Application #:
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10948562
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Filing Dt:
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09/24/2004
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Publication #:
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Pub Dt:
|
03/31/2005
| | | | |
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Title:
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INTEGRATED MEMORY AND METHOD FOR FUNCTIONAL TESTING OF THE INTEGRATED MEMORY
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Patent #:
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Issue Dt:
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12/11/2007
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10988541
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Filing Dt:
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11/16/2004
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Pub Dt:
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05/19/2005
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Title:
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INPUT SWITCHING ARRANGEMENT FOR A SEMICONDUCTOR CIRCUIT AND TEST METHOD FOR UNIDIRECTIONAL INPUT DRIVERS IN SEMICONDUCTOR CIRCUITS
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08/28/2007
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11013870
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12/16/2004
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06/22/2006
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Title:
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MEMORY HAVING TEST CIRCUIT
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01/08/2008
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11031716
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01/07/2005
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07/13/2006
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Title:
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HIGH DIELECTRIC CONSTANT MATERIALS
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12/25/2007
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11169812
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06/29/2005
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01/12/2006
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Title:
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11/20/2007
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11175280
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07/07/2005
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01/11/2007
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Title:
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METHOD AND APPARATUS FOR SELECTIVELY ACCESSING AND CONFIGURING INDIVIDUAL CHIPS OF A SEMI-CONDUCTOR WAFER
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05/06/2008
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11182066
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07/15/2005
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02/02/2006
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Title:
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11/06/2007
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11194489
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08/01/2005
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02/01/2007
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Title:
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02/19/2008
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11210055
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08/23/2005
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03/08/2007
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Title:
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FUSE RESISTANCE READ-OUT CIRCUIT
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02/27/2007
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11212919
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08/29/2005
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03/02/2006
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Title:
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11/25/2008
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11314605
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12/21/2005
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06/21/2007
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Title:
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RANDOM ACCESS MEMORY INCLUDING CIRCUIT TO COMPRESS COMPARISON RESULTS
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01/22/2008
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11316379
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12/22/2005
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08/03/2006
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11/20/2007
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11319793
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12/29/2005
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07/05/2007
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METHOD FOR FABRICATING AN INTEGRATED CIRCUIT ON A SEMICONDUCTOR SUBSTRATE
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03/25/2008
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11343357
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01/31/2006
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09/07/2006
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Title:
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MEMORY DEVICE AND METHOD FOR TESTING MEMORY DEVICES WITH REPAIRABLE REDUNDANCY
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04/22/2008
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11385340
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03/21/2006
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09/27/2007
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11/25/2008
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11386176
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03/22/2006
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10/18/2007
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08/19/2008
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11386360
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03/22/2006
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09/27/2007
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MEMORY INCLUDING A WRITE TRAINING BLOCK
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03/11/2008
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11402412
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04/12/2006
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08/24/2006
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09/29/2009
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11588591
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10/27/2006
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05/01/2008
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MANUFACTURING METHOD FOR AN INTEGRATED SEMICONDUCTOR STRUCTURE
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07/21/2009
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11644090
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12/21/2006
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06/26/2008
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SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
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11/16/2010
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03/30/2007
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10/25/2007
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04/17/2012
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11744962
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05/07/2007
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11/13/2008
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05/03/2011
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08/28/2007
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03/05/2009
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02/15/2011
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08/06/2009
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08/23/2011
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08/28/2008
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05/15/2012
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11/19/2009
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12/23/2014
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03/04/2010
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01/18/2011
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04/15/2010
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08/14/2012
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05/20/2010
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