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NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	052121/0505			Pages:	11
		Recorded:	03/16/2020
Conveyance:	SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 44

Patent #:	7614029	Issue Dt:	11/03/2009	Application #:	11650238	Filing Dt:	01/05/2007
Publication #:	US20080168407	Pub Dt:	07/10/2008
Title:	METHODS AND SYSTEMS FOR CONVERTING A SYNCHRONOUS CIRCUIT FABRIC INTO AN ASYNCHRONOUS DATAFLOW CIRCUIT FABRIC

Patent #:	7505304	Issue Dt:	03/17/2009	Application #:	11740168	Filing Dt:	04/25/2007
Publication #:	US20070253240	Pub Dt:	11/01/2007
Title:	FAULT TOLERANT ASYNCHRONOUS CIRCUITS

Patent #:	7504851	Issue Dt:	03/17/2009	Application #:	11740180	Filing Dt:	04/25/2007
Publication #:	US20070262786	Pub Dt:	11/15/2007
Title:	FAULT TOLERANT ASYNCHRONOUS CIRCUITS

Patent #:	7610567	Issue Dt:	10/27/2009	Application #:	11740184	Filing Dt:	04/25/2007
Publication #:	US20070256038	Pub Dt:	11/01/2007
Title:	SYSTEMS AND METHODS FOR PERFORMING AUTOMATED CONVERSION OF REPRESENTATIONS OF SYNCHRONOUS CIRCUIT DESIGNS TO AND FROM REPRESENTATIONS OF ASYNCHRONOUS CIRCUIT DESIGNS

Patent #:	8104004	Issue Dt:	01/24/2012	Application #:	12030531	Filing Dt:	02/13/2008
Publication #:	US20090201044	Pub Dt:	08/13/2009
Title:	LOGIC PERFORMANCE IN CYCLIC STRUCTURES

Patent #:	7739628	Issue Dt:	06/15/2010	Application #:	12031992	Filing Dt:	02/15/2008
Publication #:	US20090210847	Pub Dt:	08/20/2009
Title:	SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION

Patent #:	7741864	Issue Dt:	06/22/2010	Application #:	12240430	Filing Dt:	09/29/2008
Publication #:	US20090027078	Pub Dt:	01/29/2009
Title:	FAULT TOLERANT ASYNCHRONOUS CIRCUITS

Patent #:	7880499	Issue Dt:	02/01/2011	Application #:	12304694	Filing Dt:	05/26/2009
Publication #:	US20100013517	Pub Dt:	01/21/2010
Title:	RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS

Patent #:	8004877	Issue Dt:	08/23/2011	Application #:	12405746	Filing Dt:	03/17/2009
Publication #:	US20090279346	Pub Dt:	11/12/2009
Title:	FAULT TOLERANT ASYNCHRONOUS CIRCUITS

Patent #:	8964795	Issue Dt:	02/24/2015	Application #:	12475744	Filing Dt:	06/01/2009
Publication #:	US20100303067	Pub Dt:	12/02/2010
Title:	ASYNCHRONOUS PIPELINED INTERCONNECT ARCHITECTURE WITH FANOUT SUPPORT

Patent #:	8191019	Issue Dt:	05/29/2012	Application #:	12505296	Filing Dt:	07/17/2009
Publication #:	US20110012666	Pub Dt:	01/20/2011
Title:	NON-PREDICATED TO PREDICATED CONVERSION OF ASYNCHRONOUS REPRESENTATIONS

Patent #:	8161435	Issue Dt:	04/17/2012	Application #:	12505653	Filing Dt:	07/20/2009
Publication #:	US20110016439	Pub Dt:	01/20/2011
Title:	RESET MECHANISM CONVERSION

Patent #:	8453079	Issue Dt:	05/28/2013	Application #:	12550582	Filing Dt:	08/31/2009
Publication #:	US20090319962	Pub Dt:	12/24/2009
Title:	AUTOMATED CONVERSION OF SYNCHRONOUS TO ASYNCHRONOUS CIRCUIT DESIGN REPRESENTATIONS

Patent #:	8375339	Issue Dt:	02/12/2013	Application #:	12555903	Filing Dt:	09/09/2009
Publication #:	US20100005431	Pub Dt:	01/07/2010
Title:	CONVERTING A SYNCHRONOUS CIRCUIT DESIGN INTO AN ASYNCHRONOUS DESIGN

Patent #:	8300635	Issue Dt:	10/30/2012	Application #:	12557287	Filing Dt:	09/10/2009
Publication #:	US20110058570	Pub Dt:	03/10/2011
Title:	PROGRAMMABLE CROSSBAR STRUCTURES IN ASYNCHRONOUS SYSTEMS

Patent #:	8228101	Issue Dt:	07/24/2012	Application #:	12558985	Filing Dt:	09/14/2009
Publication #:	US20110062999	Pub Dt:	03/17/2011
Title:	SOURCE-SYNCHRONOUS CLOCKING

Patent #:	8072250	Issue Dt:	12/06/2011	Application #:	12559009	Filing Dt:	09/14/2009
Publication #:	US20110062997	Pub Dt:	03/17/2011
Title:	RESET SIGNAL DISTRIBUTION

Patent #:	8638138	Issue Dt:	01/28/2014	Application #:	12559040	Filing Dt:	09/14/2009
Publication #:	US20110063000	Pub Dt:	03/17/2011
Title:	HIERARCHICAL GLOBAL CLOCK TREE

Patent #:	7900078	Issue Dt:	03/01/2011	Application #:	12559069	Filing Dt:	09/14/2009
Publication #:	US20110062987	Pub Dt:	03/17/2011
Title:	ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS

Patent #:	8301933	Issue Dt:	10/30/2012	Application #:	12559102	Filing Dt:	09/14/2009
Publication #:	US20110066873	Pub Dt:	03/17/2011
Title:	MULTI-CLOCK ASYNCHRONOUS LOGIC CIRCUITS

Patent #:	7982502	Issue Dt:	07/19/2011	Application #:	12559573	Filing Dt:	09/15/2009
Publication #:	US20110062991	Pub Dt:	03/17/2011
Title:	ASYNCHRONOUS CIRCUIT REPRESENTATION OF SYNCHRONOUS CIRCUIT WITH ASYNCHRONOUS INPUTS

Patent #:	8234607	Issue Dt:	07/31/2012	Application #:	12559612	Filing Dt:	09/15/2009
Publication #:	US20110066986	Pub Dt:	03/17/2011
Title:	TOKEN ENHANCED ASYNCHRONOUS CONVERSION OF SYNCHONOUS CIRCUITS

Patent #:	8661378	Issue Dt:	02/25/2014	Application #:	12570629	Filing Dt:	09/30/2009
Publication #:	US20110078644	Pub Dt:	03/31/2011
Title:	ASYCHRONOUS SYSTEM ANALYSIS

Patent #:	8222915	Issue Dt:	07/17/2012	Application #:	12768045	Filing Dt:	04/27/2010
Publication #:	US20100207658	Pub Dt:	08/19/2010
Title:	FAULT TOLERANT ASYNCHRONOUS CIRCUITS

Patent #:	8291358	Issue Dt:	10/16/2012	Application #:	12768129	Filing Dt:	04/27/2010
Publication #:	US20100205571	Pub Dt:	08/12/2010
Title:	SYNCHRONOUS TO ASYNCHRONOUS LOGIC CONVERSION

Patent #:	7932746	Issue Dt:	04/26/2011	Application #:	12793756	Filing Dt:	06/04/2010
Title:	ONE PHASE LOGIC

Patent #:	8125242	Issue Dt:	02/28/2012	Application #:	13007933	Filing Dt:	01/17/2011
Publication #:	US20110169524	Pub Dt:	07/14/2011
Title:	RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS

Patent #:	8078899	Issue Dt:	12/13/2011	Application #:	13022843	Filing Dt:	02/08/2011
Publication #:	US20110130171	Pub Dt:	06/02/2011
Title:	ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS

Patent #:	8106683	Issue Dt:	01/31/2012	Application #:	13043858	Filing Dt:	03/09/2011
Publication #:	US20110298495	Pub Dt:	12/08/2011
Title:	ONE PHASE LOGIC

Patent #:	8305124	Issue Dt:	11/06/2012	Application #:	13310382	Filing Dt:	12/02/2011
Publication #:	US20120074991	Pub Dt:	03/29/2012
Title:	RESET SIGNAL DISTRIBUTION

Patent #:	8593176	Issue Dt:	11/26/2013	Application #:	13350342	Filing Dt:	01/13/2012
Publication #:	US20120112792	Pub Dt:	05/10/2012
Title:	ONE PHASE LOGIC

Patent #:	8575959	Issue Dt:	11/05/2013	Application #:	13354117	Filing Dt:	01/19/2012
Publication #:	US20120119781	Pub Dt:	05/17/2012
Title:	RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS

Patent #:	8443315	Issue Dt:	05/14/2013	Application #:	13427041	Filing Dt:	03/22/2012
Publication #:	US20120180012	Pub Dt:	07/12/2012
Title:	RESET MECHANISM CONVERSION

Patent #:	8949759	Issue Dt:	02/03/2015	Application #:	14071159	Filing Dt:	11/04/2013
Publication #:	US20140137064	Pub Dt:	05/15/2014
Title:	RECONFIGURABLE LOGIC FABRICS FOR INTEGRATED CIRCUITS AND SYSTEMS AND METHODS FOR CONFIGURING RECONFIGURABLE LOGIC FABRICS

Patent #:	8933734	Issue Dt:	01/13/2015	Application #:	14159869	Filing Dt:	01/21/2014
Publication #:	US20140201560	Pub Dt:	07/17/2014
Title:	HIERARCHICAL GLOBAL CLOCK TREE

Patent #:	9344385	Issue Dt:	05/17/2016	Application #:	14629192	Filing Dt:	02/23/2015
Publication #:	US20150229589	Pub Dt:	08/13/2015
Title:	ASYNCHRONOUS PIPELINED INTERCONNECT ARCHITECTURE WITH FANOUT SUPPORT

Patent #:	10656915	Issue Dt:	05/19/2020	Application #:	16134576	Filing Dt:	09/18/2018
Publication #:	US20200019375	Pub Dt:	01/16/2020
Title:	EFFICIENT FPGA MULTIPLIERS

Patent #:	10831959	Issue Dt:	11/10/2020	Application #:	16363434	Filing Dt:	03/25/2019
Publication #:	US20200311219	Pub Dt:	10/01/2020
Title:	EMBEDDED FPGA TIMING SIGN-OFF

Patent #:	10608640	Issue Dt:	03/31/2020	Application #:	16409146	Filing Dt:	05/10/2019
Title:	ON-CHIP NETWORK IN PROGRAMMABLE INTEGRATED CIRCUIT

Patent #:	10707875	Issue Dt:	07/07/2020	Application #:	16409191	Filing Dt:	05/10/2019
Title:	RECONFIGURABLE PROGRAMMABLE INTEGRATED CIRCUIT WITH ON-CHIP NETWORK

Patent #:	10790830	Issue Dt:	09/29/2020	Application #:	16417152	Filing Dt:	05/20/2019
Title:	FUSED MEMORY AND ARITHMETIC CIRCUIT

Patent #:	11256476	Issue Dt:	02/22/2022	Application #:	16535878	Filing Dt:	08/08/2019
Publication #:	US20210042087	Pub Dt:	02/11/2021
Title:	Multiple Mode Arithmetic Circuit

Patent #:	11288220	Issue Dt:	03/29/2022	Application #:	16656685	Filing Dt:	10/18/2019
Publication #:	US20210117356	Pub Dt:	04/22/2021
Title:	CASCADE COMMUNICATIONS BETWEEN FPGA TILES

Patent #:	11397204	Issue Dt:	07/26/2022	Application #:	16695743	Filing Dt:	11/26/2019
Publication #:	US20210156897	Pub Dt:	05/27/2021
Title:	NOISE-INDEPENDENT LOSS CHARACTERIZATION OF NETWORKS

Assignor

ACHRONIX SEMICONDUCTOR CORPORATION

Exec Dt:

03/16/2020

Assignee

HERCULES CAPITAL, INC., AS AGENT

400 HAMILTON AVENUE, SUITE 310

PALO ALTO, CALIFORNIA 94301

Correspondence name and address
	PATTY CHENG
	2625 MIDDLEFIELD RD., #215
	PALO ALTO, CA 94306

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