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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:052557/0327   Pages: 13
Recorded: 05/04/2020
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 158
Page 1 of 2
Pages: 1 2
1
Patent #:
NONE
Issue Dt:
Application #:
09893104
Filing Dt:
06/27/2001
Publication #:
US20030008129
Pub Dt:
01/09/2003
Title:
Dielectric material and process of insulating a semiconductor device using same
2
Patent #:
NONE
Issue Dt:
Application #:
11115936
Filing Dt:
04/27/2005
Publication #:
US20060244138
Pub Dt:
11/02/2006
Title:
Techniques for improving bond pad performance
3
Patent #:
NONE
Issue Dt:
Application #:
12180882
Filing Dt:
07/28/2008
Publication #:
US20080284031
Pub Dt:
11/20/2008
Title:
METHOD FOR IMPROVED PROCESS LATITUDE BY ELONGATED VIA INTEGRATION
4
Patent #:
NONE
Issue Dt:
Application #:
12424981
Filing Dt:
04/16/2009
Publication #:
US20090194819
Pub Dt:
08/06/2009
Title:
CMOS STRUCTURES AND METHODS USING SELF-ALIGNED DUAL STRESSED LAYERS
5
Patent #:
NONE
Issue Dt:
Application #:
12606210
Filing Dt:
10/27/2009
Publication #:
US20110094557
Pub Dt:
04/28/2011
Title:
METHOD OF FORMING SEMICONDUCTOR FILM AND PHOTOVOLTAIC DEVICE INCLUDING THE FILM
6
Patent #:
NONE
Issue Dt:
Application #:
13604223
Filing Dt:
09/05/2012
Publication #:
US20130065351
Pub Dt:
03/14/2013
Title:
PHOTOVOLTAIC CELLS WITH COPPER GRID
7
Patent #:
NONE
Issue Dt:
Application #:
13774045
Filing Dt:
02/22/2013
Publication #:
US20130160705
Pub Dt:
06/27/2013
Title:
REDUCTION OF EDGE CHIPPING DURING WAFER HANDLING
8
Patent #:
NONE
Issue Dt:
Application #:
13777229
Filing Dt:
02/26/2013
Publication #:
US20140239569
Pub Dt:
08/28/2014
Title:
UNIVERSAL CLAMPING FIXTURE TO MAINTAIN LAMINATE FLATNESS DURING CHIP JOIN
9
Patent #:
NONE
Issue Dt:
Application #:
13849562
Filing Dt:
03/25/2013
Publication #:
US20130285245
Pub Dt:
10/31/2013
Title:
MICROSTRUCTURE MODIFICATION IN COPPER INTERCONNECT STRUCTURES
10
Patent #:
NONE
Issue Dt:
Application #:
14015967
Filing Dt:
08/30/2013
Publication #:
US20140306274
Pub Dt:
10/16/2014
Title:
SELF-ALIGNED STRUCTURE FOR BULK FinFET
11
Patent #:
NONE
Issue Dt:
Application #:
14024685
Filing Dt:
09/12/2013
Publication #:
US20140312576
Pub Dt:
10/23/2014
Title:
SUBSTRATE HOLDER ASSEMBLY FOR CONTROLLED LAYER TRANSFER
12
Patent #:
NONE
Issue Dt:
Application #:
14201893
Filing Dt:
03/09/2014
Publication #:
US20150255388
Pub Dt:
09/10/2015
Title:
ENHANCEMENT OF ISO-VIA RELIABILITY
13
Patent #:
NONE
Issue Dt:
Application #:
14221339
Filing Dt:
03/21/2014
Publication #:
US20150270344
Pub Dt:
09/24/2015
Title:
P-FET WITH GRADED SILICON-GERMANIUM CHANNEL
14
Patent #:
NONE
Issue Dt:
Application #:
14831900
Filing Dt:
08/21/2015
Publication #:
US20150376791
Pub Dt:
12/31/2015
Title:
GAS CLUSTER REACTOR FOR ANISOTROPIC FILM GROWTH
15
Patent #:
NONE
Issue Dt:
Application #:
14839358
Filing Dt:
08/28/2015
Publication #:
US20150371870
Pub Dt:
12/24/2015
Title:
DIE LEVEL CHEMICAL MECHANICAL POLISHING
16
Patent #:
NONE
Issue Dt:
Application #:
14856930
Filing Dt:
09/17/2015
Publication #:
US20170084454
Pub Dt:
03/23/2017
Title:
UNIFORM HEIGHT TALL FINS WITH VARYING SILICON GERMANIUM CONCENTRATIONS
17
Patent #:
NONE
Issue Dt:
Application #:
14934191
Filing Dt:
11/06/2015
Publication #:
US20160064210
Pub Dt:
03/03/2016
Title:
P-FET WITH GRADED SILICON-GERMANIUM CHANNEL
18
Patent #:
NONE
Issue Dt:
Application #:
14937968
Filing Dt:
11/11/2015
Publication #:
US20160071723
Pub Dt:
03/10/2016
Title:
GAS CLUSTER REACTOR FOR ANISOTROPIC FILM GROWTH
19
Patent #:
NONE
Issue Dt:
Application #:
15083852
Filing Dt:
03/29/2016
Publication #:
US20160365329
Pub Dt:
12/15/2016
Title:
CHIP-ON-CHIP STRUCTURE COMPRISING SINTERED PILLARS
20
Patent #:
NONE
Issue Dt:
Application #:
15157803
Filing Dt:
05/18/2016
Publication #:
US20170125338
Pub Dt:
05/04/2017
Title:
DUAL SILICIDE LINER FLOW FOR ENABLING LOW CONTACT RESISTANCE
21
Patent #:
NONE
Issue Dt:
Application #:
15206643
Filing Dt:
07/11/2016
Publication #:
US20160322226
Pub Dt:
11/03/2016
Title:
Techniques for Fabricating Reduced-Line-Edge-Roughness Trenches for Aspect Ratio Trapping
22
Patent #:
NONE
Issue Dt:
Application #:
15237235
Filing Dt:
08/15/2016
Publication #:
US20160358774
Pub Dt:
12/08/2016
Title:
SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING
23
Patent #:
10622235
Issue Dt:
04/14/2020
Application #:
15287093
Filing Dt:
10/06/2016
Publication #:
US20170025295
Pub Dt:
01/26/2017
Title:
PACKAGE ASSEMBLY FOR THIN WAFER SHIPPING AND METHOD OF USE
24
Patent #:
NONE
Issue Dt:
Application #:
15287582
Filing Dt:
10/06/2016
Publication #:
US20170146741
Pub Dt:
05/25/2017
Title:
OPTICAL DEVICE WITH PRECOATED UNDERFILL
25
Patent #:
NONE
Issue Dt:
Application #:
15288014
Filing Dt:
10/07/2016
Publication #:
US20170025305
Pub Dt:
01/26/2017
Title:
SHALLOW TRENCH ISOLATION REGIONS MADE FROM CRYSTALLINE OXIDES
26
Patent #:
10600783
Issue Dt:
03/24/2020
Application #:
15331074
Filing Dt:
10/21/2016
Publication #:
US20170040319
Pub Dt:
02/09/2017
Title:
SELF-CUT SIDEWALL IMAGE TRANSFER PROCESS
27
Patent #:
NONE
Issue Dt:
Application #:
15332656
Filing Dt:
10/24/2016
Publication #:
US20170256543
Pub Dt:
09/07/2017
Title:
WELL AND PUNCH THROUGH STOPPER FORMATION USING CONFORMAL DOPING
28
Patent #:
NONE
Issue Dt:
Application #:
15357201
Filing Dt:
11/21/2016
Publication #:
US20170069541
Pub Dt:
03/09/2017
Title:
METHOD AND STRUCTURE FOR FORMING FINFET CMOS WITH DUAL DOPED STI REGIONS
29
Patent #:
NONE
Issue Dt:
Application #:
15417907
Filing Dt:
01/27/2017
Publication #:
US20170148790
Pub Dt:
05/25/2017
Title:
Stop Layer Through Ion Implantation For Etch Stop
30
Patent #:
NONE
Issue Dt:
Application #:
15434335
Filing Dt:
02/16/2017
Publication #:
US20180090372
Pub Dt:
03/29/2018
Title:
HETEROGENEOUS METALLIZATION USING SOLID DIFFUSION REMOVAL OF METAL INTERCONNECTS
31
Patent #:
10916468
Issue Dt:
02/09/2021
Application #:
15442822
Filing Dt:
02/27/2017
Publication #:
US20170170120
Pub Dt:
06/15/2017
Title:
SEMICONDUCTOR DEVICE WITH BURIED LOCAL INTERCONNECTS
32
Patent #:
NONE
Issue Dt:
Application #:
15463877
Filing Dt:
03/20/2017
Publication #:
US20180114718
Pub Dt:
04/26/2018
Title:
BARRIER PLANARIZATION FOR INTERCONNECT METALLIZATION
33
Patent #:
10734410
Issue Dt:
08/04/2020
Application #:
15477277
Filing Dt:
04/03/2017
Publication #:
US20180076220
Pub Dt:
03/15/2018
Title:
CONDUCTIVE CONTACTS IN SEMICONDUCTOR ON INSULATOR SUBSTRATE
34
Patent #:
10714341
Issue Dt:
07/14/2020
Application #:
15591584
Filing Dt:
05/10/2017
Publication #:
US20170243743
Pub Dt:
08/24/2017
Title:
REACTIVE ION ETCHING ASSISTED LIFT-OFF PROCESSES FOR FABRICATING THICK METALLIZATION PATTERNS WITH TIGHT PITCH
35
Patent #:
10586741
Issue Dt:
03/10/2020
Application #:
15608476
Filing Dt:
05/30/2017
Publication #:
US20180122710
Pub Dt:
05/03/2018
Title:
GATE HEIGHT AND SPACER UNIFORMITY
36
Patent #:
NONE
Issue Dt:
Application #:
15639354
Filing Dt:
06/30/2017
Publication #:
US20170309729
Pub Dt:
10/26/2017
Title:
GATE PLANARITY FOR FINFET USING DUMMY POLISH STOP
37
Patent #:
NONE
Issue Dt:
Application #:
15654879
Filing Dt:
07/20/2017
Publication #:
US20170316945
Pub Dt:
11/02/2017
Title:
BOTTOM SOURCE/DRAIN SILICIDATION FOR VERTICAL FIELD-EFFECT TRANSISTOR (FET)
38
Patent #:
10629443
Issue Dt:
04/21/2020
Application #:
15654882
Filing Dt:
07/20/2017
Publication #:
US20170323794
Pub Dt:
11/09/2017
Title:
BOTTOM SOURCE/DRAIN SILICIDATION FOR VERTICAL FIELD-EFFECT TRANSISTOR (FET)
39
Patent #:
NONE
Issue Dt:
Application #:
15681476
Filing Dt:
08/21/2017
Publication #:
US20190058044
Pub Dt:
02/21/2019
Title:
FIN-TYPE FET WITH LOW SOURCE OR DRAIN CONTACT RESISTANCE
40
Patent #:
10734281
Issue Dt:
08/04/2020
Application #:
15699695
Filing Dt:
09/08/2017
Publication #:
US20180053716
Pub Dt:
02/22/2018
Title:
METHOD AND STRUCTURE TO FABRICATE A NANOPOROUS MEMBRANE
41
Patent #:
10586739
Issue Dt:
03/10/2020
Application #:
15795370
Filing Dt:
10/27/2017
Publication #:
US20180047637
Pub Dt:
02/15/2018
Title:
SELF-ALIGNED PUNCH THROUGH STOPPER LINER FOR BULK FINFET
42
Patent #:
11297717
Issue Dt:
04/05/2022
Application #:
15796121
Filing Dt:
10/27/2017
Publication #:
US20180054895
Pub Dt:
02/22/2018
Title:
POWER DECOUPLING ATTACHMENT
43
Patent #:
10615278
Issue Dt:
04/07/2020
Application #:
15796429
Filing Dt:
10/27/2017
Publication #:
US20180069027
Pub Dt:
03/08/2018
Title:
PREVENTING STRAINED FIN RELAXATION
44
Patent #:
10622259
Issue Dt:
04/14/2020
Application #:
15797208
Filing Dt:
10/30/2017
Publication #:
US20180069007
Pub Dt:
03/08/2018
Title:
SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
45
Patent #:
NONE
Issue Dt:
Application #:
15798659
Filing Dt:
10/31/2017
Publication #:
US20180204724
Pub Dt:
07/19/2018
Title:
IMAGE TRANSFER USING EUV LITHOGRAPHIC STRUCTURE AND DOUBLE PATTERNING PROCESS
46
Patent #:
10622207
Issue Dt:
04/14/2020
Application #:
15799579
Filing Dt:
10/31/2017
Publication #:
US20180053650
Pub Dt:
02/22/2018
Title:
LOW EXTERNAL RESISTANCE CHANNELS IN III-V SEMICONDUCTOR DEVICES
47
Patent #:
10573554
Issue Dt:
02/25/2020
Application #:
15802285
Filing Dt:
11/02/2017
Publication #:
US20180068892
Pub Dt:
03/08/2018
Title:
BACKSIDE CONTACT TO A FINAL SUBSTRATE
48
Patent #:
10629431
Issue Dt:
04/21/2020
Application #:
15813993
Filing Dt:
11/15/2017
Publication #:
US20180076029
Pub Dt:
03/15/2018
Title:
METHOD AND STRUCTURE FOR FORMING A DENSE ARRAY OF SINGLE CRYSTALLINE SEMICONDUCTOR NANOCRYSTALS
49
Patent #:
NONE
Issue Dt:
Application #:
15822542
Filing Dt:
11/27/2017
Publication #:
US20180114719
Pub Dt:
04/26/2018
Title:
BARRIER PLANARIZATION FOR INTERCONNECT METALLIZATION
50
Patent #:
10699951
Issue Dt:
06/30/2020
Application #:
15825573
Filing Dt:
11/29/2017
Publication #:
US20180082895
Pub Dt:
03/22/2018
Title:
SELF-ALIGNED LOW DIELECTRIC CONSTANT GATE CAP AND A METHOD OF FORMING THE SAME
51
Patent #:
10580704
Issue Dt:
03/03/2020
Application #:
15827058
Filing Dt:
11/30/2017
Publication #:
US20180090390
Pub Dt:
03/29/2018
Title:
SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
52
Patent #:
10607992
Issue Dt:
03/31/2020
Application #:
15859350
Filing Dt:
12/30/2017
Publication #:
US20180122807
Pub Dt:
05/03/2018
Title:
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
53
Patent #:
NONE
Issue Dt:
Application #:
15863675
Filing Dt:
01/05/2018
Publication #:
US20180138084
Pub Dt:
05/17/2018
Title:
ENHANCED VIA FILL MATERIAL AND PROCESSING FOR DUAL DAMASCENE INTEGRATION
54
Patent #:
10699950
Issue Dt:
06/30/2020
Application #:
15889248
Filing Dt:
02/06/2018
Publication #:
US20180158731
Pub Dt:
06/07/2018
Title:
METHOD OF OPTIMIZING WIRE RC FOR DEVICE PERFORMANCE AND RELIABILITY
55
Patent #:
NONE
Issue Dt:
Application #:
15912740
Filing Dt:
03/06/2018
Publication #:
US20180197780
Pub Dt:
07/12/2018
Title:
FIELD EFFECT TRANSISTOR INCLUDING STRAINED GERMANIUM FINS
56
Patent #:
10607838
Issue Dt:
03/31/2020
Application #:
15934006
Filing Dt:
03/23/2018
Publication #:
US20180211838
Pub Dt:
07/26/2018
Title:
WELL AND PUNCH THROUGH STOPPER FORMATION USING CONFORMAL DOPING
57
Patent #:
10593564
Issue Dt:
03/17/2020
Application #:
15951439
Filing Dt:
04/12/2018
Publication #:
US20180233381
Pub Dt:
08/16/2018
Title:
LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE
58
Patent #:
10580686
Issue Dt:
03/03/2020
Application #:
15989553
Filing Dt:
05/25/2018
Publication #:
US20180277424
Pub Dt:
09/27/2018
Title:
SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
59
Patent #:
10629589
Issue Dt:
04/21/2020
Application #:
15991143
Filing Dt:
05/29/2018
Publication #:
US20180308837
Pub Dt:
10/25/2018
Title:
RESISTOR FINS
60
Patent #:
10629482
Issue Dt:
04/21/2020
Application #:
15994965
Filing Dt:
05/31/2018
Publication #:
US20180286748
Pub Dt:
10/04/2018
Title:
BACKSIDE CONTACT TO A FINAL SUBSTRATE
61
Patent #:
NONE
Issue Dt:
Application #:
16001248
Filing Dt:
06/06/2018
Publication #:
US20180286680
Pub Dt:
10/04/2018
Title:
REMOVAL OF TRILAYER RESIST WITHOUT DAMAGE TO UNDERLYING STRUCTURE
62
Patent #:
NONE
Issue Dt:
Application #:
16014210
Filing Dt:
06/21/2018
Publication #:
US20180315591
Pub Dt:
11/01/2018
Title:
HETERO-INTEGRATION OF III-N MATERIAL ON SILICON
63
Patent #:
10755949
Issue Dt:
08/25/2020
Application #:
16016920
Filing Dt:
06/25/2018
Publication #:
US20180308708
Pub Dt:
10/25/2018
Title:
STRUCTURES, METHODS AND APPLICATIONS FOR ELECTRICAL PULSE ANNEAL PROCESSES
64
Patent #:
10734473
Issue Dt:
08/04/2020
Application #:
16019606
Filing Dt:
06/27/2018
Publication #:
US20180323255
Pub Dt:
11/08/2018
Title:
ON-CHIP MIM CAPACITOR
65
Patent #:
NONE
Issue Dt:
Application #:
16020090
Filing Dt:
06/27/2018
Publication #:
US20180308691
Pub Dt:
10/25/2018
Title:
POROUS FIN AS COMPLIANT MEDIUM TO FORM DISLOCATION-FREE HETEROEPITAXIAL FILMS
66
Patent #:
NONE
Issue Dt:
Application #:
16026209
Filing Dt:
07/03/2018
Publication #:
US20180330996
Pub Dt:
11/15/2018
Title:
FIELD EFFECT TRANSISTOR GATE STACK
67
Patent #:
NONE
Issue Dt:
Application #:
16032563
Filing Dt:
07/11/2018
Publication #:
US20180323280
Pub Dt:
11/08/2018
Title:
SELF-ALIGNED SPACER FOR CUT-LAST TRANSISTOR FABRICATION
68
Patent #:
10777433
Issue Dt:
09/15/2020
Application #:
16042331
Filing Dt:
07/23/2018
Publication #:
US20180350639
Pub Dt:
12/06/2018
Title:
GAS-CONTROLLED BONDING PLATFORM FOR EDGE DEFECT REDUCTION DURING WAFER BONDING
69
Patent #:
10693007
Issue Dt:
06/23/2020
Application #:
16045905
Filing Dt:
07/26/2018
Publication #:
US20180350991
Pub Dt:
12/06/2018
Title:
WRAPPED CONTACTS WITH ENHANCED AREA
70
Patent #:
10699955
Issue Dt:
06/30/2020
Application #:
16046080
Filing Dt:
07/26/2018
Publication #:
US20180330989
Pub Dt:
11/15/2018
Title:
Techniques for Creating a Local Interconnect Using a SOI Wafer
71
Patent #:
NONE
Issue Dt:
Application #:
16047952
Filing Dt:
07/27/2018
Publication #:
US20180342392
Pub Dt:
11/29/2018
Title:
Reducing Autodoping of III-V Semiconductors By Atomic Layer Epitaxy (ALE)
72
Patent #:
10644007
Issue Dt:
05/05/2020
Application #:
16053356
Filing Dt:
08/02/2018
Publication #:
US20180350816
Pub Dt:
12/06/2018
Title:
DECOUPLING CAPACITOR ON STRAIN RELAXATION BUFFER LAYER
73
Patent #:
10707083
Issue Dt:
07/07/2020
Application #:
16058379
Filing Dt:
08/08/2018
Publication #:
US20180374707
Pub Dt:
12/27/2018
Title:
HIGH ASPECT RATIO GATES
74
Patent #:
NONE
Issue Dt:
Application #:
16058409
Filing Dt:
08/08/2018
Publication #:
US20180350605
Pub Dt:
12/06/2018
Title:
HIGH ASPECT RATIO GATES
75
Patent #:
NONE
Issue Dt:
Application #:
16111300
Filing Dt:
08/24/2018
Publication #:
US20190013238
Pub Dt:
01/10/2019
Title:
PROTECTIVE LINER BETWEEN A GATE DIELECTRIC AND A GATE CONTACT
76
Patent #:
NONE
Issue Dt:
Application #:
16118883
Filing Dt:
08/31/2018
Publication #:
US20180374746
Pub Dt:
12/27/2018
Title:
DIFFUSION BARRIER LAYER FORMATION
77
Patent #:
10727299
Issue Dt:
07/28/2020
Application #:
16149598
Filing Dt:
10/02/2018
Publication #:
US20190043945
Pub Dt:
02/07/2019
Title:
LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE
78
Patent #:
10727121
Issue Dt:
07/28/2020
Application #:
16201448
Filing Dt:
11/27/2018
Publication #:
US20190096757
Pub Dt:
03/28/2019
Title:
THIN FILM INTERCONNECTS WITH LARGE GRAINS
79
Patent #:
NONE
Issue Dt:
Application #:
16207283
Filing Dt:
12/03/2018
Publication #:
US20190104203
Pub Dt:
04/04/2019
Title:
CLIENT-INITIATED LEADER ELECTION IN DISTRIBUTED CLIENT-SERVER SYSTEMS
80
Patent #:
10727051
Issue Dt:
07/28/2020
Application #:
16212000
Filing Dt:
12/06/2018
Publication #:
US20190109003
Pub Dt:
04/11/2019
Title:
SEMICONDUCTOR NANOWIRE FABRICATION
81
Patent #:
10600883
Issue Dt:
03/24/2020
Application #:
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Title:
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Title:
THREE-DIMENSIONAL MONOLITHIC VERTICAL FIELD EFFECT TRANSISTOR LOGIC GATES
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Title:
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Title:
ROBUST HIGH PERFORMANCE LOW HYDROGEN SILICON CARBON NITRIDE (SiCNH) DIELECTRICS FOR NANO ELECTRONIC DEVICES
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Title:
METHOD OF MANUFACTURING CHIP-ON-CHIP STRUCTURE COMPRISING SINTERTED PILLARS
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Title:
FINFETS WITH CONTROLLABLE AND ADJUSTABLE CHANNEL DOPING
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Pub Dt:
05/23/2019
Title:
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90
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04/07/2020
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02/04/2019
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06/13/2019
Title:
FORMATION OF COMMON INTERFACIAL LAYER ON Si/SiGe DUAL CHANNEL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE
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06/13/2019
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VFET METAL GATE PATTERNING FOR VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR
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Title:
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93
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Title:
SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES
94
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Title:
SELF-ALIGNED VERTICAL FIELD-EFFECT TRANSISTOR WITH EPITAXIALLY GROWN BOTTOM AND TOP SOURCE DRAIN REGIONS
95
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CONTROLLING GATE PROFILE BY INTER-LAYER DIELECTRIC (ILD) NANOLAMINATES
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16293853
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FORMATION OF FULL METAL GATE TO SUPPRESS INTERFICIAL LAYER GROWTH
100
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Title:
GATE-LAST SEMICONDUCTOR FABRICATION WITH NEGATIVE-TONE RESOLUTION ENHANCEMENT
Assignor
1
INTERNATIONAL BUSINESS MACHINES CORPORATION
Exec Dt:
03/06/2020
Assignee
1
ELPIS TECHNOLOGIES INC.
1891 ROBERSTON ROAD
SUITE 100
OTTAWA, CANADA K2H 5B7
Correspondence name and address
ELPIS TECHNOLOGIES INC.
1891 ROBERSTON ROAD
SUITE 100
OTTAWA, K2H 5B7 CANADA

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